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authorAlex Frid <afrid@nvidia.com>2017-07-25 06:18:40 -0400
committerStephen Boyd <sboyd@codeaurora.org>2017-08-31 21:43:38 -0400
commit2316a7a33408b6e7b24e9d2a9a7c24af9a012289 (patch)
tree0bc2dc4fd97f8927062274f8686d10bd164a5f23
parent6c264416c9b3dfd860aba9bcbe0ab4e0f061c0ca (diff)
clk: Don't write error code into divider register
Add a check for error returned by divider value calculation to avoid writing error code into hw register. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Fixes: bca9690b9426 ("clk: divider: Make generic for usage elsewhere") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r--drivers/clk/clk-divider.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 9bb472cccca6..4ed516cb7276 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -385,12 +385,14 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
385 unsigned long parent_rate) 385 unsigned long parent_rate)
386{ 386{
387 struct clk_divider *divider = to_clk_divider(hw); 387 struct clk_divider *divider = to_clk_divider(hw);
388 unsigned int value; 388 int value;
389 unsigned long flags = 0; 389 unsigned long flags = 0;
390 u32 val; 390 u32 val;
391 391
392 value = divider_get_val(rate, parent_rate, divider->table, 392 value = divider_get_val(rate, parent_rate, divider->table,
393 divider->width, divider->flags); 393 divider->width, divider->flags);
394 if (value < 0)
395 return value;
394 396
395 if (divider->lock) 397 if (divider->lock)
396 spin_lock_irqsave(divider->lock, flags); 398 spin_lock_irqsave(divider->lock, flags);
@@ -403,7 +405,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
403 val = clk_readl(divider->reg); 405 val = clk_readl(divider->reg);
404 val &= ~(div_mask(divider->width) << divider->shift); 406 val &= ~(div_mask(divider->width) << divider->shift);
405 } 407 }
406 val |= value << divider->shift; 408 val |= (u32)value << divider->shift;
407 clk_writel(val, divider->reg); 409 clk_writel(val, divider->reg);
408 410
409 if (divider->lock) 411 if (divider->lock)