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authorEric Anholt <eric@anholt.net>2016-09-19 04:43:18 -0400
committerEric Anholt <eric@anholt.net>2016-10-17 12:55:27 -0400
commit21ff843931b2e5a9b628ac56fd0f2e4355890096 (patch)
tree7d20dab1e4e4c8a954a7f57be76321e116343aa8
parent396a3529800af0817c6af2eb65c542588a1f7fb7 (diff)
ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.
The BCM2835-ARM-Peripherals.pdf documentation specifies what the function selects do for the pins, and there are a bunch of obvious groupings to be made. With these created, we'll be able to replace bcm2835-rpi.dtsi's main "set all of these pins to alt0" with references to specific groups we want enabled. Also add pinctrl groups for emmc and sdhost. Based on patches by Eric Anholt, with fixups by Gerd Hoffmann. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
-rw-r--r--arch/arm/boot/dts/bcm283x.dtsi203
1 files changed, 203 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 46d46d894a44..2123d0eb1890 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -132,6 +132,209 @@
132 132
133 interrupt-controller; 133 interrupt-controller;
134 #interrupt-cells = <2>; 134 #interrupt-cells = <2>;
135
136 /* Defines pin muxing groups according to
137 * BCM2835-ARM-Peripherals.pdf page 102.
138 *
139 * While each pin can have its mux selected
140 * for various functions individually, some
141 * groups only make sense to switch to a
142 * particular function together.
143 */
144 dpi_gpio0: dpi_gpio0 {
145 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
146 12 13 14 15 16 17 18 19
147 20 21 22 23 24 25 26 27>;
148 brcm,function = <BCM2835_FSEL_ALT2>;
149 };
150 emmc_gpio22: emmc_gpio22 {
151 brcm,pins = <22 23 24 25 26 27>;
152 brcm,function = <BCM2835_FSEL_ALT3>;
153 };
154 emmc_gpio34: emmc_gpio34 {
155 brcm,pins = <34 35 36 37 38 39>;
156 brcm,function = <BCM2835_FSEL_ALT3>;
157 brcm,pull = <BCM2835_PUD_OFF
158 BCM2835_PUD_UP
159 BCM2835_PUD_UP
160 BCM2835_PUD_UP
161 BCM2835_PUD_UP
162 BCM2835_PUD_UP>;
163 };
164 emmc_gpio48: emmc_gpio48 {
165 brcm,pins = <48 49 50 51 52 53>;
166 brcm,function = <BCM2835_FSEL_ALT3>;
167 };
168
169 gpclk0_gpio4: gpclk0_gpio4 {
170 brcm,pins = <4>;
171 brcm,function = <BCM2835_FSEL_ALT0>;
172 };
173 gpclk1_gpio5: gpclk1_gpio5 {
174 brcm,pins = <5>;
175 brcm,function = <BCM2835_FSEL_ALT0>;
176 };
177 gpclk1_gpio42: gpclk1_gpio42 {
178 brcm,pins = <42>;
179 brcm,function = <BCM2835_FSEL_ALT0>;
180 };
181 gpclk1_gpio44: gpclk1_gpio44 {
182 brcm,pins = <44>;
183 brcm,function = <BCM2835_FSEL_ALT0>;
184 };
185 gpclk2_gpio6: gpclk2_gpio6 {
186 brcm,pins = <6>;
187 brcm,function = <BCM2835_FSEL_ALT0>;
188 };
189 gpclk2_gpio43: gpclk2_gpio43 {
190 brcm,pins = <43>;
191 brcm,function = <BCM2835_FSEL_ALT0>;
192 };
193
194 i2c0_gpio0: i2c0_gpio0 {
195 brcm,pins = <0 1>;
196 brcm,function = <BCM2835_FSEL_ALT0>;
197 };
198 i2c0_gpio32: i2c0_gpio32 {
199 brcm,pins = <32 34>;
200 brcm,function = <BCM2835_FSEL_ALT0>;
201 };
202 i2c0_gpio44: i2c0_gpio44 {
203 brcm,pins = <44 45>;
204 brcm,function = <BCM2835_FSEL_ALT1>;
205 };
206 i2c1_gpio2: i2c1_gpio2 {
207 brcm,pins = <2 3>;
208 brcm,function = <BCM2835_FSEL_ALT0>;
209 };
210 i2c1_gpio44: i2c1_gpio44 {
211 brcm,pins = <44 45>;
212 brcm,function = <BCM2835_FSEL_ALT2>;
213 };
214 i2c_slave_gpio18: i2c_slave_gpio18 {
215 brcm,pins = <18 19 20 21>;
216 brcm,function = <BCM2835_FSEL_ALT3>;
217 };
218
219 jtag_gpio4: jtag_gpio4 {
220 brcm,pins = <4 5 6 12 13>;
221 brcm,function = <BCM2835_FSEL_ALT4>;
222 };
223 jtag_gpio22: jtag_gpio22 {
224 brcm,pins = <22 23 24 25 26 27>;
225 brcm,function = <BCM2835_FSEL_ALT4>;
226 };
227
228 pcm_gpio18: pcm_gpio18 {
229 brcm,pins = <18 19 20 21>;
230 brcm,function = <BCM2835_FSEL_ALT0>;
231 };
232 pcm_gpio28: pcm_gpio28 {
233 brcm,pins = <28 29 30 31>;
234 brcm,function = <BCM2835_FSEL_ALT2>;
235 };
236
237 pwm0_gpio12: pwm0_gpio12 {
238 brcm,pins = <12>;
239 brcm,function = <BCM2835_FSEL_ALT0>;
240 };
241 pwm0_gpio18: pwm0_gpio18 {
242 brcm,pins = <18>;
243 brcm,function = <BCM2835_FSEL_ALT5>;
244 };
245 pwm0_gpio40: pwm0_gpio40 {
246 brcm,pins = <40>;
247 brcm,function = <BCM2835_FSEL_ALT0>;
248 };
249 pwm1_gpio13: pwm1_gpio13 {
250 brcm,pins = <13>;
251 brcm,function = <BCM2835_FSEL_ALT0>;
252 };
253 pwm1_gpio19: pwm1_gpio19 {
254 brcm,pins = <19>;
255 brcm,function = <BCM2835_FSEL_ALT5>;
256 };
257 pwm1_gpio41: pwm1_gpio41 {
258 brcm,pins = <41>;
259 brcm,function = <BCM2835_FSEL_ALT0>;
260 };
261 pwm1_gpio45: pwm1_gpio45 {
262 brcm,pins = <45>;
263 brcm,function = <BCM2835_FSEL_ALT0>;
264 };
265
266 sdhost_gpio48: sdhost_gpio48 {
267 brcm,pins = <48 49 50 51 52 53>;
268 brcm,function = <BCM2835_FSEL_ALT0>;
269 };
270
271 spi0_gpio7: spi0_gpio7 {
272 brcm,pins = <7 8 9 10 11>;
273 brcm,function = <BCM2835_FSEL_ALT0>;
274 };
275 spi0_gpio35: spi0_gpio35 {
276 brcm,pins = <35 36 37 38 39>;
277 brcm,function = <BCM2835_FSEL_ALT0>;
278 };
279 spi1_gpio16: spi1_gpio16 {
280 brcm,pins = <16 17 18 19 20 21>;
281 brcm,function = <BCM2835_FSEL_ALT4>;
282 };
283 spi2_gpio40: spi2_gpio40 {
284 brcm,pins = <40 41 42 43 44 45>;
285 brcm,function = <BCM2835_FSEL_ALT4>;
286 };
287
288 uart0_gpio14: uart0_gpio14 {
289 brcm,pins = <14 15>;
290 brcm,function = <BCM2835_FSEL_ALT0>;
291 };
292 /* Separate from the uart0_gpio14 group
293 * because it conflicts with spi1_gpio16, and
294 * people often run uart0 on the two pins
295 * without flow contrl.
296 */
297 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
298 brcm,pins = <16 17>;
299 brcm,function = <BCM2835_FSEL_ALT3>;
300 };
301 uart0_gpio30: uart0_gpio30 {
302 brcm,pins = <30 31>;
303 brcm,function = <BCM2835_FSEL_ALT3>;
304 };
305 uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
306 brcm,pins = <32 33>;
307 brcm,function = <BCM2835_FSEL_ALT3>;
308 };
309
310 uart1_gpio14: uart1_gpio14 {
311 brcm,pins = <14 15>;
312 brcm,function = <BCM2835_FSEL_ALT5>;
313 };
314 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
315 brcm,pins = <16 17>;
316 brcm,function = <BCM2835_FSEL_ALT5>;
317 };
318 uart1_gpio32: uart1_gpio32 {
319 brcm,pins = <32 33>;
320 brcm,function = <BCM2835_FSEL_ALT5>;
321 };
322 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
323 brcm,pins = <30 31>;
324 brcm,function = <BCM2835_FSEL_ALT5>;
325 };
326 uart1_gpio36: uart1_gpio36 {
327 brcm,pins = <36 37 38 39>;
328 brcm,function = <BCM2835_FSEL_ALT2>;
329 };
330 uart1_gpio40: uart1_gpio40 {
331 brcm,pins = <40 41>;
332 brcm,function = <BCM2835_FSEL_ALT5>;
333 };
334 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
335 brcm,pins = <42 43>;
336 brcm,function = <BCM2835_FSEL_ALT5>;
337 };
135 }; 338 };
136 339
137 uart0: serial@7e201000 { 340 uart0: serial@7e201000 {