aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorVinod Koul <vinod.koul@intel.com>2018-01-31 03:21:11 -0500
committerVinod Koul <vinod.koul@intel.com>2018-01-31 03:21:11 -0500
commit21359a84a0e1467fcb2704ffbdb52c063e38630b (patch)
tree6cac890f713628d8f59a08ef79ce53e26f2d8dbc
parent6811837d5332aa7312d901533ff89985d6ab9df2 (diff)
parentf6160f359846408056c2646f1dbb4ea098930fee (diff)
Merge branch 'topic/tegra' into for-linus
-rw-r--r--drivers/dma/tegra20-apb-dma.c19
1 files changed, 14 insertions, 5 deletions
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index b9d75a54c896..9a558e30c461 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -353,7 +353,8 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
353 } 353 }
354 354
355 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); 355 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
356 if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID) { 356 if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID &&
357 sconfig->device_fc) {
357 if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK) 358 if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
358 return -EINVAL; 359 return -EINVAL;
359 tdc->slave_id = sconfig->slave_id; 360 tdc->slave_id = sconfig->slave_id;
@@ -970,8 +971,13 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
970 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT; 971 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
971 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32; 972 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
972 973
973 csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW; 974 csr |= TEGRA_APBDMA_CSR_ONCE;
974 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; 975
976 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
977 csr |= TEGRA_APBDMA_CSR_FLOW;
978 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
979 }
980
975 if (flags & DMA_PREP_INTERRUPT) 981 if (flags & DMA_PREP_INTERRUPT)
976 csr |= TEGRA_APBDMA_CSR_IE_EOC; 982 csr |= TEGRA_APBDMA_CSR_IE_EOC;
977 983
@@ -1110,10 +1116,13 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1110 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT; 1116 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1111 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32; 1117 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1112 1118
1113 csr |= TEGRA_APBDMA_CSR_FLOW; 1119 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
1120 csr |= TEGRA_APBDMA_CSR_FLOW;
1121 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1122 }
1123
1114 if (flags & DMA_PREP_INTERRUPT) 1124 if (flags & DMA_PREP_INTERRUPT)
1115 csr |= TEGRA_APBDMA_CSR_IE_EOC; 1125 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1116 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1117 1126
1118 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1; 1127 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1119 1128