diff options
author | Jani Nikula <jani.nikula@intel.com> | 2015-06-26 07:18:56 -0400 |
---|---|---|
committer | Jani Nikula <jani.nikula@intel.com> | 2015-06-29 07:31:04 -0400 |
commit | 2059ac3b1304cb6a82f9d90762dea9f556831627 (patch) | |
tree | 1d92db32fa4e603dafadf47f86946bfdb48cafd2 | |
parent | 8b572a4200828b4e75cc22ed2f494b58d5372d65 (diff) |
drm/i915: fix backlight after resume on 855gm
Some 855gm models (at least ThinkPad X40) regressed because of
commit b0cd324faed23d10d66ba6ade66579c681feef6f
Author: Jani Nikula <jani.nikula@intel.com>
Date: Wed Nov 12 16:25:43 2014 +0200
drm/i915: don't save/restore backlight hist ctl registers
which tried to make our driver more robust by not blindly saving and
restoring registers, but it failed to take into account
commit 0eb96d6ed38430b72897adde58f5477a6b71757a
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Wed Oct 14 12:33:41 2009 -0700
drm/i915: save/restore BLC histogram control reg across suspend/resume
Fix the regression by enabling hist ctl on gen2.
v2: Improved the comment.
v3: Improved the comment, again.
Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net>
References: http://mid.gmane.org/20150623222648.GD12335@acheron
Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_panel.c | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6d3fead3a358..47bb110a5e36 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -3491,6 +3491,7 @@ enum skl_disp_power_wells { | |||
3491 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ | 3491 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
3492 | 3492 | ||
3493 | #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) | 3493 | #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) |
3494 | #define BLM_HISTOGRAM_ENABLE (1 << 31) | ||
3494 | 3495 | ||
3495 | /* New registers for PCH-split platforms. Safe where new bits show up, the | 3496 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
3496 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ | 3497 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ |
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 7d83527f95f7..55aad2322e10 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c | |||
@@ -907,6 +907,14 @@ static void i9xx_enable_backlight(struct intel_connector *connector) | |||
907 | 907 | ||
908 | /* XXX: combine this into above write? */ | 908 | /* XXX: combine this into above write? */ |
909 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | 909 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
910 | |||
911 | /* | ||
912 | * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is | ||
913 | * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2 | ||
914 | * that has backlight. | ||
915 | */ | ||
916 | if (IS_GEN2(dev)) | ||
917 | I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); | ||
910 | } | 918 | } |
911 | 919 | ||
912 | static void i965_enable_backlight(struct intel_connector *connector) | 920 | static void i965_enable_backlight(struct intel_connector *connector) |