usb: chipidea: Add support for 'phy-clkgate-delay-us' property

Add support for the optional 'phy-clkgate-delay-us' property that is
used to describe the delay time between putting PHY into low power mode
and turning off the PHY clock.

Signed-off-by: Li Jun <jun.li@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>

2 files changed, 8 insertions, 0 deletions

diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 573c2876b263..f4fd76ab3aef 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -688,6 +688,10 @@ static int ci_get_platdata(struct device *dev,
         if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
                 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
 
+        if (of_find_property(dev->of_node, "phy-clkgate-delay-us", NULL))
+                of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
+                                     &platdata->phy_clkgate_delay_us);
+
         platdata->itc_setting = 1;
         if (of_find_property(dev->of_node, "itc-setting", NULL)) {
                 ret = of_property_read_u32(dev->of_node, "itc-setting",
@@ -1121,6 +1125,9 @@ static void ci_controller_suspend(struct ci_hdrc *ci)
 {
         disable_irq(ci->irq);
         ci_hdrc_enter_lpm(ci, true);
+        if (ci->platdata->phy_clkgate_delay_us)
+                usleep_range(ci->platdata->phy_clkgate_delay_us,
+                             ci->platdata->phy_clkgate_delay_us + 50);
         usb_phy_set_suspend(ci->usb_phy, 1);
         ci->in_lpm = true;
         enable_irq(ci->irq);
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
index c5cddc6901d0..5dd75fa47dd8 100644
--- a/include/linux/usb/chipidea.h
+++ b/include/linux/usb/chipidea.h
@@ -71,6 +71,7 @@ struct ci_hdrc_platform_data {
         /* VBUS and ID signal state tracking, using extcon framework */
         struct ci_hdrc_cable            vbus_extcon;
         struct ci_hdrc_cable            id_extcon;
+        u32                     phy_clkgate_delay_us;
 };
 
 /* Default offset of capability registers */