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authorAndi Kleen <ak@linux.intel.com>2016-10-05 12:53:11 -0400
committerArnaldo Carvalho de Melo <acme@redhat.com>2016-10-17 12:39:47 -0400
commit1fbd54b2e2356659f9f87920dc514792db6ff602 (patch)
tree1a67fc0e79ddb6a1ba024d93063f98325d2b9d2f
parent01dd25455b3588431d3f59c70e7b934a91d66121 (diff)
perf vendor events: Add WestmereEX V2 event file
Add a Intel event file for perf. Signed-off-by: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-2comz45lmusdf8i0n2va1ul5@git.kernel.org [ Lowercased the directory and file names ] Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat
-rw-r--r--tools/perf/pmu-events/arch/x86/mapfile.csv1
-rw-r--r--tools/perf/pmu-events/arch/x86/westmereex/cache.json3225
-rw-r--r--tools/perf/pmu-events/arch/x86/westmereex/floating-point.json229
-rw-r--r--tools/perf/pmu-events/arch/x86/westmereex/frontend.json26
-rw-r--r--tools/perf/pmu-events/arch/x86/westmereex/memory.json747
-rw-r--r--tools/perf/pmu-events/arch/x86/westmereex/other.json287
-rw-r--r--tools/perf/pmu-events/arch/x86/westmereex/pipeline.json905
-rw-r--r--tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json173
8 files changed, 5593 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 01453bc560d2..12181bb1da2a 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -32,3 +32,4 @@ GenuineIntel-6-2A,v15,sandybridge,core
32GenuineIntel-6-2C,v2,westmereep-dp,core 32GenuineIntel-6-2C,v2,westmereep-dp,core
33GenuineIntel-6-2C,v2,westmereep-dp,core 33GenuineIntel-6-2C,v2,westmereep-dp,core
34GenuineIntel-6-25,v2,westmereep-sp,core 34GenuineIntel-6-25,v2,westmereep-sp,core
35GenuineIntel-6-2F,v2,westmereex,core
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/cache.json b/tools/perf/pmu-events/arch/x86/westmereex/cache.json
new file mode 100644
index 000000000000..f9bc7fdd48d6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/westmereex/cache.json
@@ -0,0 +1,3225 @@
1[
2 {
3 "EventCode": "0x63",
4 "Counter": "0,1",
5 "UMask": "0x2",
6 "EventName": "CACHE_LOCK_CYCLES.L1D",
7 "SampleAfterValue": "2000000",
8 "BriefDescription": "Cycles L1D locked"
9 },
10 {
11 "EventCode": "0x63",
12 "Counter": "0,1",
13 "UMask": "0x1",
14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
15 "SampleAfterValue": "2000000",
16 "BriefDescription": "Cycles L1D and L2 locked"
17 },
18 {
19 "EventCode": "0x51",
20 "Counter": "0,1",
21 "UMask": "0x4",
22 "EventName": "L1D.M_EVICT",
23 "SampleAfterValue": "2000000",
24 "BriefDescription": "L1D cache lines replaced in M state"
25 },
26 {
27 "EventCode": "0x51",
28 "Counter": "0,1",
29 "UMask": "0x2",
30 "EventName": "L1D.M_REPL",
31 "SampleAfterValue": "2000000",
32 "BriefDescription": "L1D cache lines allocated in the M state"
33 },
34 {
35 "EventCode": "0x51",
36 "Counter": "0,1",
37 "UMask": "0x8",
38 "EventName": "L1D.M_SNOOP_EVICT",
39 "SampleAfterValue": "2000000",
40 "BriefDescription": "L1D snoop eviction of cache lines in M state"
41 },
42 {
43 "EventCode": "0x51",
44 "Counter": "0,1",
45 "UMask": "0x1",
46 "EventName": "L1D.REPL",
47 "SampleAfterValue": "2000000",
48 "BriefDescription": "L1 data cache lines allocated"
49 },
50 {
51 "EventCode": "0x52",
52 "Counter": "0,1",
53 "UMask": "0x1",
54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
55 "SampleAfterValue": "2000000",
56 "BriefDescription": "L1D prefetch load lock accepted in fill buffer"
57 },
58 {
59 "EventCode": "0x4E",
60 "Counter": "0,1",
61 "UMask": "0x2",
62 "EventName": "L1D_PREFETCH.MISS",
63 "SampleAfterValue": "200000",
64 "BriefDescription": "L1D hardware prefetch misses"
65 },
66 {
67 "EventCode": "0x4E",
68 "Counter": "0,1",
69 "UMask": "0x1",
70 "EventName": "L1D_PREFETCH.REQUESTS",
71 "SampleAfterValue": "200000",
72 "BriefDescription": "L1D hardware prefetch requests"
73 },
74 {
75 "EventCode": "0x4E",
76 "Counter": "0,1",
77 "UMask": "0x4",
78 "EventName": "L1D_PREFETCH.TRIGGERS",
79 "SampleAfterValue": "200000",
80 "BriefDescription": "L1D hardware prefetch requests triggered"
81 },
82 {
83 "EventCode": "0x28",
84 "Counter": "0,1,2,3",
85 "UMask": "0x4",
86 "EventName": "L1D_WB_L2.E_STATE",
87 "SampleAfterValue": "100000",
88 "BriefDescription": "L1 writebacks to L2 in E state"
89 },
90 {
91 "EventCode": "0x28",
92 "Counter": "0,1,2,3",
93 "UMask": "0x1",
94 "EventName": "L1D_WB_L2.I_STATE",
95 "SampleAfterValue": "100000",
96 "BriefDescription": "L1 writebacks to L2 in I state (misses)"
97 },
98 {
99 "EventCode": "0x28",
100 "Counter": "0,1,2,3",
101 "UMask": "0x8",
102 "EventName": "L1D_WB_L2.M_STATE",
103 "SampleAfterValue": "100000",
104 "BriefDescription": "L1 writebacks to L2 in M state"
105 },
106 {
107 "EventCode": "0x28",
108 "Counter": "0,1,2,3",
109 "UMask": "0xf",
110 "EventName": "L1D_WB_L2.MESI",
111 "SampleAfterValue": "100000",
112 "BriefDescription": "All L1 writebacks to L2"
113 },
114 {
115 "EventCode": "0x28",
116 "Counter": "0,1,2,3",
117 "UMask": "0x2",
118 "EventName": "L1D_WB_L2.S_STATE",
119 "SampleAfterValue": "100000",
120 "BriefDescription": "L1 writebacks to L2 in S state"
121 },
122 {
123 "EventCode": "0x26",
124 "Counter": "0,1,2,3",
125 "UMask": "0xff",
126 "EventName": "L2_DATA_RQSTS.ANY",
127 "SampleAfterValue": "200000",
128 "BriefDescription": "All L2 data requests"
129 },
130 {
131 "EventCode": "0x26",
132 "Counter": "0,1,2,3",
133 "UMask": "0x4",
134 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
135 "SampleAfterValue": "200000",
136 "BriefDescription": "L2 data demand loads in E state"
137 },
138 {
139 "EventCode": "0x26",
140 "Counter": "0,1,2,3",
141 "UMask": "0x1",
142 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
143 "SampleAfterValue": "200000",
144 "BriefDescription": "L2 data demand loads in I state (misses)"
145 },
146 {
147 "EventCode": "0x26",
148 "Counter": "0,1,2,3",
149 "UMask": "0x8",
150 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
151 "SampleAfterValue": "200000",
152 "BriefDescription": "L2 data demand loads in M state"
153 },
154 {
155 "EventCode": "0x26",
156 "Counter": "0,1,2,3",
157 "UMask": "0xf",
158 "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
159 "SampleAfterValue": "200000",
160 "BriefDescription": "L2 data demand requests"
161 },
162 {
163 "EventCode": "0x26",
164 "Counter": "0,1,2,3",
165 "UMask": "0x2",
166 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
167 "SampleAfterValue": "200000",
168 "BriefDescription": "L2 data demand loads in S state"
169 },
170 {
171 "EventCode": "0x26",
172 "Counter": "0,1,2,3",
173 "UMask": "0x40",
174 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
175 "SampleAfterValue": "200000",
176 "BriefDescription": "L2 data prefetches in E state"
177 },
178 {
179 "EventCode": "0x26",
180 "Counter": "0,1,2,3",
181 "UMask": "0x10",
182 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
183 "SampleAfterValue": "200000",
184 "BriefDescription": "L2 data prefetches in the I state (misses)"
185 },
186 {
187 "EventCode": "0x26",
188 "Counter": "0,1,2,3",
189 "UMask": "0x80",
190 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
191 "SampleAfterValue": "200000",
192 "BriefDescription": "L2 data prefetches in M state"
193 },
194 {
195 "EventCode": "0x26",
196 "Counter": "0,1,2,3",
197 "UMask": "0xf0",
198 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
199 "SampleAfterValue": "200000",
200 "BriefDescription": "All L2 data prefetches"
201 },
202 {
203 "EventCode": "0x26",
204 "Counter": "0,1,2,3",
205 "UMask": "0x20",
206 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
207 "SampleAfterValue": "200000",
208 "BriefDescription": "L2 data prefetches in the S state"
209 },
210 {
211 "EventCode": "0xF1",
212 "Counter": "0,1,2,3",
213 "UMask": "0x7",
214 "EventName": "L2_LINES_IN.ANY",
215 "SampleAfterValue": "100000",
216 "BriefDescription": "L2 lines alloacated"
217 },
218 {
219 "EventCode": "0xF1",
220 "Counter": "0,1,2,3",
221 "UMask": "0x4",
222 "EventName": "L2_LINES_IN.E_STATE",
223 "SampleAfterValue": "100000",
224 "BriefDescription": "L2 lines allocated in the E state"
225 },
226 {
227 "EventCode": "0xF1",
228 "Counter": "0,1,2,3",
229 "UMask": "0x2",
230 "EventName": "L2_LINES_IN.S_STATE",
231 "SampleAfterValue": "100000",
232 "BriefDescription": "L2 lines allocated in the S state"
233 },
234 {
235 "EventCode": "0xF2",
236 "Counter": "0,1,2,3",
237 "UMask": "0xf",
238 "EventName": "L2_LINES_OUT.ANY",
239 "SampleAfterValue": "100000",
240 "BriefDescription": "L2 lines evicted"
241 },
242 {
243 "EventCode": "0xF2",
244 "Counter": "0,1,2,3",
245 "UMask": "0x1",
246 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
247 "SampleAfterValue": "100000",
248 "BriefDescription": "L2 lines evicted by a demand request"
249 },
250 {
251 "EventCode": "0xF2",
252 "Counter": "0,1,2,3",
253 "UMask": "0x2",
254 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
255 "SampleAfterValue": "100000",
256 "BriefDescription": "L2 modified lines evicted by a demand request"
257 },
258 {
259 "EventCode": "0xF2",
260 "Counter": "0,1,2,3",
261 "UMask": "0x4",
262 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
263 "SampleAfterValue": "100000",
264 "BriefDescription": "L2 lines evicted by a prefetch request"
265 },
266 {
267 "EventCode": "0xF2",
268 "Counter": "0,1,2,3",
269 "UMask": "0x8",
270 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
271 "SampleAfterValue": "100000",
272 "BriefDescription": "L2 modified lines evicted by a prefetch request"
273 },
274 {
275 "EventCode": "0x24",
276 "Counter": "0,1,2,3",
277 "UMask": "0x10",
278 "EventName": "L2_RQSTS.IFETCH_HIT",
279 "SampleAfterValue": "200000",
280 "BriefDescription": "L2 instruction fetch hits"
281 },
282 {
283 "EventCode": "0x24",
284 "Counter": "0,1,2,3",
285 "UMask": "0x20",
286 "EventName": "L2_RQSTS.IFETCH_MISS",
287 "SampleAfterValue": "200000",
288 "BriefDescription": "L2 instruction fetch misses"
289 },
290 {
291 "EventCode": "0x24",
292 "Counter": "0,1,2,3",
293 "UMask": "0x30",
294 "EventName": "L2_RQSTS.IFETCHES",
295 "SampleAfterValue": "200000",
296 "BriefDescription": "L2 instruction fetches"
297 },
298 {
299 "EventCode": "0x24",
300 "Counter": "0,1,2,3",
301 "UMask": "0x1",
302 "EventName": "L2_RQSTS.LD_HIT",
303 "SampleAfterValue": "200000",
304 "BriefDescription": "L2 load hits"
305 },
306 {
307 "EventCode": "0x24",
308 "Counter": "0,1,2,3",
309 "UMask": "0x2",
310 "EventName": "L2_RQSTS.LD_MISS",
311 "SampleAfterValue": "200000",
312 "BriefDescription": "L2 load misses"
313 },
314 {
315 "EventCode": "0x24",
316 "Counter": "0,1,2,3",
317 "UMask": "0x3",
318 "EventName": "L2_RQSTS.LOADS",
319 "SampleAfterValue": "200000",
320 "BriefDescription": "L2 requests"
321 },
322 {
323 "EventCode": "0x24",
324 "Counter": "0,1,2,3",
325 "UMask": "0xaa",
326 "EventName": "L2_RQSTS.MISS",
327 "SampleAfterValue": "200000",
328 "BriefDescription": "All L2 misses"
329 },
330 {
331 "EventCode": "0x24",
332 "Counter": "0,1,2,3",
333 "UMask": "0x40",
334 "EventName": "L2_RQSTS.PREFETCH_HIT",
335 "SampleAfterValue": "200000",
336 "BriefDescription": "L2 prefetch hits"
337 },
338 {
339 "EventCode": "0x24",
340 "Counter": "0,1,2,3",
341 "UMask": "0x80",
342 "EventName": "L2_RQSTS.PREFETCH_MISS",
343 "SampleAfterValue": "200000",
344 "BriefDescription": "L2 prefetch misses"
345 },
346 {
347 "EventCode": "0x24",
348 "Counter": "0,1,2,3",
349 "UMask": "0xc0",
350 "EventName": "L2_RQSTS.PREFETCHES",
351 "SampleAfterValue": "200000",
352 "BriefDescription": "All L2 prefetches"
353 },
354 {
355 "EventCode": "0x24",
356 "Counter": "0,1,2,3",
357 "UMask": "0xff",
358 "EventName": "L2_RQSTS.REFERENCES",
359 "SampleAfterValue": "200000",
360 "BriefDescription": "All L2 requests"
361 },
362 {
363 "EventCode": "0x24",
364 "Counter": "0,1,2,3",
365 "UMask": "0x4",
366 "EventName": "L2_RQSTS.RFO_HIT",
367 "SampleAfterValue": "200000",
368 "BriefDescription": "L2 RFO hits"
369 },
370 {
371 "EventCode": "0x24",
372 "Counter": "0,1,2,3",
373 "UMask": "0x8",
374 "EventName": "L2_RQSTS.RFO_MISS",
375 "SampleAfterValue": "200000",
376 "BriefDescription": "L2 RFO misses"
377 },
378 {
379 "EventCode": "0x24",
380 "Counter": "0,1,2,3",
381 "UMask": "0xc",
382 "EventName": "L2_RQSTS.RFOS",
383 "SampleAfterValue": "200000",
384 "BriefDescription": "L2 RFO requests"
385 },
386 {
387 "EventCode": "0xF0",
388 "Counter": "0,1,2,3",
389 "UMask": "0x80",
390 "EventName": "L2_TRANSACTIONS.ANY",
391 "SampleAfterValue": "200000",
392 "BriefDescription": "All L2 transactions"
393 },
394 {
395 "EventCode": "0xF0",
396 "Counter": "0,1,2,3",
397 "UMask": "0x20",
398 "EventName": "L2_TRANSACTIONS.FILL",
399 "SampleAfterValue": "200000",
400 "BriefDescription": "L2 fill transactions"
401 },
402 {
403 "EventCode": "0xF0",
404 "Counter": "0,1,2,3",
405 "UMask": "0x4",
406 "EventName": "L2_TRANSACTIONS.IFETCH",
407 "SampleAfterValue": "200000",
408 "BriefDescription": "L2 instruction fetch transactions"
409 },
410 {
411 "EventCode": "0xF0",
412 "Counter": "0,1,2,3",
413 "UMask": "0x10",
414 "EventName": "L2_TRANSACTIONS.L1D_WB",
415 "SampleAfterValue": "200000",
416 "BriefDescription": "L1D writeback to L2 transactions"
417 },
418 {
419 "EventCode": "0xF0",
420 "Counter": "0,1,2,3",
421 "UMask": "0x1",
422 "EventName": "L2_TRANSACTIONS.LOAD",
423 "SampleAfterValue": "200000",
424 "BriefDescription": "L2 Load transactions"
425 },
426 {
427 "EventCode": "0xF0",
428 "Counter": "0,1,2,3",
429 "UMask": "0x8",
430 "EventName": "L2_TRANSACTIONS.PREFETCH",
431 "SampleAfterValue": "200000",
432 "BriefDescription": "L2 prefetch transactions"
433 },
434 {
435 "EventCode": "0xF0",
436 "Counter": "0,1,2,3",
437 "UMask": "0x2",
438 "EventName": "L2_TRANSACTIONS.RFO",
439 "SampleAfterValue": "200000",
440 "BriefDescription": "L2 RFO transactions"
441 },
442 {
443 "EventCode": "0xF0",
444 "Counter": "0,1,2,3",
445 "UMask": "0x40",
446 "EventName": "L2_TRANSACTIONS.WB",
447 "SampleAfterValue": "200000",
448 "BriefDescription": "L2 writeback to LLC transactions"
449 },
450 {
451 "EventCode": "0x27",
452 "Counter": "0,1,2,3",
453 "UMask": "0x40",
454 "EventName": "L2_WRITE.LOCK.E_STATE",
455 "SampleAfterValue": "100000",
456 "BriefDescription": "L2 demand lock RFOs in E state"
457 },
458 {
459 "EventCode": "0x27",
460 "Counter": "0,1,2,3",
461 "UMask": "0xe0",
462 "EventName": "L2_WRITE.LOCK.HIT",
463 "SampleAfterValue": "100000",
464 "BriefDescription": "All demand L2 lock RFOs that hit the cache"
465 },
466 {
467 "EventCode": "0x27",
468 "Counter": "0,1,2,3",
469 "UMask": "0x10",
470 "EventName": "L2_WRITE.LOCK.I_STATE",
471 "SampleAfterValue": "100000",
472 "BriefDescription": "L2 demand lock RFOs in I state (misses)"
473 },
474 {
475 "EventCode": "0x27",
476 "Counter": "0,1,2,3",
477 "UMask": "0x80",
478 "EventName": "L2_WRITE.LOCK.M_STATE",
479 "SampleAfterValue": "100000",
480 "BriefDescription": "L2 demand lock RFOs in M state"
481 },
482 {
483 "EventCode": "0x27",
484 "Counter": "0,1,2,3",
485 "UMask": "0xf0",
486 "EventName": "L2_WRITE.LOCK.MESI",
487 "SampleAfterValue": "100000",
488 "BriefDescription": "All demand L2 lock RFOs"
489 },
490 {
491 "EventCode": "0x27",
492 "Counter": "0,1,2,3",
493 "UMask": "0x20",
494 "EventName": "L2_WRITE.LOCK.S_STATE",
495 "SampleAfterValue": "100000",
496 "BriefDescription": "L2 demand lock RFOs in S state"
497 },
498 {
499 "EventCode": "0x27",
500 "Counter": "0,1,2,3",
501 "UMask": "0xe",
502 "EventName": "L2_WRITE.RFO.HIT",
503 "SampleAfterValue": "100000",
504 "BriefDescription": "All L2 demand store RFOs that hit the cache"
505 },
506 {
507 "EventCode": "0x27",
508 "Counter": "0,1,2,3",
509 "UMask": "0x1",
510 "EventName": "L2_WRITE.RFO.I_STATE",
511 "SampleAfterValue": "100000",
512 "BriefDescription": "L2 demand store RFOs in I state (misses)"
513 },
514 {
515 "EventCode": "0x27",
516 "Counter": "0,1,2,3",
517 "UMask": "0x8",
518 "EventName": "L2_WRITE.RFO.M_STATE",
519 "SampleAfterValue": "100000",
520 "BriefDescription": "L2 demand store RFOs in M state"
521 },
522 {
523 "EventCode": "0x27",
524 "Counter": "0,1,2,3",
525 "UMask": "0xf",
526 "EventName": "L2_WRITE.RFO.MESI",
527 "SampleAfterValue": "100000",
528 "BriefDescription": "All L2 demand store RFOs"
529 },
530 {
531 "EventCode": "0x27",
532 "Counter": "0,1,2,3",
533 "UMask": "0x2",
534 "EventName": "L2_WRITE.RFO.S_STATE",
535 "SampleAfterValue": "100000",
536 "BriefDescription": "L2 demand store RFOs in S state"
537 },
538 {
539 "EventCode": "0x2E",
540 "Counter": "0,1,2,3",
541 "UMask": "0x41",
542 "EventName": "LONGEST_LAT_CACHE.MISS",
543 "SampleAfterValue": "100000",
544 "BriefDescription": "Longest latency cache miss"
545 },
546 {
547 "EventCode": "0x2E",
548 "Counter": "0,1,2,3",
549 "UMask": "0x4f",
550 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
551 "SampleAfterValue": "200000",
552 "BriefDescription": "Longest latency cache reference"
553 },
554 {
555 "PEBS": "1",
556 "EventCode": "0xB",
557 "Counter": "0,1,2,3",
558 "UMask": "0x1",
559 "EventName": "MEM_INST_RETIRED.LOADS",
560 "SampleAfterValue": "2000000",
561 "BriefDescription": "Instructions retired which contains a load (Precise Event)"
562 },
563 {
564 "PEBS": "1",
565 "EventCode": "0xB",
566 "Counter": "0,1,2,3",
567 "UMask": "0x2",
568 "EventName": "MEM_INST_RETIRED.STORES",
569 "SampleAfterValue": "2000000",
570 "BriefDescription": "Instructions retired which contains a store (Precise Event)"
571 },
572 {
573 "PEBS": "1",
574 "EventCode": "0xCB",
575 "Counter": "0,1,2,3",
576 "UMask": "0x40",
577 "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
578 "SampleAfterValue": "200000",
579 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)"
580 },
581 {
582 "PEBS": "1",
583 "EventCode": "0xCB",
584 "Counter": "0,1,2,3",
585 "UMask": "0x1",
586 "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
587 "SampleAfterValue": "2000000",
588 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)"
589 },
590 {
591 "PEBS": "1",
592 "EventCode": "0xCB",
593 "Counter": "0,1,2,3",
594 "UMask": "0x2",
595 "EventName": "MEM_LOAD_RETIRED.L2_HIT",
596 "SampleAfterValue": "200000",
597 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)"
598 },
599 {
600 "PEBS": "1",
601 "EventCode": "0xCB",
602 "Counter": "0,1,2,3",
603 "UMask": "0x10",
604 "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
605 "SampleAfterValue": "10000",
606 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)"
607 },
608 {
609 "PEBS": "1",
610 "EventCode": "0xCB",
611 "Counter": "0,1,2,3",
612 "UMask": "0x4",
613 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
614 "SampleAfterValue": "40000",
615 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)"
616 },
617 {
618 "PEBS": "1",
619 "EventCode": "0xCB",
620 "Counter": "0,1,2,3",
621 "UMask": "0x8",
622 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
623 "SampleAfterValue": "40000",
624 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)"
625 },
626 {
627 "PEBS": "1",
628 "EventCode": "0xF",
629 "Counter": "0,1,2,3",
630 "UMask": "0x2",
631 "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM",
632 "SampleAfterValue": "40000",
633 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)"
634 },
635 {
636 "PEBS": "1",
637 "EventCode": "0xF",
638 "Counter": "0,1,2,3",
639 "UMask": "0x8",
640 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
641 "SampleAfterValue": "20000",
642 "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)"
643 },
644 {
645 "PEBS": "1",
646 "EventCode": "0xF",
647 "Counter": "0,1,2,3",
648 "UMask": "0x20",
649 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
650 "SampleAfterValue": "10000",
651 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)"
652 },
653 {
654 "PEBS": "1",
655 "EventCode": "0xF",
656 "Counter": "0,1,2,3",
657 "UMask": "0x80",
658 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
659 "SampleAfterValue": "4000",
660 "BriefDescription": "Load instructions retired IO (Precise Event)"
661 },
662 {
663 "PEBS": "1",
664 "EventCode": "0xF",
665 "Counter": "0,1,2,3",
666 "UMask": "0x4",
667 "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM",
668 "SampleAfterValue": "40000",
669 "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)"
670 },
671 {
672 "EventCode": "0xB0",
673 "Counter": "0,1,2,3",
674 "UMask": "0x80",
675 "EventName": "OFFCORE_REQUESTS.ANY",
676 "SampleAfterValue": "100000",
677 "BriefDescription": "All offcore requests"
678 },
679 {
680 "EventCode": "0xB0",
681 "Counter": "0,1,2,3",
682 "UMask": "0x8",
683 "EventName": "OFFCORE_REQUESTS.ANY.READ",
684 "SampleAfterValue": "100000",
685 "BriefDescription": "Offcore read requests"
686 },
687 {
688 "EventCode": "0xB0",
689 "Counter": "0,1,2,3",
690 "UMask": "0x10",
691 "EventName": "OFFCORE_REQUESTS.ANY.RFO",
692 "SampleAfterValue": "100000",
693 "BriefDescription": "Offcore RFO requests"
694 },
695 {
696 "EventCode": "0xB0",
697 "Counter": "0,1,2,3",
698 "UMask": "0x2",
699 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
700 "SampleAfterValue": "100000",
701 "BriefDescription": "Offcore demand code read requests"
702 },
703 {
704 "EventCode": "0xB0",
705 "Counter": "0,1,2,3",
706 "UMask": "0x1",
707 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
708 "SampleAfterValue": "100000",
709 "BriefDescription": "Offcore demand data read requests"
710 },
711 {
712 "EventCode": "0xB0",
713 "Counter": "0,1,2,3",
714 "UMask": "0x4",
715 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
716 "SampleAfterValue": "100000",
717 "BriefDescription": "Offcore demand RFO requests"
718 },
719 {
720 "EventCode": "0xB0",
721 "Counter": "0,1,2,3",
722 "UMask": "0x40",
723 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
724 "SampleAfterValue": "100000",
725 "BriefDescription": "Offcore L1 data cache writebacks"
726 },
727 {
728 "EventCode": "0x60",
729 "UMask": "0x8",
730 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
731 "SampleAfterValue": "2000000",
732 "BriefDescription": "Outstanding offcore reads"
733 },
734 {
735 "EventCode": "0x60",
736 "UMask": "0x8",
737 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
738 "SampleAfterValue": "2000000",
739 "BriefDescription": "Cycles offcore reads busy",
740 "CounterMask": "1"
741 },
742 {
743 "EventCode": "0x60",
744 "UMask": "0x2",
745 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
746 "SampleAfterValue": "2000000",
747 "BriefDescription": "Outstanding offcore demand code reads"
748 },
749 {
750 "EventCode": "0x60",
751 "UMask": "0x2",
752 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
753 "SampleAfterValue": "2000000",
754 "BriefDescription": "Cycles offcore demand code read busy",
755 "CounterMask": "1"
756 },
757 {
758 "EventCode": "0x60",
759 "UMask": "0x1",
760 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
761 "SampleAfterValue": "2000000",
762 "BriefDescription": "Outstanding offcore demand data reads"
763 },
764 {
765 "EventCode": "0x60",
766 "UMask": "0x1",
767 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
768 "SampleAfterValue": "2000000",
769 "BriefDescription": "Cycles offcore demand data read busy",
770 "CounterMask": "1"
771 },
772 {
773 "EventCode": "0x60",
774 "UMask": "0x4",
775 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
776 "SampleAfterValue": "2000000",
777 "BriefDescription": "Outstanding offcore demand RFOs"
778 },
779 {
780 "EventCode": "0x60",
781 "UMask": "0x4",
782 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
783 "SampleAfterValue": "2000000",
784 "BriefDescription": "Cycles offcore demand RFOs busy",
785 "CounterMask": "1"
786 },
787 {
788 "EventCode": "0xB2",
789 "Counter": "0,1,2,3",
790 "UMask": "0x1",
791 "EventName": "OFFCORE_REQUESTS_SQ_FULL",
792 "SampleAfterValue": "100000",
793 "BriefDescription": "Offcore requests blocked due to Super Queue full"
794 },
795 {
796 "EventCode": "0xF4",
797 "Counter": "0,1,2,3",
798 "UMask": "0x4",
799 "EventName": "SQ_MISC.LRU_HINTS",
800 "SampleAfterValue": "2000000",
801 "BriefDescription": "Super Queue LRU hints sent to LLC"
802 },
803 {
804 "EventCode": "0xF4",
805 "Counter": "0,1,2,3",
806 "UMask": "0x10",
807 "EventName": "SQ_MISC.SPLIT_LOCK",
808 "SampleAfterValue": "2000000",
809 "BriefDescription": "Super Queue lock splits across a cache line"
810 },
811 {
812 "EventCode": "0x6",
813 "Counter": "0,1,2,3",
814 "UMask": "0x4",
815 "EventName": "STORE_BLOCKS.AT_RET",
816 "SampleAfterValue": "200000",
817 "BriefDescription": "Loads delayed with at-Retirement block code"
818 },
819 {
820 "EventCode": "0x6",
821 "Counter": "0,1,2,3",
822 "UMask": "0x8",
823 "EventName": "STORE_BLOCKS.L1D_BLOCK",
824 "SampleAfterValue": "200000",
825 "BriefDescription": "Cacheable loads delayed with L1D block code"
826 },
827 {
828 "PEBS": "2",
829 "EventCode": "0xB",
830 "MSRValue": "0x0",
831 "Counter": "3",
832 "UMask": "0x10",
833 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
834 "MSRIndex": "0x3F6",
835 "SampleAfterValue": "2000000",
836 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)"
837 },
838 {
839 "PEBS": "2",
840 "EventCode": "0xB",
841 "MSRValue": "0x400",
842 "Counter": "3",
843 "UMask": "0x10",
844 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
845 "MSRIndex": "0x3F6",
846 "SampleAfterValue": "100",
847 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)"
848 },
849 {
850 "PEBS": "2",
851 "EventCode": "0xB",
852 "MSRValue": "0x80",
853 "Counter": "3",
854 "UMask": "0x10",
855 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
856 "MSRIndex": "0x3F6",
857 "SampleAfterValue": "1000",
858 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)"
859 },
860 {
861 "PEBS": "2",
862 "EventCode": "0xB",
863 "MSRValue": "0x10",
864 "Counter": "3",
865 "UMask": "0x10",
866 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
867 "MSRIndex": "0x3F6",
868 "SampleAfterValue": "10000",
869 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)"
870 },
871 {
872 "PEBS": "2",
873 "EventCode": "0xB",
874 "MSRValue": "0x4000",
875 "Counter": "3",
876 "UMask": "0x10",
877 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
878 "MSRIndex": "0x3F6",
879 "SampleAfterValue": "5",
880 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)"
881 },
882 {
883 "PEBS": "2",
884 "EventCode": "0xB",
885 "MSRValue": "0x800",
886 "Counter": "3",
887 "UMask": "0x10",
888 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
889 "MSRIndex": "0x3F6",
890 "SampleAfterValue": "50",
891 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)"
892 },
893 {
894 "PEBS": "2",
895 "EventCode": "0xB",
896 "MSRValue": "0x100",
897 "Counter": "3",
898 "UMask": "0x10",
899 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
900 "MSRIndex": "0x3F6",
901 "SampleAfterValue": "500",
902 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)"
903 },
904 {
905 "PEBS": "2",
906 "EventCode": "0xB",
907 "MSRValue": "0x20",
908 "Counter": "3",
909 "UMask": "0x10",
910 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
911 "MSRIndex": "0x3F6",
912 "SampleAfterValue": "5000",
913 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)"
914 },
915 {
916 "PEBS": "2",
917 "EventCode": "0xB",
918 "MSRValue": "0x8000",
919 "Counter": "3",
920 "UMask": "0x10",
921 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
922 "MSRIndex": "0x3F6",
923 "SampleAfterValue": "3",
924 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)"
925 },
926 {
927 "PEBS": "2",
928 "EventCode": "0xB",
929 "MSRValue": "0x4",
930 "Counter": "3",
931 "UMask": "0x10",
932 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
933 "MSRIndex": "0x3F6",
934 "SampleAfterValue": "50000",
935 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)"
936 },
937 {
938 "PEBS": "2",
939 "EventCode": "0xB",
940 "MSRValue": "0x1000",
941 "Counter": "3",
942 "UMask": "0x10",
943 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
944 "MSRIndex": "0x3F6",
945 "SampleAfterValue": "20",
946 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)"
947 },
948 {
949 "PEBS": "2",
950 "EventCode": "0xB",
951 "MSRValue": "0x200",
952 "Counter": "3",
953 "UMask": "0x10",
954 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
955 "MSRIndex": "0x3F6",
956 "SampleAfterValue": "200",
957 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)"
958 },
959 {
960 "PEBS": "2",
961 "EventCode": "0xB",
962 "MSRValue": "0x40",
963 "Counter": "3",
964 "UMask": "0x10",
965 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
966 "MSRIndex": "0x3F6",
967 "SampleAfterValue": "2000",
968 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)"
969 },
970 {
971 "PEBS": "2",
972 "EventCode": "0xB",
973 "MSRValue": "0x8",
974 "Counter": "3",
975 "UMask": "0x10",
976 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
977 "MSRIndex": "0x3F6",
978 "SampleAfterValue": "20000",
979 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)"
980 },
981 {
982 "PEBS": "2",
983 "EventCode": "0xB",
984 "MSRValue": "0x2000",
985 "Counter": "3",
986 "UMask": "0x10",
987 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
988 "MSRIndex": "0x3F6",
989 "SampleAfterValue": "10",
990 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)"
991 },
992 {
993 "EventCode": "0xB7",
994 "MSRValue": "0x7F11",
995 "Counter": "2",
996 "UMask": "0x1",
997 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
998 "MSRIndex": "0x1A6",
999 "SampleAfterValue": "100000",
1000 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
1001 "Offcore": "1"
1002 },
1003 {
1004 "EventCode": "0xB7",
1005 "MSRValue": "0xFF11",
1006 "Counter": "2",
1007 "UMask": "0x1",
1008 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
1009 "MSRIndex": "0x1A6",
1010 "SampleAfterValue": "100000",
1011 "BriefDescription": "All offcore data reads",
1012 "Offcore": "1"
1013 },
1014 {
1015 "EventCode": "0xB7",
1016 "MSRValue": "0x8011",
1017 "Counter": "2",
1018 "UMask": "0x1",
1019 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
1020 "MSRIndex": "0x1A6",
1021 "SampleAfterValue": "100000",
1022 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
1023 "Offcore": "1"
1024 },
1025 {
1026 "EventCode": "0xB7",
1027 "MSRValue": "0x111",
1028 "Counter": "2",
1029 "UMask": "0x1",
1030 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
1031 "MSRIndex": "0x1A6",
1032 "SampleAfterValue": "100000",
1033 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
1034 "Offcore": "1"
1035 },
1036 {
1037 "EventCode": "0xB7",
1038 "MSRValue": "0x211",
1039 "Counter": "2",
1040 "UMask": "0x1",
1041 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
1042 "MSRIndex": "0x1A6",
1043 "SampleAfterValue": "100000",
1044 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
1045 "Offcore": "1"
1046 },
1047 {
1048 "EventCode": "0xB7",
1049 "MSRValue": "0x411",
1050 "Counter": "2",
1051 "UMask": "0x1",
1052 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
1053 "MSRIndex": "0x1A6",
1054 "SampleAfterValue": "100000",
1055 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
1056 "Offcore": "1"
1057 },
1058 {
1059 "EventCode": "0xB7",
1060 "MSRValue": "0x711",
1061 "Counter": "2",
1062 "UMask": "0x1",
1063 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
1064 "MSRIndex": "0x1A6",
1065 "SampleAfterValue": "100000",
1066 "BriefDescription": "Offcore data reads satisfied by the LLC",
1067 "Offcore": "1"
1068 },
1069 {
1070 "EventCode": "0xB7",
1071 "MSRValue": "0x4711",
1072 "Counter": "2",
1073 "UMask": "0x1",
1074 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
1075 "MSRIndex": "0x1A6",
1076 "SampleAfterValue": "100000",
1077 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
1078 "Offcore": "1"
1079 },
1080 {
1081 "EventCode": "0xB7",
1082 "MSRValue": "0x1811",
1083 "Counter": "2",
1084 "UMask": "0x1",
1085 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
1086 "MSRIndex": "0x1A6",
1087 "SampleAfterValue": "100000",
1088 "BriefDescription": "Offcore data reads satisfied by a remote cache",
1089 "Offcore": "1"
1090 },
1091 {
1092 "EventCode": "0xB7",
1093 "MSRValue": "0x3811",
1094 "Counter": "2",
1095 "UMask": "0x1",
1096 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
1097 "MSRIndex": "0x1A6",
1098 "SampleAfterValue": "100000",
1099 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
1100 "Offcore": "1"
1101 },
1102 {
1103 "EventCode": "0xB7",
1104 "MSRValue": "0x1011",
1105 "Counter": "2",
1106 "UMask": "0x1",
1107 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
1108 "MSRIndex": "0x1A6",
1109 "SampleAfterValue": "100000",
1110 "BriefDescription": "Offcore data reads that HIT in a remote cache",
1111 "Offcore": "1"
1112 },
1113 {
1114 "EventCode": "0xB7",
1115 "MSRValue": "0x811",
1116 "Counter": "2",
1117 "UMask": "0x1",
1118 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1119 "MSRIndex": "0x1A6",
1120 "SampleAfterValue": "100000",
1121 "BriefDescription": "Offcore data reads that HITM in a remote cache",
1122 "Offcore": "1"
1123 },
1124 {
1125 "EventCode": "0xB7",
1126 "MSRValue": "0x7F44",
1127 "Counter": "2",
1128 "UMask": "0x1",
1129 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1130 "MSRIndex": "0x1A6",
1131 "SampleAfterValue": "100000",
1132 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
1133 "Offcore": "1"
1134 },
1135 {
1136 "EventCode": "0xB7",
1137 "MSRValue": "0xFF44",
1138 "Counter": "2",
1139 "UMask": "0x1",
1140 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1141 "MSRIndex": "0x1A6",
1142 "SampleAfterValue": "100000",
1143 "BriefDescription": "All offcore code reads",
1144 "Offcore": "1"
1145 },
1146 {
1147 "EventCode": "0xB7",
1148 "MSRValue": "0x8044",
1149 "Counter": "2",
1150 "UMask": "0x1",
1151 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1152 "MSRIndex": "0x1A6",
1153 "SampleAfterValue": "100000",
1154 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
1155 "Offcore": "1"
1156 },
1157 {
1158 "EventCode": "0xB7",
1159 "MSRValue": "0x144",
1160 "Counter": "2",
1161 "UMask": "0x1",
1162 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1163 "MSRIndex": "0x1A6",
1164 "SampleAfterValue": "100000",
1165 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
1166 "Offcore": "1"
1167 },
1168 {
1169 "EventCode": "0xB7",
1170 "MSRValue": "0x244",
1171 "Counter": "2",
1172 "UMask": "0x1",
1173 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1174 "MSRIndex": "0x1A6",
1175 "SampleAfterValue": "100000",
1176 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
1177 "Offcore": "1"
1178 },
1179 {
1180 "EventCode": "0xB7",
1181 "MSRValue": "0x444",
1182 "Counter": "2",
1183 "UMask": "0x1",
1184 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1185 "MSRIndex": "0x1A6",
1186 "SampleAfterValue": "100000",
1187 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
1188 "Offcore": "1"
1189 },
1190 {
1191 "EventCode": "0xB7",
1192 "MSRValue": "0x744",
1193 "Counter": "2",
1194 "UMask": "0x1",
1195 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1196 "MSRIndex": "0x1A6",
1197 "SampleAfterValue": "100000",
1198 "BriefDescription": "Offcore code reads satisfied by the LLC",
1199 "Offcore": "1"
1200 },
1201 {
1202 "EventCode": "0xB7",
1203 "MSRValue": "0x4744",
1204 "Counter": "2",
1205 "UMask": "0x1",
1206 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
1207 "MSRIndex": "0x1A6",
1208 "SampleAfterValue": "100000",
1209 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
1210 "Offcore": "1"
1211 },
1212 {
1213 "EventCode": "0xB7",
1214 "MSRValue": "0x1844",
1215 "Counter": "2",
1216 "UMask": "0x1",
1217 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
1218 "MSRIndex": "0x1A6",
1219 "SampleAfterValue": "100000",
1220 "BriefDescription": "Offcore code reads satisfied by a remote cache",
1221 "Offcore": "1"
1222 },
1223 {
1224 "EventCode": "0xB7",
1225 "MSRValue": "0x3844",
1226 "Counter": "2",
1227 "UMask": "0x1",
1228 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
1229 "MSRIndex": "0x1A6",
1230 "SampleAfterValue": "100000",
1231 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
1232 "Offcore": "1"
1233 },
1234 {
1235 "EventCode": "0xB7",
1236 "MSRValue": "0x1044",
1237 "Counter": "2",
1238 "UMask": "0x1",
1239 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
1240 "MSRIndex": "0x1A6",
1241 "SampleAfterValue": "100000",
1242 "BriefDescription": "Offcore code reads that HIT in a remote cache",
1243 "Offcore": "1"
1244 },
1245 {
1246 "EventCode": "0xB7",
1247 "MSRValue": "0x844",
1248 "Counter": "2",
1249 "UMask": "0x1",
1250 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1251 "MSRIndex": "0x1A6",
1252 "SampleAfterValue": "100000",
1253 "BriefDescription": "Offcore code reads that HITM in a remote cache",
1254 "Offcore": "1"
1255 },
1256 {
1257 "EventCode": "0xB7",
1258 "MSRValue": "0x7FFF",
1259 "Counter": "2",
1260 "UMask": "0x1",
1261 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1262 "MSRIndex": "0x1A6",
1263 "SampleAfterValue": "100000",
1264 "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
1265 "Offcore": "1"
1266 },
1267 {
1268 "EventCode": "0xB7",
1269 "MSRValue": "0xFFFF",
1270 "Counter": "2",
1271 "UMask": "0x1",
1272 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1273 "MSRIndex": "0x1A6",
1274 "SampleAfterValue": "100000",
1275 "BriefDescription": "All offcore requests",
1276 "Offcore": "1"
1277 },
1278 {
1279 "EventCode": "0xB7",
1280 "MSRValue": "0x80FF",
1281 "Counter": "2",
1282 "UMask": "0x1",
1283 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1284 "MSRIndex": "0x1A6",
1285 "SampleAfterValue": "100000",
1286 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
1287 "Offcore": "1"
1288 },
1289 {
1290 "EventCode": "0xB7",
1291 "MSRValue": "0x1FF",
1292 "Counter": "2",
1293 "UMask": "0x1",
1294 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1295 "MSRIndex": "0x1A6",
1296 "SampleAfterValue": "100000",
1297 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
1298 "Offcore": "1"
1299 },
1300 {
1301 "EventCode": "0xB7",
1302 "MSRValue": "0x2FF",
1303 "Counter": "2",
1304 "UMask": "0x1",
1305 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1306 "MSRIndex": "0x1A6",
1307 "SampleAfterValue": "100000",
1308 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
1309 "Offcore": "1"
1310 },
1311 {
1312 "EventCode": "0xB7",
1313 "MSRValue": "0x4FF",
1314 "Counter": "2",
1315 "UMask": "0x1",
1316 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1317 "MSRIndex": "0x1A6",
1318 "SampleAfterValue": "100000",
1319 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
1320 "Offcore": "1"
1321 },
1322 {
1323 "EventCode": "0xB7",
1324 "MSRValue": "0x7FF",
1325 "Counter": "2",
1326 "UMask": "0x1",
1327 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1328 "MSRIndex": "0x1A6",
1329 "SampleAfterValue": "100000",
1330 "BriefDescription": "Offcore requests satisfied by the LLC",
1331 "Offcore": "1"
1332 },
1333 {
1334 "EventCode": "0xB7",
1335 "MSRValue": "0x47FF",
1336 "Counter": "2",
1337 "UMask": "0x1",
1338 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
1339 "MSRIndex": "0x1A6",
1340 "SampleAfterValue": "100000",
1341 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
1342 "Offcore": "1"
1343 },
1344 {
1345 "EventCode": "0xB7",
1346 "MSRValue": "0x18FF",
1347 "Counter": "2",
1348 "UMask": "0x1",
1349 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
1350 "MSRIndex": "0x1A6",
1351 "SampleAfterValue": "100000",
1352 "BriefDescription": "Offcore requests satisfied by a remote cache",
1353 "Offcore": "1"
1354 },
1355 {
1356 "EventCode": "0xB7",
1357 "MSRValue": "0x38FF",
1358 "Counter": "2",
1359 "UMask": "0x1",
1360 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
1361 "MSRIndex": "0x1A6",
1362 "SampleAfterValue": "100000",
1363 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
1364 "Offcore": "1"
1365 },
1366 {
1367 "EventCode": "0xB7",
1368 "MSRValue": "0x10FF",
1369 "Counter": "2",
1370 "UMask": "0x1",
1371 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
1372 "MSRIndex": "0x1A6",
1373 "SampleAfterValue": "100000",
1374 "BriefDescription": "Offcore requests that HIT in a remote cache",
1375 "Offcore": "1"
1376 },
1377 {
1378 "EventCode": "0xB7",
1379 "MSRValue": "0x8FF",
1380 "Counter": "2",
1381 "UMask": "0x1",
1382 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1383 "MSRIndex": "0x1A6",
1384 "SampleAfterValue": "100000",
1385 "BriefDescription": "Offcore requests that HITM in a remote cache",
1386 "Offcore": "1"
1387 },
1388 {
1389 "EventCode": "0xB7",
1390 "MSRValue": "0x7F22",
1391 "Counter": "2",
1392 "UMask": "0x1",
1393 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1394 "MSRIndex": "0x1A6",
1395 "SampleAfterValue": "100000",
1396 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
1397 "Offcore": "1"
1398 },
1399 {
1400 "EventCode": "0xB7",
1401 "MSRValue": "0xFF22",
1402 "Counter": "2",
1403 "UMask": "0x1",
1404 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1405 "MSRIndex": "0x1A6",
1406 "SampleAfterValue": "100000",
1407 "BriefDescription": "All offcore RFO requests",
1408 "Offcore": "1"
1409 },
1410 {
1411 "EventCode": "0xB7",
1412 "MSRValue": "0x8022",
1413 "Counter": "2",
1414 "UMask": "0x1",
1415 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1416 "MSRIndex": "0x1A6",
1417 "SampleAfterValue": "100000",
1418 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
1419 "Offcore": "1"
1420 },
1421 {
1422 "EventCode": "0xB7",
1423 "MSRValue": "0x122",
1424 "Counter": "2",
1425 "UMask": "0x1",
1426 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1427 "MSRIndex": "0x1A6",
1428 "SampleAfterValue": "100000",
1429 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
1430 "Offcore": "1"
1431 },
1432 {
1433 "EventCode": "0xB7",
1434 "MSRValue": "0x222",
1435 "Counter": "2",
1436 "UMask": "0x1",
1437 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1438 "MSRIndex": "0x1A6",
1439 "SampleAfterValue": "100000",
1440 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
1441 "Offcore": "1"
1442 },
1443 {
1444 "EventCode": "0xB7",
1445 "MSRValue": "0x422",
1446 "Counter": "2",
1447 "UMask": "0x1",
1448 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1449 "MSRIndex": "0x1A6",
1450 "SampleAfterValue": "100000",
1451 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
1452 "Offcore": "1"
1453 },
1454 {
1455 "EventCode": "0xB7",
1456 "MSRValue": "0x722",
1457 "Counter": "2",
1458 "UMask": "0x1",
1459 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1460 "MSRIndex": "0x1A6",
1461 "SampleAfterValue": "100000",
1462 "BriefDescription": "Offcore RFO requests satisfied by the LLC",
1463 "Offcore": "1"
1464 },
1465 {
1466 "EventCode": "0xB7",
1467 "MSRValue": "0x4722",
1468 "Counter": "2",
1469 "UMask": "0x1",
1470 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
1471 "MSRIndex": "0x1A6",
1472 "SampleAfterValue": "100000",
1473 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
1474 "Offcore": "1"
1475 },
1476 {
1477 "EventCode": "0xB7",
1478 "MSRValue": "0x1822",
1479 "Counter": "2",
1480 "UMask": "0x1",
1481 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
1482 "MSRIndex": "0x1A6",
1483 "SampleAfterValue": "100000",
1484 "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
1485 "Offcore": "1"
1486 },
1487 {
1488 "EventCode": "0xB7",
1489 "MSRValue": "0x3822",
1490 "Counter": "2",
1491 "UMask": "0x1",
1492 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
1493 "MSRIndex": "0x1A6",
1494 "SampleAfterValue": "100000",
1495 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
1496 "Offcore": "1"
1497 },
1498 {
1499 "EventCode": "0xB7",
1500 "MSRValue": "0x1022",
1501 "Counter": "2",
1502 "UMask": "0x1",
1503 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
1504 "MSRIndex": "0x1A6",
1505 "SampleAfterValue": "100000",
1506 "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
1507 "Offcore": "1"
1508 },
1509 {
1510 "EventCode": "0xB7",
1511 "MSRValue": "0x822",
1512 "Counter": "2",
1513 "UMask": "0x1",
1514 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1515 "MSRIndex": "0x1A6",
1516 "SampleAfterValue": "100000",
1517 "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
1518 "Offcore": "1"
1519 },
1520 {
1521 "EventCode": "0xB7",
1522 "MSRValue": "0x7F08",
1523 "Counter": "2",
1524 "UMask": "0x1",
1525 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1526 "MSRIndex": "0x1A6",
1527 "SampleAfterValue": "100000",
1528 "BriefDescription": "Offcore writebacks to any cache or DRAM.",
1529 "Offcore": "1"
1530 },
1531 {
1532 "EventCode": "0xB7",
1533 "MSRValue": "0xFF08",
1534 "Counter": "2",
1535 "UMask": "0x1",
1536 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1537 "MSRIndex": "0x1A6",
1538 "SampleAfterValue": "100000",
1539 "BriefDescription": "All offcore writebacks",
1540 "Offcore": "1"
1541 },
1542 {
1543 "EventCode": "0xB7",
1544 "MSRValue": "0x8008",
1545 "Counter": "2",
1546 "UMask": "0x1",
1547 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1548 "MSRIndex": "0x1A6",
1549 "SampleAfterValue": "100000",
1550 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
1551 "Offcore": "1"
1552 },
1553 {
1554 "EventCode": "0xB7",
1555 "MSRValue": "0x108",
1556 "Counter": "2",
1557 "UMask": "0x1",
1558 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1559 "MSRIndex": "0x1A6",
1560 "SampleAfterValue": "100000",
1561 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
1562 "Offcore": "1"
1563 },
1564 {
1565 "EventCode": "0xB7",
1566 "MSRValue": "0x408",
1567 "Counter": "2",
1568 "UMask": "0x1",
1569 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1570 "MSRIndex": "0x1A6",
1571 "SampleAfterValue": "100000",
1572 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
1573 "Offcore": "1"
1574 },
1575 {
1576 "EventCode": "0xB7",
1577 "MSRValue": "0x708",
1578 "Counter": "2",
1579 "UMask": "0x1",
1580 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1581 "MSRIndex": "0x1A6",
1582 "SampleAfterValue": "100000",
1583 "BriefDescription": "Offcore writebacks to the LLC",
1584 "Offcore": "1"
1585 },
1586 {
1587 "EventCode": "0xB7",
1588 "MSRValue": "0x4708",
1589 "Counter": "2",
1590 "UMask": "0x1",
1591 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
1592 "MSRIndex": "0x1A6",
1593 "SampleAfterValue": "100000",
1594 "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
1595 "Offcore": "1"
1596 },
1597 {
1598 "EventCode": "0xB7",
1599 "MSRValue": "0x1808",
1600 "Counter": "2",
1601 "UMask": "0x1",
1602 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
1603 "MSRIndex": "0x1A6",
1604 "SampleAfterValue": "100000",
1605 "BriefDescription": "Offcore writebacks to a remote cache",
1606 "Offcore": "1"
1607 },
1608 {
1609 "EventCode": "0xB7",
1610 "MSRValue": "0x3808",
1611 "Counter": "2",
1612 "UMask": "0x1",
1613 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
1614 "MSRIndex": "0x1A6",
1615 "SampleAfterValue": "100000",
1616 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
1617 "Offcore": "1"
1618 },
1619 {
1620 "EventCode": "0xB7",
1621 "MSRValue": "0x1008",
1622 "Counter": "2",
1623 "UMask": "0x1",
1624 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
1625 "MSRIndex": "0x1A6",
1626 "SampleAfterValue": "100000",
1627 "BriefDescription": "Offcore writebacks that HIT in a remote cache",
1628 "Offcore": "1"
1629 },
1630 {
1631 "EventCode": "0xB7",
1632 "MSRValue": "0x808",
1633 "Counter": "2",
1634 "UMask": "0x1",
1635 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1636 "MSRIndex": "0x1A6",
1637 "SampleAfterValue": "100000",
1638 "BriefDescription": "Offcore writebacks that HITM in a remote cache",
1639 "Offcore": "1"
1640 },
1641 {
1642 "EventCode": "0xB7",
1643 "MSRValue": "0x7F77",
1644 "Counter": "2",
1645 "UMask": "0x1",
1646 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1647 "MSRIndex": "0x1A6",
1648 "SampleAfterValue": "100000",
1649 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
1650 "Offcore": "1"
1651 },
1652 {
1653 "EventCode": "0xB7",
1654 "MSRValue": "0xFF77",
1655 "Counter": "2",
1656 "UMask": "0x1",
1657 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1658 "MSRIndex": "0x1A6",
1659 "SampleAfterValue": "100000",
1660 "BriefDescription": "All offcore code or data read requests",
1661 "Offcore": "1"
1662 },
1663 {
1664 "EventCode": "0xB7",
1665 "MSRValue": "0x8077",
1666 "Counter": "2",
1667 "UMask": "0x1",
1668 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1669 "MSRIndex": "0x1A6",
1670 "SampleAfterValue": "100000",
1671 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
1672 "Offcore": "1"
1673 },
1674 {
1675 "EventCode": "0xB7",
1676 "MSRValue": "0x177",
1677 "Counter": "2",
1678 "UMask": "0x1",
1679 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1680 "MSRIndex": "0x1A6",
1681 "SampleAfterValue": "100000",
1682 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
1683 "Offcore": "1"
1684 },
1685 {
1686 "EventCode": "0xB7",
1687 "MSRValue": "0x277",
1688 "Counter": "2",
1689 "UMask": "0x1",
1690 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1691 "MSRIndex": "0x1A6",
1692 "SampleAfterValue": "100000",
1693 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
1694 "Offcore": "1"
1695 },
1696 {
1697 "EventCode": "0xB7",
1698 "MSRValue": "0x477",
1699 "Counter": "2",
1700 "UMask": "0x1",
1701 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1702 "MSRIndex": "0x1A6",
1703 "SampleAfterValue": "100000",
1704 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
1705 "Offcore": "1"
1706 },
1707 {
1708 "EventCode": "0xB7",
1709 "MSRValue": "0x777",
1710 "Counter": "2",
1711 "UMask": "0x1",
1712 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1713 "MSRIndex": "0x1A6",
1714 "SampleAfterValue": "100000",
1715 "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
1716 "Offcore": "1"
1717 },
1718 {
1719 "EventCode": "0xB7",
1720 "MSRValue": "0x4777",
1721 "Counter": "2",
1722 "UMask": "0x1",
1723 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
1724 "MSRIndex": "0x1A6",
1725 "SampleAfterValue": "100000",
1726 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
1727 "Offcore": "1"
1728 },
1729 {
1730 "EventCode": "0xB7",
1731 "MSRValue": "0x1877",
1732 "Counter": "2",
1733 "UMask": "0x1",
1734 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
1735 "MSRIndex": "0x1A6",
1736 "SampleAfterValue": "100000",
1737 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
1738 "Offcore": "1"
1739 },
1740 {
1741 "EventCode": "0xB7",
1742 "MSRValue": "0x3877",
1743 "Counter": "2",
1744 "UMask": "0x1",
1745 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
1746 "MSRIndex": "0x1A6",
1747 "SampleAfterValue": "100000",
1748 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
1749 "Offcore": "1"
1750 },
1751 {
1752 "EventCode": "0xB7",
1753 "MSRValue": "0x1077",
1754 "Counter": "2",
1755 "UMask": "0x1",
1756 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
1757 "MSRIndex": "0x1A6",
1758 "SampleAfterValue": "100000",
1759 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
1760 "Offcore": "1"
1761 },
1762 {
1763 "EventCode": "0xB7",
1764 "MSRValue": "0x877",
1765 "Counter": "2",
1766 "UMask": "0x1",
1767 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1768 "MSRIndex": "0x1A6",
1769 "SampleAfterValue": "100000",
1770 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
1771 "Offcore": "1"
1772 },
1773 {
1774 "EventCode": "0xB7",
1775 "MSRValue": "0x7F33",
1776 "Counter": "2",
1777 "UMask": "0x1",
1778 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1779 "MSRIndex": "0x1A6",
1780 "SampleAfterValue": "100000",
1781 "BriefDescription": "Offcore request = all data, response = any cache_dram",
1782 "Offcore": "1"
1783 },
1784 {
1785 "EventCode": "0xB7",
1786 "MSRValue": "0xFF33",
1787 "Counter": "2",
1788 "UMask": "0x1",
1789 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1790 "MSRIndex": "0x1A6",
1791 "SampleAfterValue": "100000",
1792 "BriefDescription": "Offcore request = all data, response = any location",
1793 "Offcore": "1"
1794 },
1795 {
1796 "EventCode": "0xB7",
1797 "MSRValue": "0x8033",
1798 "Counter": "2",
1799 "UMask": "0x1",
1800 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1801 "MSRIndex": "0x1A6",
1802 "SampleAfterValue": "100000",
1803 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",
1804 "Offcore": "1"
1805 },
1806 {
1807 "EventCode": "0xB7",
1808 "MSRValue": "0x133",
1809 "Counter": "2",
1810 "UMask": "0x1",
1811 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1812 "MSRIndex": "0x1A6",
1813 "SampleAfterValue": "100000",
1814 "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",
1815 "Offcore": "1"
1816 },
1817 {
1818 "EventCode": "0xB7",
1819 "MSRValue": "0x233",
1820 "Counter": "2",
1821 "UMask": "0x1",
1822 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1823 "MSRIndex": "0x1A6",
1824 "SampleAfterValue": "100000",
1825 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",
1826 "Offcore": "1"
1827 },
1828 {
1829 "EventCode": "0xB7",
1830 "MSRValue": "0x433",
1831 "Counter": "2",
1832 "UMask": "0x1",
1833 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1834 "MSRIndex": "0x1A6",
1835 "SampleAfterValue": "100000",
1836 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core",
1837 "Offcore": "1"
1838 },
1839 {
1840 "EventCode": "0xB7",
1841 "MSRValue": "0x733",
1842 "Counter": "2",
1843 "UMask": "0x1",
1844 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1845 "MSRIndex": "0x1A6",
1846 "SampleAfterValue": "100000",
1847 "BriefDescription": "Offcore request = all data, response = local cache",
1848 "Offcore": "1"
1849 },
1850 {
1851 "EventCode": "0xB7",
1852 "MSRValue": "0x4733",
1853 "Counter": "2",
1854 "UMask": "0x1",
1855 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
1856 "MSRIndex": "0x1A6",
1857 "SampleAfterValue": "100000",
1858 "BriefDescription": "Offcore request = all data, response = local cache or dram",
1859 "Offcore": "1"
1860 },
1861 {
1862 "EventCode": "0xB7",
1863 "MSRValue": "0x1833",
1864 "Counter": "2",
1865 "UMask": "0x1",
1866 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
1867 "MSRIndex": "0x1A6",
1868 "SampleAfterValue": "100000",
1869 "BriefDescription": "Offcore request = all data, response = remote cache",
1870 "Offcore": "1"
1871 },
1872 {
1873 "EventCode": "0xB7",
1874 "MSRValue": "0x3833",
1875 "Counter": "2",
1876 "UMask": "0x1",
1877 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
1878 "MSRIndex": "0x1A6",
1879 "SampleAfterValue": "100000",
1880 "BriefDescription": "Offcore request = all data, response = remote cache or dram",
1881 "Offcore": "1"
1882 },
1883 {
1884 "EventCode": "0xB7",
1885 "MSRValue": "0x1033",
1886 "Counter": "2",
1887 "UMask": "0x1",
1888 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
1889 "MSRIndex": "0x1A6",
1890 "SampleAfterValue": "100000",
1891 "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",
1892 "Offcore": "1"
1893 },
1894 {
1895 "EventCode": "0xB7",
1896 "MSRValue": "0x833",
1897 "Counter": "2",
1898 "UMask": "0x1",
1899 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1900 "MSRIndex": "0x1A6",
1901 "SampleAfterValue": "100000",
1902 "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",
1903 "Offcore": "1"
1904 },
1905 {
1906 "EventCode": "0xB7",
1907 "MSRValue": "0x7F03",
1908 "Counter": "2",
1909 "UMask": "0x1",
1910 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1911 "MSRIndex": "0x1A6",
1912 "SampleAfterValue": "100000",
1913 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
1914 "Offcore": "1"
1915 },
1916 {
1917 "EventCode": "0xB7",
1918 "MSRValue": "0xFF03",
1919 "Counter": "2",
1920 "UMask": "0x1",
1921 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1922 "MSRIndex": "0x1A6",
1923 "SampleAfterValue": "100000",
1924 "BriefDescription": "All offcore demand data requests",
1925 "Offcore": "1"
1926 },
1927 {
1928 "EventCode": "0xB7",
1929 "MSRValue": "0x8003",
1930 "Counter": "2",
1931 "UMask": "0x1",
1932 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1933 "MSRIndex": "0x1A6",
1934 "SampleAfterValue": "100000",
1935 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
1936 "Offcore": "1"
1937 },
1938 {
1939 "EventCode": "0xB7",
1940 "MSRValue": "0x103",
1941 "Counter": "2",
1942 "UMask": "0x1",
1943 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1944 "MSRIndex": "0x1A6",
1945 "SampleAfterValue": "100000",
1946 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
1947 "Offcore": "1"
1948 },
1949 {
1950 "EventCode": "0xB7",
1951 "MSRValue": "0x203",
1952 "Counter": "2",
1953 "UMask": "0x1",
1954 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1955 "MSRIndex": "0x1A6",
1956 "SampleAfterValue": "100000",
1957 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
1958 "Offcore": "1"
1959 },
1960 {
1961 "EventCode": "0xB7",
1962 "MSRValue": "0x403",
1963 "Counter": "2",
1964 "UMask": "0x1",
1965 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1966 "MSRIndex": "0x1A6",
1967 "SampleAfterValue": "100000",
1968 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
1969 "Offcore": "1"
1970 },
1971 {
1972 "EventCode": "0xB7",
1973 "MSRValue": "0x703",
1974 "Counter": "2",
1975 "UMask": "0x1",
1976 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1977 "MSRIndex": "0x1A6",
1978 "SampleAfterValue": "100000",
1979 "BriefDescription": "Offcore demand data requests satisfied by the LLC",
1980 "Offcore": "1"
1981 },
1982 {
1983 "EventCode": "0xB7",
1984 "MSRValue": "0x4703",
1985 "Counter": "2",
1986 "UMask": "0x1",
1987 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
1988 "MSRIndex": "0x1A6",
1989 "SampleAfterValue": "100000",
1990 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
1991 "Offcore": "1"
1992 },
1993 {
1994 "EventCode": "0xB7",
1995 "MSRValue": "0x1803",
1996 "Counter": "2",
1997 "UMask": "0x1",
1998 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
1999 "MSRIndex": "0x1A6",
2000 "SampleAfterValue": "100000",
2001 "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
2002 "Offcore": "1"
2003 },
2004 {
2005 "EventCode": "0xB7",
2006 "MSRValue": "0x3803",
2007 "Counter": "2",
2008 "UMask": "0x1",
2009 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
2010 "MSRIndex": "0x1A6",
2011 "SampleAfterValue": "100000",
2012 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
2013 "Offcore": "1"
2014 },
2015 {
2016 "EventCode": "0xB7",
2017 "MSRValue": "0x1003",
2018 "Counter": "2",
2019 "UMask": "0x1",
2020 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
2021 "MSRIndex": "0x1A6",
2022 "SampleAfterValue": "100000",
2023 "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
2024 "Offcore": "1"
2025 },
2026 {
2027 "EventCode": "0xB7",
2028 "MSRValue": "0x803",
2029 "Counter": "2",
2030 "UMask": "0x1",
2031 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
2032 "MSRIndex": "0x1A6",
2033 "SampleAfterValue": "100000",
2034 "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
2035 "Offcore": "1"
2036 },
2037 {
2038 "EventCode": "0xB7",
2039 "MSRValue": "0x7F01",
2040 "Counter": "2",
2041 "UMask": "0x1",
2042 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
2043 "MSRIndex": "0x1A6",
2044 "SampleAfterValue": "100000",
2045 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
2046 "Offcore": "1"
2047 },
2048 {
2049 "EventCode": "0xB7",
2050 "MSRValue": "0xFF01",
2051 "Counter": "2",
2052 "UMask": "0x1",
2053 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
2054 "MSRIndex": "0x1A6",
2055 "SampleAfterValue": "100000",
2056 "BriefDescription": "All offcore demand data reads",
2057 "Offcore": "1"
2058 },
2059 {
2060 "EventCode": "0xB7",
2061 "MSRValue": "0x8001",
2062 "Counter": "2",
2063 "UMask": "0x1",
2064 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
2065 "MSRIndex": "0x1A6",
2066 "SampleAfterValue": "100000",
2067 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
2068 "Offcore": "1"
2069 },
2070 {
2071 "EventCode": "0xB7",
2072 "MSRValue": "0x101",
2073 "Counter": "2",
2074 "UMask": "0x1",
2075 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2076 "MSRIndex": "0x1A6",
2077 "SampleAfterValue": "100000",
2078 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
2079 "Offcore": "1"
2080 },
2081 {
2082 "EventCode": "0xB7",
2083 "MSRValue": "0x201",
2084 "Counter": "2",
2085 "UMask": "0x1",
2086 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2087 "MSRIndex": "0x1A6",
2088 "SampleAfterValue": "100000",
2089 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
2090 "Offcore": "1"
2091 },
2092 {
2093 "EventCode": "0xB7",
2094 "MSRValue": "0x401",
2095 "Counter": "2",
2096 "UMask": "0x1",
2097 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2098 "MSRIndex": "0x1A6",
2099 "SampleAfterValue": "100000",
2100 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
2101 "Offcore": "1"
2102 },
2103 {
2104 "EventCode": "0xB7",
2105 "MSRValue": "0x701",
2106 "Counter": "2",
2107 "UMask": "0x1",
2108 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
2109 "MSRIndex": "0x1A6",
2110 "SampleAfterValue": "100000",
2111 "BriefDescription": "Offcore demand data reads satisfied by the LLC",
2112 "Offcore": "1"
2113 },
2114 {
2115 "EventCode": "0xB7",
2116 "MSRValue": "0x4701",
2117 "Counter": "2",
2118 "UMask": "0x1",
2119 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
2120 "MSRIndex": "0x1A6",
2121 "SampleAfterValue": "100000",
2122 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
2123 "Offcore": "1"
2124 },
2125 {
2126 "EventCode": "0xB7",
2127 "MSRValue": "0x1801",
2128 "Counter": "2",
2129 "UMask": "0x1",
2130 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
2131 "MSRIndex": "0x1A6",
2132 "SampleAfterValue": "100000",
2133 "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
2134 "Offcore": "1"
2135 },
2136 {
2137 "EventCode": "0xB7",
2138 "MSRValue": "0x3801",
2139 "Counter": "2",
2140 "UMask": "0x1",
2141 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
2142 "MSRIndex": "0x1A6",
2143 "SampleAfterValue": "100000",
2144 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
2145 "Offcore": "1"
2146 },
2147 {
2148 "EventCode": "0xB7",
2149 "MSRValue": "0x1001",
2150 "Counter": "2",
2151 "UMask": "0x1",
2152 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
2153 "MSRIndex": "0x1A6",
2154 "SampleAfterValue": "100000",
2155 "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
2156 "Offcore": "1"
2157 },
2158 {
2159 "EventCode": "0xB7",
2160 "MSRValue": "0x801",
2161 "Counter": "2",
2162 "UMask": "0x1",
2163 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
2164 "MSRIndex": "0x1A6",
2165 "SampleAfterValue": "100000",
2166 "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
2167 "Offcore": "1"
2168 },
2169 {
2170 "EventCode": "0xB7",
2171 "MSRValue": "0x7F04",
2172 "Counter": "2",
2173 "UMask": "0x1",
2174 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
2175 "MSRIndex": "0x1A6",
2176 "SampleAfterValue": "100000",
2177 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
2178 "Offcore": "1"
2179 },
2180 {
2181 "EventCode": "0xB7",
2182 "MSRValue": "0xFF04",
2183 "Counter": "2",
2184 "UMask": "0x1",
2185 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
2186 "MSRIndex": "0x1A6",
2187 "SampleAfterValue": "100000",
2188 "BriefDescription": "All offcore demand code reads",
2189 "Offcore": "1"
2190 },
2191 {
2192 "EventCode": "0xB7",
2193 "MSRValue": "0x8004",
2194 "Counter": "2",
2195 "UMask": "0x1",
2196 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
2197 "MSRIndex": "0x1A6",
2198 "SampleAfterValue": "100000",
2199 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
2200 "Offcore": "1"
2201 },
2202 {
2203 "EventCode": "0xB7",
2204 "MSRValue": "0x104",
2205 "Counter": "2",
2206 "UMask": "0x1",
2207 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
2208 "MSRIndex": "0x1A6",
2209 "SampleAfterValue": "100000",
2210 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
2211 "Offcore": "1"
2212 },
2213 {
2214 "EventCode": "0xB7",
2215 "MSRValue": "0x204",
2216 "Counter": "2",
2217 "UMask": "0x1",
2218 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2219 "MSRIndex": "0x1A6",
2220 "SampleAfterValue": "100000",
2221 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
2222 "Offcore": "1"
2223 },
2224 {
2225 "EventCode": "0xB7",
2226 "MSRValue": "0x404",
2227 "Counter": "2",
2228 "UMask": "0x1",
2229 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2230 "MSRIndex": "0x1A6",
2231 "SampleAfterValue": "100000",
2232 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
2233 "Offcore": "1"
2234 },
2235 {
2236 "EventCode": "0xB7",
2237 "MSRValue": "0x704",
2238 "Counter": "2",
2239 "UMask": "0x1",
2240 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
2241 "MSRIndex": "0x1A6",
2242 "SampleAfterValue": "100000",
2243 "BriefDescription": "Offcore demand code reads satisfied by the LLC",
2244 "Offcore": "1"
2245 },
2246 {
2247 "EventCode": "0xB7",
2248 "MSRValue": "0x4704",
2249 "Counter": "2",
2250 "UMask": "0x1",
2251 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
2252 "MSRIndex": "0x1A6",
2253 "SampleAfterValue": "100000",
2254 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
2255 "Offcore": "1"
2256 },
2257 {
2258 "EventCode": "0xB7",
2259 "MSRValue": "0x1804",
2260 "Counter": "2",
2261 "UMask": "0x1",
2262 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
2263 "MSRIndex": "0x1A6",
2264 "SampleAfterValue": "100000",
2265 "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
2266 "Offcore": "1"
2267 },
2268 {
2269 "EventCode": "0xB7",
2270 "MSRValue": "0x3804",
2271 "Counter": "2",
2272 "UMask": "0x1",
2273 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
2274 "MSRIndex": "0x1A6",
2275 "SampleAfterValue": "100000",
2276 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
2277 "Offcore": "1"
2278 },
2279 {
2280 "EventCode": "0xB7",
2281 "MSRValue": "0x1004",
2282 "Counter": "2",
2283 "UMask": "0x1",
2284 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
2285 "MSRIndex": "0x1A6",
2286 "SampleAfterValue": "100000",
2287 "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
2288 "Offcore": "1"
2289 },
2290 {
2291 "EventCode": "0xB7",
2292 "MSRValue": "0x804",
2293 "Counter": "2",
2294 "UMask": "0x1",
2295 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
2296 "MSRIndex": "0x1A6",
2297 "SampleAfterValue": "100000",
2298 "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
2299 "Offcore": "1"
2300 },
2301 {
2302 "EventCode": "0xB7",
2303 "MSRValue": "0x7F02",
2304 "Counter": "2",
2305 "UMask": "0x1",
2306 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
2307 "MSRIndex": "0x1A6",
2308 "SampleAfterValue": "100000",
2309 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
2310 "Offcore": "1"
2311 },
2312 {
2313 "EventCode": "0xB7",
2314 "MSRValue": "0xFF02",
2315 "Counter": "2",
2316 "UMask": "0x1",
2317 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
2318 "MSRIndex": "0x1A6",
2319 "SampleAfterValue": "100000",
2320 "BriefDescription": "All offcore demand RFO requests",
2321 "Offcore": "1"
2322 },
2323 {
2324 "EventCode": "0xB7",
2325 "MSRValue": "0x8002",
2326 "Counter": "2",
2327 "UMask": "0x1",
2328 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
2329 "MSRIndex": "0x1A6",
2330 "SampleAfterValue": "100000",
2331 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
2332 "Offcore": "1"
2333 },
2334 {
2335 "EventCode": "0xB7",
2336 "MSRValue": "0x102",
2337 "Counter": "2",
2338 "UMask": "0x1",
2339 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
2340 "MSRIndex": "0x1A6",
2341 "SampleAfterValue": "100000",
2342 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
2343 "Offcore": "1"
2344 },
2345 {
2346 "EventCode": "0xB7",
2347 "MSRValue": "0x202",
2348 "Counter": "2",
2349 "UMask": "0x1",
2350 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
2351 "MSRIndex": "0x1A6",
2352 "SampleAfterValue": "100000",
2353 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
2354 "Offcore": "1"
2355 },
2356 {
2357 "EventCode": "0xB7",
2358 "MSRValue": "0x402",
2359 "Counter": "2",
2360 "UMask": "0x1",
2361 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
2362 "MSRIndex": "0x1A6",
2363 "SampleAfterValue": "100000",
2364 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
2365 "Offcore": "1"
2366 },
2367 {
2368 "EventCode": "0xB7",
2369 "MSRValue": "0x702",
2370 "Counter": "2",
2371 "UMask": "0x1",
2372 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
2373 "MSRIndex": "0x1A6",
2374 "SampleAfterValue": "100000",
2375 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
2376 "Offcore": "1"
2377 },
2378 {
2379 "EventCode": "0xB7",
2380 "MSRValue": "0x4702",
2381 "Counter": "2",
2382 "UMask": "0x1",
2383 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
2384 "MSRIndex": "0x1A6",
2385 "SampleAfterValue": "100000",
2386 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
2387 "Offcore": "1"
2388 },
2389 {
2390 "EventCode": "0xB7",
2391 "MSRValue": "0x1802",
2392 "Counter": "2",
2393 "UMask": "0x1",
2394 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
2395 "MSRIndex": "0x1A6",
2396 "SampleAfterValue": "100000",
2397 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
2398 "Offcore": "1"
2399 },
2400 {
2401 "EventCode": "0xB7",
2402 "MSRValue": "0x3802",
2403 "Counter": "2",
2404 "UMask": "0x1",
2405 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
2406 "MSRIndex": "0x1A6",
2407 "SampleAfterValue": "100000",
2408 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
2409 "Offcore": "1"
2410 },
2411 {
2412 "EventCode": "0xB7",
2413 "MSRValue": "0x1002",
2414 "Counter": "2",
2415 "UMask": "0x1",
2416 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
2417 "MSRIndex": "0x1A6",
2418 "SampleAfterValue": "100000",
2419 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
2420 "Offcore": "1"
2421 },
2422 {
2423 "EventCode": "0xB7",
2424 "MSRValue": "0x802",
2425 "Counter": "2",
2426 "UMask": "0x1",
2427 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2428 "MSRIndex": "0x1A6",
2429 "SampleAfterValue": "100000",
2430 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
2431 "Offcore": "1"
2432 },
2433 {
2434 "EventCode": "0xB7",
2435 "MSRValue": "0x7F80",
2436 "Counter": "2",
2437 "UMask": "0x1",
2438 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2439 "MSRIndex": "0x1A6",
2440 "SampleAfterValue": "100000",
2441 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
2442 "Offcore": "1"
2443 },
2444 {
2445 "EventCode": "0xB7",
2446 "MSRValue": "0xFF80",
2447 "Counter": "2",
2448 "UMask": "0x1",
2449 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2450 "MSRIndex": "0x1A6",
2451 "SampleAfterValue": "100000",
2452 "BriefDescription": "All offcore other requests",
2453 "Offcore": "1"
2454 },
2455 {
2456 "EventCode": "0xB7",
2457 "MSRValue": "0x8080",
2458 "Counter": "2",
2459 "UMask": "0x1",
2460 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2461 "MSRIndex": "0x1A6",
2462 "SampleAfterValue": "100000",
2463 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
2464 "Offcore": "1"
2465 },
2466 {
2467 "EventCode": "0xB7",
2468 "MSRValue": "0x180",
2469 "Counter": "2",
2470 "UMask": "0x1",
2471 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2472 "MSRIndex": "0x1A6",
2473 "SampleAfterValue": "100000",
2474 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
2475 "Offcore": "1"
2476 },
2477 {
2478 "EventCode": "0xB7",
2479 "MSRValue": "0x280",
2480 "Counter": "2",
2481 "UMask": "0x1",
2482 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2483 "MSRIndex": "0x1A6",
2484 "SampleAfterValue": "100000",
2485 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
2486 "Offcore": "1"
2487 },
2488 {
2489 "EventCode": "0xB7",
2490 "MSRValue": "0x480",
2491 "Counter": "2",
2492 "UMask": "0x1",
2493 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2494 "MSRIndex": "0x1A6",
2495 "SampleAfterValue": "100000",
2496 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
2497 "Offcore": "1"
2498 },
2499 {
2500 "EventCode": "0xB7",
2501 "MSRValue": "0x780",
2502 "Counter": "2",
2503 "UMask": "0x1",
2504 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2505 "MSRIndex": "0x1A6",
2506 "SampleAfterValue": "100000",
2507 "BriefDescription": "Offcore other requests satisfied by the LLC",
2508 "Offcore": "1"
2509 },
2510 {
2511 "EventCode": "0xB7",
2512 "MSRValue": "0x4780",
2513 "Counter": "2",
2514 "UMask": "0x1",
2515 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
2516 "MSRIndex": "0x1A6",
2517 "SampleAfterValue": "100000",
2518 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
2519 "Offcore": "1"
2520 },
2521 {
2522 "EventCode": "0xB7",
2523 "MSRValue": "0x1880",
2524 "Counter": "2",
2525 "UMask": "0x1",
2526 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
2527 "MSRIndex": "0x1A6",
2528 "SampleAfterValue": "100000",
2529 "BriefDescription": "Offcore other requests satisfied by a remote cache",
2530 "Offcore": "1"
2531 },
2532 {
2533 "EventCode": "0xB7",
2534 "MSRValue": "0x3880",
2535 "Counter": "2",
2536 "UMask": "0x1",
2537 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
2538 "MSRIndex": "0x1A6",
2539 "SampleAfterValue": "100000",
2540 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
2541 "Offcore": "1"
2542 },
2543 {
2544 "EventCode": "0xB7",
2545 "MSRValue": "0x1080",
2546 "Counter": "2",
2547 "UMask": "0x1",
2548 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
2549 "MSRIndex": "0x1A6",
2550 "SampleAfterValue": "100000",
2551 "BriefDescription": "Offcore other requests that HIT in a remote cache",
2552 "Offcore": "1"
2553 },
2554 {
2555 "EventCode": "0xB7",
2556 "MSRValue": "0x880",
2557 "Counter": "2",
2558 "UMask": "0x1",
2559 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2560 "MSRIndex": "0x1A6",
2561 "SampleAfterValue": "100000",
2562 "BriefDescription": "Offcore other requests that HITM in a remote cache",
2563 "Offcore": "1"
2564 },
2565 {
2566 "EventCode": "0xB7",
2567 "MSRValue": "0x7F30",
2568 "Counter": "2",
2569 "UMask": "0x1",
2570 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2571 "MSRIndex": "0x1A6",
2572 "SampleAfterValue": "100000",
2573 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
2574 "Offcore": "1"
2575 },
2576 {
2577 "EventCode": "0xB7",
2578 "MSRValue": "0xFF30",
2579 "Counter": "2",
2580 "UMask": "0x1",
2581 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2582 "MSRIndex": "0x1A6",
2583 "SampleAfterValue": "100000",
2584 "BriefDescription": "All offcore prefetch data requests",
2585 "Offcore": "1"
2586 },
2587 {
2588 "EventCode": "0xB7",
2589 "MSRValue": "0x8030",
2590 "Counter": "2",
2591 "UMask": "0x1",
2592 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2593 "MSRIndex": "0x1A6",
2594 "SampleAfterValue": "100000",
2595 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
2596 "Offcore": "1"
2597 },
2598 {
2599 "EventCode": "0xB7",
2600 "MSRValue": "0x130",
2601 "Counter": "2",
2602 "UMask": "0x1",
2603 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2604 "MSRIndex": "0x1A6",
2605 "SampleAfterValue": "100000",
2606 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
2607 "Offcore": "1"
2608 },
2609 {
2610 "EventCode": "0xB7",
2611 "MSRValue": "0x230",
2612 "Counter": "2",
2613 "UMask": "0x1",
2614 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2615 "MSRIndex": "0x1A6",
2616 "SampleAfterValue": "100000",
2617 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
2618 "Offcore": "1"
2619 },
2620 {
2621 "EventCode": "0xB7",
2622 "MSRValue": "0x430",
2623 "Counter": "2",
2624 "UMask": "0x1",
2625 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2626 "MSRIndex": "0x1A6",
2627 "SampleAfterValue": "100000",
2628 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
2629 "Offcore": "1"
2630 },
2631 {
2632 "EventCode": "0xB7",
2633 "MSRValue": "0x730",
2634 "Counter": "2",
2635 "UMask": "0x1",
2636 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2637 "MSRIndex": "0x1A6",
2638 "SampleAfterValue": "100000",
2639 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
2640 "Offcore": "1"
2641 },
2642 {
2643 "EventCode": "0xB7",
2644 "MSRValue": "0x4730",
2645 "Counter": "2",
2646 "UMask": "0x1",
2647 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
2648 "MSRIndex": "0x1A6",
2649 "SampleAfterValue": "100000",
2650 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
2651 "Offcore": "1"
2652 },
2653 {
2654 "EventCode": "0xB7",
2655 "MSRValue": "0x1830",
2656 "Counter": "2",
2657 "UMask": "0x1",
2658 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
2659 "MSRIndex": "0x1A6",
2660 "SampleAfterValue": "100000",
2661 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
2662 "Offcore": "1"
2663 },
2664 {
2665 "EventCode": "0xB7",
2666 "MSRValue": "0x3830",
2667 "Counter": "2",
2668 "UMask": "0x1",
2669 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
2670 "MSRIndex": "0x1A6",
2671 "SampleAfterValue": "100000",
2672 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
2673 "Offcore": "1"
2674 },
2675 {
2676 "EventCode": "0xB7",
2677 "MSRValue": "0x1030",
2678 "Counter": "2",
2679 "UMask": "0x1",
2680 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
2681 "MSRIndex": "0x1A6",
2682 "SampleAfterValue": "100000",
2683 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
2684 "Offcore": "1"
2685 },
2686 {
2687 "EventCode": "0xB7",
2688 "MSRValue": "0x830",
2689 "Counter": "2",
2690 "UMask": "0x1",
2691 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2692 "MSRIndex": "0x1A6",
2693 "SampleAfterValue": "100000",
2694 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
2695 "Offcore": "1"
2696 },
2697 {
2698 "EventCode": "0xB7",
2699 "MSRValue": "0x7F10",
2700 "Counter": "2",
2701 "UMask": "0x1",
2702 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2703 "MSRIndex": "0x1A6",
2704 "SampleAfterValue": "100000",
2705 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
2706 "Offcore": "1"
2707 },
2708 {
2709 "EventCode": "0xB7",
2710 "MSRValue": "0xFF10",
2711 "Counter": "2",
2712 "UMask": "0x1",
2713 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2714 "MSRIndex": "0x1A6",
2715 "SampleAfterValue": "100000",
2716 "BriefDescription": "All offcore prefetch data reads",
2717 "Offcore": "1"
2718 },
2719 {
2720 "EventCode": "0xB7",
2721 "MSRValue": "0x8010",
2722 "Counter": "2",
2723 "UMask": "0x1",
2724 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2725 "MSRIndex": "0x1A6",
2726 "SampleAfterValue": "100000",
2727 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
2728 "Offcore": "1"
2729 },
2730 {
2731 "EventCode": "0xB7",
2732 "MSRValue": "0x110",
2733 "Counter": "2",
2734 "UMask": "0x1",
2735 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2736 "MSRIndex": "0x1A6",
2737 "SampleAfterValue": "100000",
2738 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
2739 "Offcore": "1"
2740 },
2741 {
2742 "EventCode": "0xB7",
2743 "MSRValue": "0x210",
2744 "Counter": "2",
2745 "UMask": "0x1",
2746 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2747 "MSRIndex": "0x1A6",
2748 "SampleAfterValue": "100000",
2749 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
2750 "Offcore": "1"
2751 },
2752 {
2753 "EventCode": "0xB7",
2754 "MSRValue": "0x410",
2755 "Counter": "2",
2756 "UMask": "0x1",
2757 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2758 "MSRIndex": "0x1A6",
2759 "SampleAfterValue": "100000",
2760 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
2761 "Offcore": "1"
2762 },
2763 {
2764 "EventCode": "0xB7",
2765 "MSRValue": "0x710",
2766 "Counter": "2",
2767 "UMask": "0x1",
2768 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2769 "MSRIndex": "0x1A6",
2770 "SampleAfterValue": "100000",
2771 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
2772 "Offcore": "1"
2773 },
2774 {
2775 "EventCode": "0xB7",
2776 "MSRValue": "0x4710",
2777 "Counter": "2",
2778 "UMask": "0x1",
2779 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
2780 "MSRIndex": "0x1A6",
2781 "SampleAfterValue": "100000",
2782 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
2783 "Offcore": "1"
2784 },
2785 {
2786 "EventCode": "0xB7",
2787 "MSRValue": "0x1810",
2788 "Counter": "2",
2789 "UMask": "0x1",
2790 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
2791 "MSRIndex": "0x1A6",
2792 "SampleAfterValue": "100000",
2793 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
2794 "Offcore": "1"
2795 },
2796 {
2797 "EventCode": "0xB7",
2798 "MSRValue": "0x3810",
2799 "Counter": "2",
2800 "UMask": "0x1",
2801 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
2802 "MSRIndex": "0x1A6",
2803 "SampleAfterValue": "100000",
2804 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
2805 "Offcore": "1"
2806 },
2807 {
2808 "EventCode": "0xB7",
2809 "MSRValue": "0x1010",
2810 "Counter": "2",
2811 "UMask": "0x1",
2812 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
2813 "MSRIndex": "0x1A6",
2814 "SampleAfterValue": "100000",
2815 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
2816 "Offcore": "1"
2817 },
2818 {
2819 "EventCode": "0xB7",
2820 "MSRValue": "0x810",
2821 "Counter": "2",
2822 "UMask": "0x1",
2823 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2824 "MSRIndex": "0x1A6",
2825 "SampleAfterValue": "100000",
2826 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
2827 "Offcore": "1"
2828 },
2829 {
2830 "EventCode": "0xB7",
2831 "MSRValue": "0x7F40",
2832 "Counter": "2",
2833 "UMask": "0x1",
2834 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2835 "MSRIndex": "0x1A6",
2836 "SampleAfterValue": "100000",
2837 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
2838 "Offcore": "1"
2839 },
2840 {
2841 "EventCode": "0xB7",
2842 "MSRValue": "0xFF40",
2843 "Counter": "2",
2844 "UMask": "0x1",
2845 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2846 "MSRIndex": "0x1A6",
2847 "SampleAfterValue": "100000",
2848 "BriefDescription": "All offcore prefetch code reads",
2849 "Offcore": "1"
2850 },
2851 {
2852 "EventCode": "0xB7",
2853 "MSRValue": "0x8040",
2854 "Counter": "2",
2855 "UMask": "0x1",
2856 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2857 "MSRIndex": "0x1A6",
2858 "SampleAfterValue": "100000",
2859 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
2860 "Offcore": "1"
2861 },
2862 {
2863 "EventCode": "0xB7",
2864 "MSRValue": "0x140",
2865 "Counter": "2",
2866 "UMask": "0x1",
2867 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2868 "MSRIndex": "0x1A6",
2869 "SampleAfterValue": "100000",
2870 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
2871 "Offcore": "1"
2872 },
2873 {
2874 "EventCode": "0xB7",
2875 "MSRValue": "0x240",
2876 "Counter": "2",
2877 "UMask": "0x1",
2878 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2879 "MSRIndex": "0x1A6",
2880 "SampleAfterValue": "100000",
2881 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
2882 "Offcore": "1"
2883 },
2884 {
2885 "EventCode": "0xB7",
2886 "MSRValue": "0x440",
2887 "Counter": "2",
2888 "UMask": "0x1",
2889 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2890 "MSRIndex": "0x1A6",
2891 "SampleAfterValue": "100000",
2892 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
2893 "Offcore": "1"
2894 },
2895 {
2896 "EventCode": "0xB7",
2897 "MSRValue": "0x740",
2898 "Counter": "2",
2899 "UMask": "0x1",
2900 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2901 "MSRIndex": "0x1A6",
2902 "SampleAfterValue": "100000",
2903 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
2904 "Offcore": "1"
2905 },
2906 {
2907 "EventCode": "0xB7",
2908 "MSRValue": "0x4740",
2909 "Counter": "2",
2910 "UMask": "0x1",
2911 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
2912 "MSRIndex": "0x1A6",
2913 "SampleAfterValue": "100000",
2914 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
2915 "Offcore": "1"
2916 },
2917 {
2918 "EventCode": "0xB7",
2919 "MSRValue": "0x1840",
2920 "Counter": "2",
2921 "UMask": "0x1",
2922 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
2923 "MSRIndex": "0x1A6",
2924 "SampleAfterValue": "100000",
2925 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
2926 "Offcore": "1"
2927 },
2928 {
2929 "EventCode": "0xB7",
2930 "MSRValue": "0x3840",
2931 "Counter": "2",
2932 "UMask": "0x1",
2933 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
2934 "MSRIndex": "0x1A6",
2935 "SampleAfterValue": "100000",
2936 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
2937 "Offcore": "1"
2938 },
2939 {
2940 "EventCode": "0xB7",
2941 "MSRValue": "0x1040",
2942 "Counter": "2",
2943 "UMask": "0x1",
2944 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
2945 "MSRIndex": "0x1A6",
2946 "SampleAfterValue": "100000",
2947 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
2948 "Offcore": "1"
2949 },
2950 {
2951 "EventCode": "0xB7",
2952 "MSRValue": "0x840",
2953 "Counter": "2",
2954 "UMask": "0x1",
2955 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2956 "MSRIndex": "0x1A6",
2957 "SampleAfterValue": "100000",
2958 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
2959 "Offcore": "1"
2960 },
2961 {
2962 "EventCode": "0xB7",
2963 "MSRValue": "0x7F20",
2964 "Counter": "2",
2965 "UMask": "0x1",
2966 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2967 "MSRIndex": "0x1A6",
2968 "SampleAfterValue": "100000",
2969 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
2970 "Offcore": "1"
2971 },
2972 {
2973 "EventCode": "0xB7",
2974 "MSRValue": "0xFF20",
2975 "Counter": "2",
2976 "UMask": "0x1",
2977 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2978 "MSRIndex": "0x1A6",
2979 "SampleAfterValue": "100000",
2980 "BriefDescription": "All offcore prefetch RFO requests",
2981 "Offcore": "1"
2982 },
2983 {
2984 "EventCode": "0xB7",
2985 "MSRValue": "0x8020",
2986 "Counter": "2",
2987 "UMask": "0x1",
2988 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2989 "MSRIndex": "0x1A6",
2990 "SampleAfterValue": "100000",
2991 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
2992 "Offcore": "1"
2993 },
2994 {
2995 "EventCode": "0xB7",
2996 "MSRValue": "0x120",
2997 "Counter": "2",
2998 "UMask": "0x1",
2999 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
3000 "MSRIndex": "0x1A6",
3001 "SampleAfterValue": "100000",
3002 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
3003 "Offcore": "1"
3004 },
3005 {
3006 "EventCode": "0xB7",
3007 "MSRValue": "0x220",
3008 "Counter": "2",
3009 "UMask": "0x1",
3010 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
3011 "MSRIndex": "0x1A6",
3012 "SampleAfterValue": "100000",
3013 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
3014 "Offcore": "1"
3015 },
3016 {
3017 "EventCode": "0xB7",
3018 "MSRValue": "0x420",
3019 "Counter": "2",
3020 "UMask": "0x1",
3021 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
3022 "MSRIndex": "0x1A6",
3023 "SampleAfterValue": "100000",
3024 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
3025 "Offcore": "1"
3026 },
3027 {
3028 "EventCode": "0xB7",
3029 "MSRValue": "0x720",
3030 "Counter": "2",
3031 "UMask": "0x1",
3032 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
3033 "MSRIndex": "0x1A6",
3034 "SampleAfterValue": "100000",
3035 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
3036 "Offcore": "1"
3037 },
3038 {
3039 "EventCode": "0xB7",
3040 "MSRValue": "0x4720",
3041 "Counter": "2",
3042 "UMask": "0x1",
3043 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
3044 "MSRIndex": "0x1A6",
3045 "SampleAfterValue": "100000",
3046 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
3047 "Offcore": "1"
3048 },
3049 {
3050 "EventCode": "0xB7",
3051 "MSRValue": "0x1820",
3052 "Counter": "2",
3053 "UMask": "0x1",
3054 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
3055 "MSRIndex": "0x1A6",
3056 "SampleAfterValue": "100000",
3057 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
3058 "Offcore": "1"
3059 },
3060 {
3061 "EventCode": "0xB7",
3062 "MSRValue": "0x3820",
3063 "Counter": "2",
3064 "UMask": "0x1",
3065 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
3066 "MSRIndex": "0x1A6",
3067 "SampleAfterValue": "100000",
3068 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
3069 "Offcore": "1"
3070 },
3071 {
3072 "EventCode": "0xB7",
3073 "MSRValue": "0x1020",
3074 "Counter": "2",
3075 "UMask": "0x1",
3076 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
3077 "MSRIndex": "0x1A6",
3078 "SampleAfterValue": "100000",
3079 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
3080 "Offcore": "1"
3081 },
3082 {
3083 "EventCode": "0xB7",
3084 "MSRValue": "0x820",
3085 "Counter": "2",
3086 "UMask": "0x1",
3087 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
3088 "MSRIndex": "0x1A6",
3089 "SampleAfterValue": "100000",
3090 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
3091 "Offcore": "1"
3092 },
3093 {
3094 "EventCode": "0xB7",
3095 "MSRValue": "0x7F70",
3096 "Counter": "2",
3097 "UMask": "0x1",
3098 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
3099 "MSRIndex": "0x1A6",
3100 "SampleAfterValue": "100000",
3101 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
3102 "Offcore": "1"
3103 },
3104 {
3105 "EventCode": "0xB7",
3106 "MSRValue": "0xFF70",
3107 "Counter": "2",
3108 "UMask": "0x1",
3109 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
3110 "MSRIndex": "0x1A6",
3111 "SampleAfterValue": "100000",
3112 "BriefDescription": "All offcore prefetch requests",
3113 "Offcore": "1"
3114 },
3115 {
3116 "EventCode": "0xB7",
3117 "MSRValue": "0x8070",
3118 "Counter": "2",
3119 "UMask": "0x1",
3120 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
3121 "MSRIndex": "0x1A6",
3122 "SampleAfterValue": "100000",
3123 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
3124 "Offcore": "1"
3125 },
3126 {
3127 "EventCode": "0xB7",
3128 "MSRValue": "0x170",
3129 "Counter": "2",
3130 "UMask": "0x1",
3131 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
3132 "MSRIndex": "0x1A6",
3133 "SampleAfterValue": "100000",
3134 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
3135 "Offcore": "1"
3136 },
3137 {
3138 "EventCode": "0xB7",
3139 "MSRValue": "0x270",
3140 "Counter": "2",
3141 "UMask": "0x1",
3142 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
3143 "MSRIndex": "0x1A6",
3144 "SampleAfterValue": "100000",
3145 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
3146 "Offcore": "1"
3147 },
3148 {
3149 "EventCode": "0xB7",
3150 "MSRValue": "0x470",
3151 "Counter": "2",
3152 "UMask": "0x1",
3153 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
3154 "MSRIndex": "0x1A6",
3155 "SampleAfterValue": "100000",
3156 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
3157 "Offcore": "1"
3158 },
3159 {
3160 "EventCode": "0xB7",
3161 "MSRValue": "0x770",
3162 "Counter": "2",
3163 "UMask": "0x1",
3164 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
3165 "MSRIndex": "0x1A6",
3166 "SampleAfterValue": "100000",
3167 "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
3168 "Offcore": "1"
3169 },
3170 {
3171 "EventCode": "0xB7",
3172 "MSRValue": "0x4770",
3173 "Counter": "2",
3174 "UMask": "0x1",
3175 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
3176 "MSRIndex": "0x1A6",
3177 "SampleAfterValue": "100000",
3178 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
3179 "Offcore": "1"
3180 },
3181 {
3182 "EventCode": "0xB7",
3183 "MSRValue": "0x1870",
3184 "Counter": "2",
3185 "UMask": "0x1",
3186 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
3187 "MSRIndex": "0x1A6",
3188 "SampleAfterValue": "100000",
3189 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
3190 "Offcore": "1"
3191 },
3192 {
3193 "EventCode": "0xB7",
3194 "MSRValue": "0x3870",
3195 "Counter": "2",
3196 "UMask": "0x1",
3197 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
3198 "MSRIndex": "0x1A6",
3199 "SampleAfterValue": "100000",
3200 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
3201 "Offcore": "1"
3202 },
3203 {
3204 "EventCode": "0xB7",
3205 "MSRValue": "0x1070",
3206 "Counter": "2",
3207 "UMask": "0x1",
3208 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
3209 "MSRIndex": "0x1A6",
3210 "SampleAfterValue": "100000",
3211 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
3212 "Offcore": "1"
3213 },
3214 {
3215 "EventCode": "0xB7",
3216 "MSRValue": "0x870",
3217 "Counter": "2",
3218 "UMask": "0x1",
3219 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
3220 "MSRIndex": "0x1A6",
3221 "SampleAfterValue": "100000",
3222 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
3223 "Offcore": "1"
3224 }
3225] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
new file mode 100644
index 000000000000..7d2f71a9dee3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
@@ -0,0 +1,229 @@
1[
2 {
3 "PEBS": "1",
4 "EventCode": "0xF7",
5 "Counter": "0,1,2,3",
6 "UMask": "0x1",
7 "EventName": "FP_ASSIST.ALL",
8 "SampleAfterValue": "20000",
9 "BriefDescription": "X87 Floating point assists (Precise Event)"
10 },
11 {
12 "PEBS": "1",
13 "EventCode": "0xF7",
14 "Counter": "0,1,2,3",
15 "UMask": "0x4",
16 "EventName": "FP_ASSIST.INPUT",
17 "SampleAfterValue": "20000",
18 "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)"
19 },
20 {
21 "PEBS": "1",
22 "EventCode": "0xF7",
23 "Counter": "0,1,2,3",
24 "UMask": "0x2",
25 "EventName": "FP_ASSIST.OUTPUT",
26 "SampleAfterValue": "20000",
27 "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)"
28 },
29 {
30 "EventCode": "0x10",
31 "Counter": "0,1,2,3",
32 "UMask": "0x2",
33 "EventName": "FP_COMP_OPS_EXE.MMX",
34 "SampleAfterValue": "2000000",
35 "BriefDescription": "MMX Uops"
36 },
37 {
38 "EventCode": "0x10",
39 "Counter": "0,1,2,3",
40 "UMask": "0x80",
41 "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
42 "SampleAfterValue": "2000000",
43 "BriefDescription": "SSE* FP double precision Uops"
44 },
45 {
46 "EventCode": "0x10",
47 "Counter": "0,1,2,3",
48 "UMask": "0x4",
49 "EventName": "FP_COMP_OPS_EXE.SSE_FP",
50 "SampleAfterValue": "2000000",
51 "BriefDescription": "SSE and SSE2 FP Uops"
52 },
53 {
54 "EventCode": "0x10",
55 "Counter": "0,1,2,3",
56 "UMask": "0x10",
57 "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
58 "SampleAfterValue": "2000000",
59 "BriefDescription": "SSE FP packed Uops"
60 },
61 {
62 "EventCode": "0x10",
63 "Counter": "0,1,2,3",
64 "UMask": "0x20",
65 "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
66 "SampleAfterValue": "2000000",
67 "BriefDescription": "SSE FP scalar Uops"
68 },
69 {
70 "EventCode": "0x10",
71 "Counter": "0,1,2,3",
72 "UMask": "0x40",
73 "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
74 "SampleAfterValue": "2000000",
75 "BriefDescription": "SSE* FP single precision Uops"
76 },
77 {
78 "EventCode": "0x10",
79 "Counter": "0,1,2,3",
80 "UMask": "0x8",
81 "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
82 "SampleAfterValue": "2000000",
83 "BriefDescription": "SSE2 integer Uops"
84 },
85 {
86 "EventCode": "0x10",
87 "Counter": "0,1,2,3",
88 "UMask": "0x1",
89 "EventName": "FP_COMP_OPS_EXE.X87",
90 "SampleAfterValue": "2000000",
91 "BriefDescription": "Computational floating-point operations executed"
92 },
93 {
94 "EventCode": "0xCC",
95 "Counter": "0,1,2,3",
96 "UMask": "0x3",
97 "EventName": "FP_MMX_TRANS.ANY",
98 "SampleAfterValue": "2000000",
99 "BriefDescription": "All Floating Point to and from MMX transitions"
100 },
101 {
102 "EventCode": "0xCC",
103 "Counter": "0,1,2,3",
104 "UMask": "0x1",
105 "EventName": "FP_MMX_TRANS.TO_FP",
106 "SampleAfterValue": "2000000",
107 "BriefDescription": "Transitions from MMX to Floating Point instructions"
108 },
109 {
110 "EventCode": "0xCC",
111 "Counter": "0,1,2,3",
112 "UMask": "0x2",
113 "EventName": "FP_MMX_TRANS.TO_MMX",
114 "SampleAfterValue": "2000000",
115 "BriefDescription": "Transitions from Floating Point to MMX instructions"
116 },
117 {
118 "EventCode": "0x12",
119 "Counter": "0,1,2,3",
120 "UMask": "0x4",
121 "EventName": "SIMD_INT_128.PACK",
122 "SampleAfterValue": "200000",
123 "BriefDescription": "128 bit SIMD integer pack operations"
124 },
125 {
126 "EventCode": "0x12",
127 "Counter": "0,1,2,3",
128 "UMask": "0x20",
129 "EventName": "SIMD_INT_128.PACKED_ARITH",
130 "SampleAfterValue": "200000",
131 "BriefDescription": "128 bit SIMD integer arithmetic operations"
132 },
133 {
134 "EventCode": "0x12",
135 "Counter": "0,1,2,3",
136 "UMask": "0x10",
137 "EventName": "SIMD_INT_128.PACKED_LOGICAL",
138 "SampleAfterValue": "200000",
139 "BriefDescription": "128 bit SIMD integer logical operations"
140 },
141 {
142 "EventCode": "0x12",
143 "Counter": "0,1,2,3",
144 "UMask": "0x1",
145 "EventName": "SIMD_INT_128.PACKED_MPY",
146 "SampleAfterValue": "200000",
147 "BriefDescription": "128 bit SIMD integer multiply operations"
148 },
149 {
150 "EventCode": "0x12",
151 "Counter": "0,1,2,3",
152 "UMask": "0x2",
153 "EventName": "SIMD_INT_128.PACKED_SHIFT",
154 "SampleAfterValue": "200000",
155 "BriefDescription": "128 bit SIMD integer shift operations"
156 },
157 {
158 "EventCode": "0x12",
159 "Counter": "0,1,2,3",
160 "UMask": "0x40",
161 "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
162 "SampleAfterValue": "200000",
163 "BriefDescription": "128 bit SIMD integer shuffle/move operations"
164 },
165 {
166 "EventCode": "0x12",
167 "Counter": "0,1,2,3",
168 "UMask": "0x8",
169 "EventName": "SIMD_INT_128.UNPACK",
170 "SampleAfterValue": "200000",
171 "BriefDescription": "128 bit SIMD integer unpack operations"
172 },
173 {
174 "EventCode": "0xFD",
175 "Counter": "0,1,2,3",
176 "UMask": "0x4",
177 "EventName": "SIMD_INT_64.PACK",
178 "SampleAfterValue": "200000",
179 "BriefDescription": "SIMD integer 64 bit pack operations"
180 },
181 {
182 "EventCode": "0xFD",
183 "Counter": "0,1,2,3",
184 "UMask": "0x20",
185 "EventName": "SIMD_INT_64.PACKED_ARITH",
186 "SampleAfterValue": "200000",
187 "BriefDescription": "SIMD integer 64 bit arithmetic operations"
188 },
189 {
190 "EventCode": "0xFD",
191 "Counter": "0,1,2,3",
192 "UMask": "0x10",
193 "EventName": "SIMD_INT_64.PACKED_LOGICAL",
194 "SampleAfterValue": "200000",
195 "BriefDescription": "SIMD integer 64 bit logical operations"
196 },
197 {
198 "EventCode": "0xFD",
199 "Counter": "0,1,2,3",
200 "UMask": "0x1",
201 "EventName": "SIMD_INT_64.PACKED_MPY",
202 "SampleAfterValue": "200000",
203 "BriefDescription": "SIMD integer 64 bit packed multiply operations"
204 },
205 {
206 "EventCode": "0xFD",
207 "Counter": "0,1,2,3",
208 "UMask": "0x2",
209 "EventName": "SIMD_INT_64.PACKED_SHIFT",
210 "SampleAfterValue": "200000",
211 "BriefDescription": "SIMD integer 64 bit shift operations"
212 },
213 {
214 "EventCode": "0xFD",
215 "Counter": "0,1,2,3",
216 "UMask": "0x40",
217 "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
218 "SampleAfterValue": "200000",
219 "BriefDescription": "SIMD integer 64 bit shuffle/move operations"
220 },
221 {
222 "EventCode": "0xFD",
223 "Counter": "0,1,2,3",
224 "UMask": "0x8",
225 "EventName": "SIMD_INT_64.UNPACK",
226 "SampleAfterValue": "200000",
227 "BriefDescription": "SIMD integer 64 bit unpack operations"
228 }
229] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json
new file mode 100644
index 000000000000..e5e21e03444d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json
@@ -0,0 +1,26 @@
1[
2 {
3 "EventCode": "0xD0",
4 "Counter": "0,1,2,3",
5 "UMask": "0x1",
6 "EventName": "MACRO_INSTS.DECODED",
7 "SampleAfterValue": "2000000",
8 "BriefDescription": "Instructions decoded"
9 },
10 {
11 "EventCode": "0xA6",
12 "Counter": "0,1,2,3",
13 "UMask": "0x1",
14 "EventName": "MACRO_INSTS.FUSIONS_DECODED",
15 "SampleAfterValue": "2000000",
16 "BriefDescription": "Macro-fused instructions decoded"
17 },
18 {
19 "EventCode": "0x19",
20 "Counter": "0,1,2,3",
21 "UMask": "0x1",
22 "EventName": "TWO_UOP_INSTS_DECODED",
23 "SampleAfterValue": "2000000",
24 "BriefDescription": "Two Uop instructions decoded"
25 }
26] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/memory.json b/tools/perf/pmu-events/arch/x86/westmereex/memory.json
new file mode 100644
index 000000000000..3ba555e73cbd
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/westmereex/memory.json
@@ -0,0 +1,747 @@
1[
2 {
3 "EventCode": "0x5",
4 "Counter": "0,1,2,3",
5 "UMask": "0x2",
6 "EventName": "MISALIGN_MEM_REF.STORE",
7 "SampleAfterValue": "200000",
8 "BriefDescription": "Misaligned store references"
9 },
10 {
11 "EventCode": "0xB7",
12 "MSRValue": "0x6011",
13 "Counter": "2",
14 "UMask": "0x1",
15 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
16 "MSRIndex": "0x1A6",
17 "SampleAfterValue": "100000",
18 "BriefDescription": "Offcore data reads satisfied by any DRAM",
19 "Offcore": "1"
20 },
21 {
22 "EventCode": "0xB7",
23 "MSRValue": "0xF811",
24 "Counter": "2",
25 "UMask": "0x1",
26 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
27 "MSRIndex": "0x1A6",
28 "SampleAfterValue": "100000",
29 "BriefDescription": "Offcore data reads that missed the LLC",
30 "Offcore": "1"
31 },
32 {
33 "EventCode": "0xB7",
34 "MSRValue": "0x4011",
35 "Counter": "2",
36 "UMask": "0x1",
37 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
38 "MSRIndex": "0x1A6",
39 "SampleAfterValue": "100000",
40 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
41 "Offcore": "1"
42 },
43 {
44 "EventCode": "0xB7",
45 "MSRValue": "0x2011",
46 "Counter": "2",
47 "UMask": "0x1",
48 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
49 "MSRIndex": "0x1A6",
50 "SampleAfterValue": "100000",
51 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
52 "Offcore": "1"
53 },
54 {
55 "EventCode": "0xB7",
56 "MSRValue": "0x6044",
57 "Counter": "2",
58 "UMask": "0x1",
59 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
60 "MSRIndex": "0x1A6",
61 "SampleAfterValue": "100000",
62 "BriefDescription": "Offcore code reads satisfied by any DRAM",
63 "Offcore": "1"
64 },
65 {
66 "EventCode": "0xB7",
67 "MSRValue": "0xF844",
68 "Counter": "2",
69 "UMask": "0x1",
70 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
71 "MSRIndex": "0x1A6",
72 "SampleAfterValue": "100000",
73 "BriefDescription": "Offcore code reads that missed the LLC",
74 "Offcore": "1"
75 },
76 {
77 "EventCode": "0xB7",
78 "MSRValue": "0x4044",
79 "Counter": "2",
80 "UMask": "0x1",
81 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
82 "MSRIndex": "0x1A6",
83 "SampleAfterValue": "100000",
84 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
85 "Offcore": "1"
86 },
87 {
88 "EventCode": "0xB7",
89 "MSRValue": "0x2044",
90 "Counter": "2",
91 "UMask": "0x1",
92 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
93 "MSRIndex": "0x1A6",
94 "SampleAfterValue": "100000",
95 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
96 "Offcore": "1"
97 },
98 {
99 "EventCode": "0xB7",
100 "MSRValue": "0x60FF",
101 "Counter": "2",
102 "UMask": "0x1",
103 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
104 "MSRIndex": "0x1A6",
105 "SampleAfterValue": "100000",
106 "BriefDescription": "Offcore requests satisfied by any DRAM",
107 "Offcore": "1"
108 },
109 {
110 "EventCode": "0xB7",
111 "MSRValue": "0xF8FF",
112 "Counter": "2",
113 "UMask": "0x1",
114 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
115 "MSRIndex": "0x1A6",
116 "SampleAfterValue": "100000",
117 "BriefDescription": "Offcore requests that missed the LLC",
118 "Offcore": "1"
119 },
120 {
121 "EventCode": "0xB7",
122 "MSRValue": "0x40FF",
123 "Counter": "2",
124 "UMask": "0x1",
125 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
126 "MSRIndex": "0x1A6",
127 "SampleAfterValue": "100000",
128 "BriefDescription": "Offcore requests satisfied by the local DRAM",
129 "Offcore": "1"
130 },
131 {
132 "EventCode": "0xB7",
133 "MSRValue": "0x20FF",
134 "Counter": "2",
135 "UMask": "0x1",
136 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
137 "MSRIndex": "0x1A6",
138 "SampleAfterValue": "100000",
139 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
140 "Offcore": "1"
141 },
142 {
143 "EventCode": "0xB7",
144 "MSRValue": "0x6022",
145 "Counter": "2",
146 "UMask": "0x1",
147 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
148 "MSRIndex": "0x1A6",
149 "SampleAfterValue": "100000",
150 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
151 "Offcore": "1"
152 },
153 {
154 "EventCode": "0xB7",
155 "MSRValue": "0xF822",
156 "Counter": "2",
157 "UMask": "0x1",
158 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
159 "MSRIndex": "0x1A6",
160 "SampleAfterValue": "100000",
161 "BriefDescription": "Offcore RFO requests that missed the LLC",
162 "Offcore": "1"
163 },
164 {
165 "EventCode": "0xB7",
166 "MSRValue": "0x4022",
167 "Counter": "2",
168 "UMask": "0x1",
169 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
170 "MSRIndex": "0x1A6",
171 "SampleAfterValue": "100000",
172 "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
173 "Offcore": "1"
174 },
175 {
176 "EventCode": "0xB7",
177 "MSRValue": "0x2022",
178 "Counter": "2",
179 "UMask": "0x1",
180 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
181 "MSRIndex": "0x1A6",
182 "SampleAfterValue": "100000",
183 "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
184 "Offcore": "1"
185 },
186 {
187 "EventCode": "0xB7",
188 "MSRValue": "0x6008",
189 "Counter": "2",
190 "UMask": "0x1",
191 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
192 "MSRIndex": "0x1A6",
193 "SampleAfterValue": "100000",
194 "BriefDescription": "Offcore writebacks to any DRAM",
195 "Offcore": "1"
196 },
197 {
198 "EventCode": "0xB7",
199 "MSRValue": "0xF808",
200 "Counter": "2",
201 "UMask": "0x1",
202 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
203 "MSRIndex": "0x1A6",
204 "SampleAfterValue": "100000",
205 "BriefDescription": "Offcore writebacks that missed the LLC",
206 "Offcore": "1"
207 },
208 {
209 "EventCode": "0xB7",
210 "MSRValue": "0x4008",
211 "Counter": "2",
212 "UMask": "0x1",
213 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
214 "MSRIndex": "0x1A6",
215 "SampleAfterValue": "100000",
216 "BriefDescription": "Offcore writebacks to the local DRAM",
217 "Offcore": "1"
218 },
219 {
220 "EventCode": "0xB7",
221 "MSRValue": "0x2008",
222 "Counter": "2",
223 "UMask": "0x1",
224 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
225 "MSRIndex": "0x1A6",
226 "SampleAfterValue": "100000",
227 "BriefDescription": "Offcore writebacks to a remote DRAM",
228 "Offcore": "1"
229 },
230 {
231 "EventCode": "0xB7",
232 "MSRValue": "0x6077",
233 "Counter": "2",
234 "UMask": "0x1",
235 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
236 "MSRIndex": "0x1A6",
237 "SampleAfterValue": "100000",
238 "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
239 "Offcore": "1"
240 },
241 {
242 "EventCode": "0xB7",
243 "MSRValue": "0xF877",
244 "Counter": "2",
245 "UMask": "0x1",
246 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
247 "MSRIndex": "0x1A6",
248 "SampleAfterValue": "100000",
249 "BriefDescription": "Offcore code or data read requests that missed the LLC",
250 "Offcore": "1"
251 },
252 {
253 "EventCode": "0xB7",
254 "MSRValue": "0x4077",
255 "Counter": "2",
256 "UMask": "0x1",
257 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
258 "MSRIndex": "0x1A6",
259 "SampleAfterValue": "100000",
260 "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
261 "Offcore": "1"
262 },
263 {
264 "EventCode": "0xB7",
265 "MSRValue": "0x2077",
266 "Counter": "2",
267 "UMask": "0x1",
268 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
269 "MSRIndex": "0x1A6",
270 "SampleAfterValue": "100000",
271 "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
272 "Offcore": "1"
273 },
274 {
275 "EventCode": "0xB7",
276 "MSRValue": "0x6033",
277 "Counter": "2",
278 "UMask": "0x1",
279 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
280 "MSRIndex": "0x1A6",
281 "SampleAfterValue": "100000",
282 "BriefDescription": "Offcore request = all data, response = any DRAM",
283 "Offcore": "1"
284 },
285 {
286 "EventCode": "0xB7",
287 "MSRValue": "0xF833",
288 "Counter": "2",
289 "UMask": "0x1",
290 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
291 "MSRIndex": "0x1A6",
292 "SampleAfterValue": "100000",
293 "BriefDescription": "Offcore request = all data, response = any LLC miss",
294 "Offcore": "1"
295 },
296 {
297 "EventCode": "0xB7",
298 "MSRValue": "0x4033",
299 "Counter": "2",
300 "UMask": "0x1",
301 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
302 "MSRIndex": "0x1A6",
303 "SampleAfterValue": "100000",
304 "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",
305 "Offcore": "1"
306 },
307 {
308 "EventCode": "0xB7",
309 "MSRValue": "0x2033",
310 "Counter": "2",
311 "UMask": "0x1",
312 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
313 "MSRIndex": "0x1A6",
314 "SampleAfterValue": "100000",
315 "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",
316 "Offcore": "1"
317 },
318 {
319 "EventCode": "0xB7",
320 "MSRValue": "0x6003",
321 "Counter": "2",
322 "UMask": "0x1",
323 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
324 "MSRIndex": "0x1A6",
325 "SampleAfterValue": "100000",
326 "BriefDescription": "Offcore demand data requests satisfied by any DRAM",
327 "Offcore": "1"
328 },
329 {
330 "EventCode": "0xB7",
331 "MSRValue": "0xF803",
332 "Counter": "2",
333 "UMask": "0x1",
334 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
335 "MSRIndex": "0x1A6",
336 "SampleAfterValue": "100000",
337 "BriefDescription": "Offcore demand data requests that missed the LLC",
338 "Offcore": "1"
339 },
340 {
341 "EventCode": "0xB7",
342 "MSRValue": "0x4003",
343 "Counter": "2",
344 "UMask": "0x1",
345 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
346 "MSRIndex": "0x1A6",
347 "SampleAfterValue": "100000",
348 "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
349 "Offcore": "1"
350 },
351 {
352 "EventCode": "0xB7",
353 "MSRValue": "0x2003",
354 "Counter": "2",
355 "UMask": "0x1",
356 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
357 "MSRIndex": "0x1A6",
358 "SampleAfterValue": "100000",
359 "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
360 "Offcore": "1"
361 },
362 {
363 "EventCode": "0xB7",
364 "MSRValue": "0x6001",
365 "Counter": "2",
366 "UMask": "0x1",
367 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
368 "MSRIndex": "0x1A6",
369 "SampleAfterValue": "100000",
370 "BriefDescription": "Offcore demand data reads satisfied by any DRAM",
371 "Offcore": "1"
372 },
373 {
374 "EventCode": "0xB7",
375 "MSRValue": "0xF801",
376 "Counter": "2",
377 "UMask": "0x1",
378 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
379 "MSRIndex": "0x1A6",
380 "SampleAfterValue": "100000",
381 "BriefDescription": "Offcore demand data reads that missed the LLC",
382 "Offcore": "1"
383 },
384 {
385 "EventCode": "0xB7",
386 "MSRValue": "0x4001",
387 "Counter": "2",
388 "UMask": "0x1",
389 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
390 "MSRIndex": "0x1A6",
391 "SampleAfterValue": "100000",
392 "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
393 "Offcore": "1"
394 },
395 {
396 "EventCode": "0xB7",
397 "MSRValue": "0x2001",
398 "Counter": "2",
399 "UMask": "0x1",
400 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
401 "MSRIndex": "0x1A6",
402 "SampleAfterValue": "100000",
403 "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
404 "Offcore": "1"
405 },
406 {
407 "EventCode": "0xB7",
408 "MSRValue": "0x6004",
409 "Counter": "2",
410 "UMask": "0x1",
411 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
412 "MSRIndex": "0x1A6",
413 "SampleAfterValue": "100000",
414 "BriefDescription": "Offcore demand code reads satisfied by any DRAM",
415 "Offcore": "1"
416 },
417 {
418 "EventCode": "0xB7",
419 "MSRValue": "0xF804",
420 "Counter": "2",
421 "UMask": "0x1",
422 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
423 "MSRIndex": "0x1A6",
424 "SampleAfterValue": "100000",
425 "BriefDescription": "Offcore demand code reads that missed the LLC",
426 "Offcore": "1"
427 },
428 {
429 "EventCode": "0xB7",
430 "MSRValue": "0x4004",
431 "Counter": "2",
432 "UMask": "0x1",
433 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
434 "MSRIndex": "0x1A6",
435 "SampleAfterValue": "100000",
436 "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
437 "Offcore": "1"
438 },
439 {
440 "EventCode": "0xB7",
441 "MSRValue": "0x2004",
442 "Counter": "2",
443 "UMask": "0x1",
444 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
445 "MSRIndex": "0x1A6",
446 "SampleAfterValue": "100000",
447 "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
448 "Offcore": "1"
449 },
450 {
451 "EventCode": "0xB7",
452 "MSRValue": "0x6002",
453 "Counter": "2",
454 "UMask": "0x1",
455 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
456 "MSRIndex": "0x1A6",
457 "SampleAfterValue": "100000",
458 "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
459 "Offcore": "1"
460 },
461 {
462 "EventCode": "0xB7",
463 "MSRValue": "0xF802",
464 "Counter": "2",
465 "UMask": "0x1",
466 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
467 "MSRIndex": "0x1A6",
468 "SampleAfterValue": "100000",
469 "BriefDescription": "Offcore demand RFO requests that missed the LLC",
470 "Offcore": "1"
471 },
472 {
473 "EventCode": "0xB7",
474 "MSRValue": "0x4002",
475 "Counter": "2",
476 "UMask": "0x1",
477 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
478 "MSRIndex": "0x1A6",
479 "SampleAfterValue": "100000",
480 "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
481 "Offcore": "1"
482 },
483 {
484 "EventCode": "0xB7",
485 "MSRValue": "0x2002",
486 "Counter": "2",
487 "UMask": "0x1",
488 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
489 "MSRIndex": "0x1A6",
490 "SampleAfterValue": "100000",
491 "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
492 "Offcore": "1"
493 },
494 {
495 "EventCode": "0xB7",
496 "MSRValue": "0x6080",
497 "Counter": "2",
498 "UMask": "0x1",
499 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
500 "MSRIndex": "0x1A6",
501 "SampleAfterValue": "100000",
502 "BriefDescription": "Offcore other requests satisfied by any DRAM",
503 "Offcore": "1"
504 },
505 {
506 "EventCode": "0xB7",
507 "MSRValue": "0xF880",
508 "Counter": "2",
509 "UMask": "0x1",
510 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
511 "MSRIndex": "0x1A6",
512 "SampleAfterValue": "100000",
513 "BriefDescription": "Offcore other requests that missed the LLC",
514 "Offcore": "1"
515 },
516 {
517 "EventCode": "0xB7",
518 "MSRValue": "0x2080",
519 "Counter": "2",
520 "UMask": "0x1",
521 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
522 "MSRIndex": "0x1A6",
523 "SampleAfterValue": "100000",
524 "BriefDescription": "Offcore other requests satisfied by a remote DRAM",
525 "Offcore": "1"
526 },
527 {
528 "EventCode": "0xB7",
529 "MSRValue": "0x6030",
530 "Counter": "2",
531 "UMask": "0x1",
532 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
533 "MSRIndex": "0x1A6",
534 "SampleAfterValue": "100000",
535 "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
536 "Offcore": "1"
537 },
538 {
539 "EventCode": "0xB7",
540 "MSRValue": "0xF830",
541 "Counter": "2",
542 "UMask": "0x1",
543 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
544 "MSRIndex": "0x1A6",
545 "SampleAfterValue": "100000",
546 "BriefDescription": "Offcore prefetch data requests that missed the LLC",
547 "Offcore": "1"
548 },
549 {
550 "EventCode": "0xB7",
551 "MSRValue": "0x4030",
552 "Counter": "2",
553 "UMask": "0x1",
554 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
555 "MSRIndex": "0x1A6",
556 "SampleAfterValue": "100000",
557 "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
558 "Offcore": "1"
559 },
560 {
561 "EventCode": "0xB7",
562 "MSRValue": "0x2030",
563 "Counter": "2",
564 "UMask": "0x1",
565 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
566 "MSRIndex": "0x1A6",
567 "SampleAfterValue": "100000",
568 "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
569 "Offcore": "1"
570 },
571 {
572 "EventCode": "0xB7",
573 "MSRValue": "0x6010",
574 "Counter": "2",
575 "UMask": "0x1",
576 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
577 "MSRIndex": "0x1A6",
578 "SampleAfterValue": "100000",
579 "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
580 "Offcore": "1"
581 },
582 {
583 "EventCode": "0xB7",
584 "MSRValue": "0xF810",
585 "Counter": "2",
586 "UMask": "0x1",
587 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
588 "MSRIndex": "0x1A6",
589 "SampleAfterValue": "100000",
590 "BriefDescription": "Offcore prefetch data reads that missed the LLC",
591 "Offcore": "1"
592 },
593 {
594 "EventCode": "0xB7",
595 "MSRValue": "0x4010",
596 "Counter": "2",
597 "UMask": "0x1",
598 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
599 "MSRIndex": "0x1A6",
600 "SampleAfterValue": "100000",
601 "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
602 "Offcore": "1"
603 },
604 {
605 "EventCode": "0xB7",
606 "MSRValue": "0x2010",
607 "Counter": "2",
608 "UMask": "0x1",
609 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
610 "MSRIndex": "0x1A6",
611 "SampleAfterValue": "100000",
612 "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
613 "Offcore": "1"
614 },
615 {
616 "EventCode": "0xB7",
617 "MSRValue": "0x6040",
618 "Counter": "2",
619 "UMask": "0x1",
620 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
621 "MSRIndex": "0x1A6",
622 "SampleAfterValue": "100000",
623 "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
624 "Offcore": "1"
625 },
626 {
627 "EventCode": "0xB7",
628 "MSRValue": "0xF840",
629 "Counter": "2",
630 "UMask": "0x1",
631 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
632 "MSRIndex": "0x1A6",
633 "SampleAfterValue": "100000",
634 "BriefDescription": "Offcore prefetch code reads that missed the LLC",
635 "Offcore": "1"
636 },
637 {
638 "EventCode": "0xB7",
639 "MSRValue": "0x4040",
640 "Counter": "2",
641 "UMask": "0x1",
642 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
643 "MSRIndex": "0x1A6",
644 "SampleAfterValue": "100000",
645 "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
646 "Offcore": "1"
647 },
648 {
649 "EventCode": "0xB7",
650 "MSRValue": "0x2040",
651 "Counter": "2",
652 "UMask": "0x1",
653 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
654 "MSRIndex": "0x1A6",
655 "SampleAfterValue": "100000",
656 "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
657 "Offcore": "1"
658 },
659 {
660 "EventCode": "0xB7",
661 "MSRValue": "0x6020",
662 "Counter": "2",
663 "UMask": "0x1",
664 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
665 "MSRIndex": "0x1A6",
666 "SampleAfterValue": "100000",
667 "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
668 "Offcore": "1"
669 },
670 {
671 "EventCode": "0xB7",
672 "MSRValue": "0xF820",
673 "Counter": "2",
674 "UMask": "0x1",
675 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
676 "MSRIndex": "0x1A6",
677 "SampleAfterValue": "100000",
678 "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
679 "Offcore": "1"
680 },
681 {
682 "EventCode": "0xB7",
683 "MSRValue": "0x4020",
684 "Counter": "2",
685 "UMask": "0x1",
686 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
687 "MSRIndex": "0x1A6",
688 "SampleAfterValue": "100000",
689 "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
690 "Offcore": "1"
691 },
692 {
693 "EventCode": "0xB7",
694 "MSRValue": "0x2020",
695 "Counter": "2",
696 "UMask": "0x1",
697 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
698 "MSRIndex": "0x1A6",
699 "SampleAfterValue": "100000",
700 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
701 "Offcore": "1"
702 },
703 {
704 "EventCode": "0xB7",
705 "MSRValue": "0x6070",
706 "Counter": "2",
707 "UMask": "0x1",
708 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
709 "MSRIndex": "0x1A6",
710 "SampleAfterValue": "100000",
711 "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
712 "Offcore": "1"
713 },
714 {
715 "EventCode": "0xB7",
716 "MSRValue": "0xF870",
717 "Counter": "2",
718 "UMask": "0x1",
719 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
720 "MSRIndex": "0x1A6",
721 "SampleAfterValue": "100000",
722 "BriefDescription": "Offcore prefetch requests that missed the LLC",
723 "Offcore": "1"
724 },
725 {
726 "EventCode": "0xB7",
727 "MSRValue": "0x4070",
728 "Counter": "2",
729 "UMask": "0x1",
730 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
731 "MSRIndex": "0x1A6",
732 "SampleAfterValue": "100000",
733 "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
734 "Offcore": "1"
735 },
736 {
737 "EventCode": "0xB7",
738 "MSRValue": "0x2070",
739 "Counter": "2",
740 "UMask": "0x1",
741 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
742 "MSRIndex": "0x1A6",
743 "SampleAfterValue": "100000",
744 "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
745 "Offcore": "1"
746 }
747] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/perf/pmu-events/arch/x86/westmereex/other.json
new file mode 100644
index 000000000000..85133d6a5ce0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json
@@ -0,0 +1,287 @@
1[
2 {
3 "EventCode": "0xE8",
4 "Counter": "0,1,2,3",
5 "UMask": "0x1",
6 "EventName": "BPU_CLEARS.EARLY",
7 "SampleAfterValue": "2000000",
8 "BriefDescription": "Early Branch Prediciton Unit clears"
9 },
10 {
11 "EventCode": "0xE8",
12 "Counter": "0,1,2,3",
13 "UMask": "0x2",
14 "EventName": "BPU_CLEARS.LATE",
15 "SampleAfterValue": "2000000",
16 "BriefDescription": "Late Branch Prediction Unit clears"
17 },
18 {
19 "EventCode": "0xE5",
20 "Counter": "0,1,2,3",
21 "UMask": "0x1",
22 "EventName": "BPU_MISSED_CALL_RET",
23 "SampleAfterValue": "2000000",
24 "BriefDescription": "Branch prediction unit missed call or return"
25 },
26 {
27 "EventCode": "0xD5",
28 "Counter": "0,1,2,3",
29 "UMask": "0x1",
30 "EventName": "ES_REG_RENAMES",
31 "SampleAfterValue": "2000000",
32 "BriefDescription": "ES segment renames"
33 },
34 {
35 "EventCode": "0x6C",
36 "Counter": "0,1,2,3",
37 "UMask": "0x1",
38 "EventName": "IO_TRANSACTIONS",
39 "SampleAfterValue": "2000000",
40 "BriefDescription": "I/O transactions"
41 },
42 {
43 "EventCode": "0x80",
44 "Counter": "0,1,2,3",
45 "UMask": "0x4",
46 "EventName": "L1I.CYCLES_STALLED",
47 "SampleAfterValue": "2000000",
48 "BriefDescription": "L1I instruction fetch stall cycles"
49 },
50 {
51 "EventCode": "0x80",
52 "Counter": "0,1,2,3",
53 "UMask": "0x1",
54 "EventName": "L1I.HITS",
55 "SampleAfterValue": "2000000",
56 "BriefDescription": "L1I instruction fetch hits"
57 },
58 {
59 "EventCode": "0x80",
60 "Counter": "0,1,2,3",
61 "UMask": "0x2",
62 "EventName": "L1I.MISSES",
63 "SampleAfterValue": "2000000",
64 "BriefDescription": "L1I instruction fetch misses"
65 },
66 {
67 "EventCode": "0x80",
68 "Counter": "0,1,2,3",
69 "UMask": "0x3",
70 "EventName": "L1I.READS",
71 "SampleAfterValue": "2000000",
72 "BriefDescription": "L1I Instruction fetches"
73 },
74 {
75 "EventCode": "0x82",
76 "Counter": "0,1,2,3",
77 "UMask": "0x1",
78 "EventName": "LARGE_ITLB.HIT",
79 "SampleAfterValue": "200000",
80 "BriefDescription": "Large ITLB hit"
81 },
82 {
83 "EventCode": "0x3",
84 "Counter": "0,1,2,3",
85 "UMask": "0x2",
86 "EventName": "LOAD_BLOCK.OVERLAP_STORE",
87 "SampleAfterValue": "200000",
88 "BriefDescription": "Loads that partially overlap an earlier store"
89 },
90 {
91 "EventCode": "0x13",
92 "Counter": "0,1,2,3",
93 "UMask": "0x7",
94 "EventName": "LOAD_DISPATCH.ANY",
95 "SampleAfterValue": "2000000",
96 "BriefDescription": "All loads dispatched"
97 },
98 {
99 "EventCode": "0x13",
100 "Counter": "0,1,2,3",
101 "UMask": "0x4",
102 "EventName": "LOAD_DISPATCH.MOB",
103 "SampleAfterValue": "2000000",
104 "BriefDescription": "Loads dispatched from the MOB"
105 },
106 {
107 "EventCode": "0x13",
108 "Counter": "0,1,2,3",
109 "UMask": "0x1",
110 "EventName": "LOAD_DISPATCH.RS",
111 "SampleAfterValue": "2000000",
112 "BriefDescription": "Loads dispatched that bypass the MOB"
113 },
114 {
115 "EventCode": "0x13",
116 "Counter": "0,1,2,3",
117 "UMask": "0x2",
118 "EventName": "LOAD_DISPATCH.RS_DELAYED",
119 "SampleAfterValue": "2000000",
120 "BriefDescription": "Loads dispatched from stage 305"
121 },
122 {
123 "EventCode": "0x7",
124 "Counter": "0,1,2,3",
125 "UMask": "0x1",
126 "EventName": "PARTIAL_ADDRESS_ALIAS",
127 "SampleAfterValue": "200000",
128 "BriefDescription": "False dependencies due to partial address aliasing"
129 },
130 {
131 "EventCode": "0xD2",
132 "Counter": "0,1,2,3",
133 "UMask": "0xf",
134 "EventName": "RAT_STALLS.ANY",
135 "SampleAfterValue": "2000000",
136 "BriefDescription": "All RAT stall cycles"
137 },
138 {
139 "EventCode": "0xD2",
140 "Counter": "0,1,2,3",
141 "UMask": "0x1",
142 "EventName": "RAT_STALLS.FLAGS",
143 "SampleAfterValue": "2000000",
144 "BriefDescription": "Flag stall cycles"
145 },
146 {
147 "EventCode": "0xD2",
148 "Counter": "0,1,2,3",
149 "UMask": "0x2",
150 "EventName": "RAT_STALLS.REGISTERS",
151 "SampleAfterValue": "2000000",
152 "BriefDescription": "Partial register stall cycles"
153 },
154 {
155 "EventCode": "0xD2",
156 "Counter": "0,1,2,3",
157 "UMask": "0x4",
158 "EventName": "RAT_STALLS.ROB_READ_PORT",
159 "SampleAfterValue": "2000000",
160 "BriefDescription": "ROB read port stalls cycles"
161 },
162 {
163 "EventCode": "0xD2",
164 "Counter": "0,1,2,3",
165 "UMask": "0x8",
166 "EventName": "RAT_STALLS.SCOREBOARD",
167 "SampleAfterValue": "2000000",
168 "BriefDescription": "Scoreboard stall cycles"
169 },
170 {
171 "EventCode": "0x4",
172 "Counter": "0,1,2,3",
173 "UMask": "0x7",
174 "EventName": "SB_DRAIN.ANY",
175 "SampleAfterValue": "200000",
176 "BriefDescription": "All Store buffer stall cycles"
177 },
178 {
179 "EventCode": "0xD4",
180 "Counter": "0,1,2,3",
181 "UMask": "0x1",
182 "EventName": "SEG_RENAME_STALLS",
183 "SampleAfterValue": "2000000",
184 "BriefDescription": "Segment rename stall cycles"
185 },
186 {
187 "EventCode": "0xB8",
188 "Counter": "0,1,2,3",
189 "UMask": "0x1",
190 "EventName": "SNOOP_RESPONSE.HIT",
191 "SampleAfterValue": "100000",
192 "BriefDescription": "Thread responded HIT to snoop"
193 },
194 {
195 "EventCode": "0xB8",
196 "Counter": "0,1,2,3",
197 "UMask": "0x2",
198 "EventName": "SNOOP_RESPONSE.HITE",
199 "SampleAfterValue": "100000",
200 "BriefDescription": "Thread responded HITE to snoop"
201 },
202 {
203 "EventCode": "0xB8",
204 "Counter": "0,1,2,3",
205 "UMask": "0x4",
206 "EventName": "SNOOP_RESPONSE.HITM",
207 "SampleAfterValue": "100000",
208 "BriefDescription": "Thread responded HITM to snoop"
209 },
210 {
211 "EventCode": "0xB4",
212 "Counter": "0,1,2,3",
213 "UMask": "0x4",
214 "EventName": "SNOOPQ_REQUESTS.CODE",
215 "SampleAfterValue": "100000",
216 "BriefDescription": "Snoop code requests"
217 },
218 {
219 "EventCode": "0xB4",
220 "Counter": "0,1,2,3",
221 "UMask": "0x1",
222 "EventName": "SNOOPQ_REQUESTS.DATA",
223 "SampleAfterValue": "100000",
224 "BriefDescription": "Snoop data requests"
225 },
226 {
227 "EventCode": "0xB4",
228 "Counter": "0,1,2,3",
229 "UMask": "0x2",
230 "EventName": "SNOOPQ_REQUESTS.INVALIDATE",
231 "SampleAfterValue": "100000",
232 "BriefDescription": "Snoop invalidate requests"
233 },
234 {
235 "EventCode": "0xB3",
236 "UMask": "0x4",
237 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
238 "SampleAfterValue": "2000000",
239 "BriefDescription": "Outstanding snoop code requests"
240 },
241 {
242 "EventCode": "0xB3",
243 "UMask": "0x4",
244 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
245 "SampleAfterValue": "2000000",
246 "BriefDescription": "Cycles snoop code requests queued",
247 "CounterMask": "1"
248 },
249 {
250 "EventCode": "0xB3",
251 "UMask": "0x1",
252 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
253 "SampleAfterValue": "2000000",
254 "BriefDescription": "Outstanding snoop data requests"
255 },
256 {
257 "EventCode": "0xB3",
258 "UMask": "0x1",
259 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
260 "SampleAfterValue": "2000000",
261 "BriefDescription": "Cycles snoop data requests queued",
262 "CounterMask": "1"
263 },
264 {
265 "EventCode": "0xB3",
266 "UMask": "0x2",
267 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
268 "SampleAfterValue": "2000000",
269 "BriefDescription": "Outstanding snoop invalidate requests"
270 },
271 {
272 "EventCode": "0xB3",
273 "UMask": "0x2",
274 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
275 "SampleAfterValue": "2000000",
276 "BriefDescription": "Cycles snoop invalidate requests queued",
277 "CounterMask": "1"
278 },
279 {
280 "EventCode": "0xF6",
281 "Counter": "0,1,2,3",
282 "UMask": "0x1",
283 "EventName": "SQ_FULL_STALL_CYCLES",
284 "SampleAfterValue": "2000000",
285 "BriefDescription": "Super Queue full stall cycles"
286 }
287] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
new file mode 100644
index 000000000000..799c57d94c39
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
@@ -0,0 +1,905 @@
1[
2 {
3 "EventCode": "0x14",
4 "Counter": "0,1,2,3",
5 "UMask": "0x1",
6 "EventName": "ARITH.CYCLES_DIV_BUSY",
7 "SampleAfterValue": "2000000",
8 "BriefDescription": "Cycles the divider is busy"
9 },
10 {
11 "EventCode": "0x14",
12 "Invert": "1",
13 "Counter": "0,1,2,3",
14 "UMask": "0x1",
15 "EventName": "ARITH.DIV",
16 "SampleAfterValue": "2000000",
17 "BriefDescription": "Divide Operations executed",
18 "CounterMask": "1",
19 "EdgeDetect": "1"
20 },
21 {
22 "EventCode": "0x14",
23 "Counter": "0,1,2,3",
24 "UMask": "0x2",
25 "EventName": "ARITH.MUL",
26 "SampleAfterValue": "2000000",
27 "BriefDescription": "Multiply operations executed"
28 },
29 {
30 "EventCode": "0xE6",
31 "Counter": "0,1,2,3",
32 "UMask": "0x2",
33 "EventName": "BACLEAR.BAD_TARGET",
34 "SampleAfterValue": "2000000",
35 "BriefDescription": "BACLEAR asserted with bad target address"
36 },
37 {
38 "EventCode": "0xE6",
39 "Counter": "0,1,2,3",
40 "UMask": "0x1",
41 "EventName": "BACLEAR.CLEAR",
42 "SampleAfterValue": "2000000",
43 "BriefDescription": "BACLEAR asserted, regardless of cause "
44 },
45 {
46 "EventCode": "0xA7",
47 "Counter": "0,1,2,3",
48 "UMask": "0x1",
49 "EventName": "BACLEAR_FORCE_IQ",
50 "SampleAfterValue": "2000000",
51 "BriefDescription": "Instruction queue forced BACLEAR"
52 },
53 {
54 "EventCode": "0xE0",
55 "Counter": "0,1,2,3",
56 "UMask": "0x1",
57 "EventName": "BR_INST_DECODED",
58 "SampleAfterValue": "2000000",
59 "BriefDescription": "Branch instructions decoded"
60 },
61 {
62 "EventCode": "0x88",
63 "Counter": "0,1,2,3",
64 "UMask": "0x7f",
65 "EventName": "BR_INST_EXEC.ANY",
66 "SampleAfterValue": "200000",
67 "BriefDescription": "Branch instructions executed"
68 },
69 {
70 "EventCode": "0x88",
71 "Counter": "0,1,2,3",
72 "UMask": "0x1",
73 "EventName": "BR_INST_EXEC.COND",
74 "SampleAfterValue": "200000",
75 "BriefDescription": "Conditional branch instructions executed"
76 },
77 {
78 "EventCode": "0x88",
79 "Counter": "0,1,2,3",
80 "UMask": "0x2",
81 "EventName": "BR_INST_EXEC.DIRECT",
82 "SampleAfterValue": "200000",
83 "BriefDescription": "Unconditional branches executed"
84 },
85 {
86 "EventCode": "0x88",
87 "Counter": "0,1,2,3",
88 "UMask": "0x10",
89 "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
90 "SampleAfterValue": "20000",
91 "BriefDescription": "Unconditional call branches executed"
92 },
93 {
94 "EventCode": "0x88",
95 "Counter": "0,1,2,3",
96 "UMask": "0x20",
97 "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
98 "SampleAfterValue": "20000",
99 "BriefDescription": "Indirect call branches executed"
100 },
101 {
102 "EventCode": "0x88",
103 "Counter": "0,1,2,3",
104 "UMask": "0x4",
105 "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
106 "SampleAfterValue": "20000",
107 "BriefDescription": "Indirect non call branches executed"
108 },
109 {
110 "EventCode": "0x88",
111 "Counter": "0,1,2,3",
112 "UMask": "0x30",
113 "EventName": "BR_INST_EXEC.NEAR_CALLS",
114 "SampleAfterValue": "20000",
115 "BriefDescription": "Call branches executed"
116 },
117 {
118 "EventCode": "0x88",
119 "Counter": "0,1,2,3",
120 "UMask": "0x7",
121 "EventName": "BR_INST_EXEC.NON_CALLS",
122 "SampleAfterValue": "200000",
123 "BriefDescription": "All non call branches executed"
124 },
125 {
126 "EventCode": "0x88",
127 "Counter": "0,1,2,3",
128 "UMask": "0x8",
129 "EventName": "BR_INST_EXEC.RETURN_NEAR",
130 "SampleAfterValue": "20000",
131 "BriefDescription": "Indirect return branches executed"
132 },
133 {
134 "EventCode": "0x88",
135 "Counter": "0,1,2,3",
136 "UMask": "0x40",
137 "EventName": "BR_INST_EXEC.TAKEN",
138 "SampleAfterValue": "200000",
139 "BriefDescription": "Taken branches executed"
140 },
141 {
142 "PEBS": "1",
143 "EventCode": "0xC4",
144 "Counter": "0,1,2,3",
145 "UMask": "0x4",
146 "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
147 "SampleAfterValue": "200000",
148 "BriefDescription": "Retired branch instructions (Precise Event)"
149 },
150 {
151 "PEBS": "1",
152 "EventCode": "0xC4",
153 "Counter": "0,1,2,3",
154 "UMask": "0x1",
155 "EventName": "BR_INST_RETIRED.CONDITIONAL",
156 "SampleAfterValue": "200000",
157 "BriefDescription": "Retired conditional branch instructions (Precise Event)"
158 },
159 {
160 "PEBS": "1",
161 "EventCode": "0xC4",
162 "Counter": "0,1,2,3",
163 "UMask": "0x2",
164 "EventName": "BR_INST_RETIRED.NEAR_CALL",
165 "SampleAfterValue": "20000",
166 "BriefDescription": "Retired near call instructions (Precise Event)"
167 },
168 {
169 "EventCode": "0x89",
170 "Counter": "0,1,2,3",
171 "UMask": "0x7f",
172 "EventName": "BR_MISP_EXEC.ANY",
173 "SampleAfterValue": "20000",
174 "BriefDescription": "Mispredicted branches executed"
175 },
176 {
177 "EventCode": "0x89",
178 "Counter": "0,1,2,3",
179 "UMask": "0x1",
180 "EventName": "BR_MISP_EXEC.COND",
181 "SampleAfterValue": "20000",
182 "BriefDescription": "Mispredicted conditional branches executed"
183 },
184 {
185 "EventCode": "0x89",
186 "Counter": "0,1,2,3",
187 "UMask": "0x2",
188 "EventName": "BR_MISP_EXEC.DIRECT",
189 "SampleAfterValue": "20000",
190 "BriefDescription": "Mispredicted unconditional branches executed"
191 },
192 {
193 "EventCode": "0x89",
194 "Counter": "0,1,2,3",
195 "UMask": "0x10",
196 "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
197 "SampleAfterValue": "2000",
198 "BriefDescription": "Mispredicted non call branches executed"
199 },
200 {
201 "EventCode": "0x89",
202 "Counter": "0,1,2,3",
203 "UMask": "0x20",
204 "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
205 "SampleAfterValue": "2000",
206 "BriefDescription": "Mispredicted indirect call branches executed"
207 },
208 {
209 "EventCode": "0x89",
210 "Counter": "0,1,2,3",
211 "UMask": "0x4",
212 "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
213 "SampleAfterValue": "2000",
214 "BriefDescription": "Mispredicted indirect non call branches executed"
215 },
216 {
217 "EventCode": "0x89",
218 "Counter": "0,1,2,3",
219 "UMask": "0x30",
220 "EventName": "BR_MISP_EXEC.NEAR_CALLS",
221 "SampleAfterValue": "2000",
222 "BriefDescription": "Mispredicted call branches executed"
223 },
224 {
225 "EventCode": "0x89",
226 "Counter": "0,1,2,3",
227 "UMask": "0x7",
228 "EventName": "BR_MISP_EXEC.NON_CALLS",
229 "SampleAfterValue": "20000",
230 "BriefDescription": "Mispredicted non call branches executed"
231 },
232 {
233 "EventCode": "0x89",
234 "Counter": "0,1,2,3",
235 "UMask": "0x8",
236 "EventName": "BR_MISP_EXEC.RETURN_NEAR",
237 "SampleAfterValue": "2000",
238 "BriefDescription": "Mispredicted return branches executed"
239 },
240 {
241 "EventCode": "0x89",
242 "Counter": "0,1,2,3",
243 "UMask": "0x40",
244 "EventName": "BR_MISP_EXEC.TAKEN",
245 "SampleAfterValue": "20000",
246 "BriefDescription": "Mispredicted taken branches executed"
247 },
248 {
249 "PEBS": "1",
250 "EventCode": "0xC5",
251 "Counter": "0,1,2,3",
252 "UMask": "0x4",
253 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
254 "SampleAfterValue": "20000",
255 "BriefDescription": "Mispredicted retired branch instructions (Precise Event)"
256 },
257 {
258 "PEBS": "1",
259 "EventCode": "0xC5",
260 "Counter": "0,1,2,3",
261 "UMask": "0x1",
262 "EventName": "BR_MISP_RETIRED.CONDITIONAL",
263 "SampleAfterValue": "20000",
264 "BriefDescription": "Mispredicted conditional retired branches (Precise Event)"
265 },
266 {
267 "PEBS": "1",
268 "EventCode": "0xC5",
269 "Counter": "0,1,2,3",
270 "UMask": "0x2",
271 "EventName": "BR_MISP_RETIRED.NEAR_CALL",
272 "SampleAfterValue": "2000",
273 "BriefDescription": "Mispredicted near retired calls (Precise Event)"
274 },
275 {
276 "EventCode": "0x0",
277 "Counter": "Fixed counter 3",
278 "UMask": "0x0",
279 "EventName": "CPU_CLK_UNHALTED.REF",
280 "SampleAfterValue": "2000000",
281 "BriefDescription": "Reference cycles when thread is not halted (fixed counter)"
282 },
283 {
284 "EventCode": "0x3C",
285 "Counter": "0,1,2,3",
286 "UMask": "0x1",
287 "EventName": "CPU_CLK_UNHALTED.REF_P",
288 "SampleAfterValue": "100000",
289 "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)"
290 },
291 {
292 "EventCode": "0x0",
293 "Counter": "Fixed counter 2",
294 "UMask": "0x0",
295 "EventName": "CPU_CLK_UNHALTED.THREAD",
296 "SampleAfterValue": "2000000",
297 "BriefDescription": "Cycles when thread is not halted (fixed counter)"
298 },
299 {
300 "EventCode": "0x3C",
301 "Counter": "0,1,2,3",
302 "UMask": "0x0",
303 "EventName": "CPU_CLK_UNHALTED.THREAD_P",
304 "SampleAfterValue": "2000000",
305 "BriefDescription": "Cycles when thread is not halted (programmable counter)"
306 },
307 {
308 "EventCode": "0x3C",
309 "Invert": "1",
310 "Counter": "0,1,2,3",
311 "UMask": "0x0",
312 "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
313 "SampleAfterValue": "2000000",
314 "BriefDescription": "Total CPU cycles",
315 "CounterMask": "2"
316 },
317 {
318 "EventCode": "0x87",
319 "Counter": "0,1,2,3",
320 "UMask": "0xf",
321 "EventName": "ILD_STALL.ANY",
322 "SampleAfterValue": "2000000",
323 "BriefDescription": "Any Instruction Length Decoder stall cycles"
324 },
325 {
326 "EventCode": "0x87",
327 "Counter": "0,1,2,3",
328 "UMask": "0x4",
329 "EventName": "ILD_STALL.IQ_FULL",
330 "SampleAfterValue": "2000000",
331 "BriefDescription": "Instruction Queue full stall cycles"
332 },
333 {
334 "EventCode": "0x87",
335 "Counter": "0,1,2,3",
336 "UMask": "0x1",
337 "EventName": "ILD_STALL.LCP",
338 "SampleAfterValue": "2000000",
339 "BriefDescription": "Length Change Prefix stall cycles"
340 },
341 {
342 "EventCode": "0x87",
343 "Counter": "0,1,2,3",
344 "UMask": "0x2",
345 "EventName": "ILD_STALL.MRU",
346 "SampleAfterValue": "2000000",
347 "BriefDescription": "Stall cycles due to BPU MRU bypass"
348 },
349 {
350 "EventCode": "0x87",
351 "Counter": "0,1,2,3",
352 "UMask": "0x8",
353 "EventName": "ILD_STALL.REGEN",
354 "SampleAfterValue": "2000000",
355 "BriefDescription": "Regen stall cycles"
356 },
357 {
358 "EventCode": "0x18",
359 "Counter": "0,1,2,3",
360 "UMask": "0x1",
361 "EventName": "INST_DECODED.DEC0",
362 "SampleAfterValue": "2000000",
363 "BriefDescription": "Instructions that must be decoded by decoder 0"
364 },
365 {
366 "EventCode": "0x1E",
367 "Counter": "0,1,2,3",
368 "UMask": "0x1",
369 "EventName": "INST_QUEUE_WRITE_CYCLES",
370 "SampleAfterValue": "2000000",
371 "BriefDescription": "Cycles instructions are written to the instruction queue"
372 },
373 {
374 "EventCode": "0x17",
375 "Counter": "0,1,2,3",
376 "UMask": "0x1",
377 "EventName": "INST_QUEUE_WRITES",
378 "SampleAfterValue": "2000000",
379 "BriefDescription": "Instructions written to instruction queue."
380 },
381 {
382 "EventCode": "0x0",
383 "Counter": "Fixed counter 1",
384 "UMask": "0x0",
385 "EventName": "INST_RETIRED.ANY",
386 "SampleAfterValue": "2000000",
387 "BriefDescription": "Instructions retired (fixed counter)"
388 },
389 {
390 "PEBS": "1",
391 "EventCode": "0xC0",
392 "Counter": "0,1,2,3",
393 "UMask": "0x1",
394 "EventName": "INST_RETIRED.ANY_P",
395 "SampleAfterValue": "2000000",
396 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)"
397 },
398 {
399 "PEBS": "1",
400 "EventCode": "0xC0",
401 "Counter": "0,1,2,3",
402 "UMask": "0x4",
403 "EventName": "INST_RETIRED.MMX",
404 "SampleAfterValue": "2000000",
405 "BriefDescription": "Retired MMX instructions (Precise Event)"
406 },
407 {
408 "PEBS": "1",
409 "EventCode": "0xC0",
410 "Invert": "1",
411 "Counter": "0,1,2,3",
412 "UMask": "0x1",
413 "EventName": "INST_RETIRED.TOTAL_CYCLES",
414 "SampleAfterValue": "2000000",
415 "BriefDescription": "Total cycles (Precise Event)",
416 "CounterMask": "16"
417 },
418 {
419 "PEBS": "1",
420 "EventCode": "0xC0",
421 "Counter": "0,1,2,3",
422 "UMask": "0x2",
423 "EventName": "INST_RETIRED.X87",
424 "SampleAfterValue": "2000000",
425 "BriefDescription": "Retired floating-point operations (Precise Event)"
426 },
427 {
428 "EventCode": "0x4C",
429 "Counter": "0,1",
430 "UMask": "0x1",
431 "EventName": "LOAD_HIT_PRE",
432 "SampleAfterValue": "200000",
433 "BriefDescription": "Load operations conflicting with software prefetches"
434 },
435 {
436 "EventCode": "0xA8",
437 "Counter": "0,1,2,3",
438 "UMask": "0x1",
439 "EventName": "LSD.ACTIVE",
440 "SampleAfterValue": "2000000",
441 "BriefDescription": "Cycles when uops were delivered by the LSD",
442 "CounterMask": "1"
443 },
444 {
445 "EventCode": "0xA8",
446 "Invert": "1",
447 "Counter": "0,1,2,3",
448 "UMask": "0x1",
449 "EventName": "LSD.INACTIVE",
450 "SampleAfterValue": "2000000",
451 "BriefDescription": "Cycles no uops were delivered by the LSD",
452 "CounterMask": "1"
453 },
454 {
455 "EventCode": "0x20",
456 "Counter": "0,1,2,3",
457 "UMask": "0x1",
458 "EventName": "LSD_OVERFLOW",
459 "SampleAfterValue": "2000000",
460 "BriefDescription": "Loops that can't stream from the instruction queue"
461 },
462 {
463 "EventCode": "0xC3",
464 "Counter": "0,1,2,3",
465 "UMask": "0x1",
466 "EventName": "MACHINE_CLEARS.CYCLES",
467 "SampleAfterValue": "20000",
468 "BriefDescription": "Cycles machine clear asserted"
469 },
470 {
471 "EventCode": "0xC3",
472 "Counter": "0,1,2,3",
473 "UMask": "0x2",
474 "EventName": "MACHINE_CLEARS.MEM_ORDER",
475 "SampleAfterValue": "20000",
476 "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts"
477 },
478 {
479 "EventCode": "0xC3",
480 "Counter": "0,1,2,3",
481 "UMask": "0x4",
482 "EventName": "MACHINE_CLEARS.SMC",
483 "SampleAfterValue": "20000",
484 "BriefDescription": "Self-Modifying Code detected"
485 },
486 {
487 "EventCode": "0xA2",
488 "Counter": "0,1,2,3",
489 "UMask": "0x1",
490 "EventName": "RESOURCE_STALLS.ANY",
491 "SampleAfterValue": "2000000",
492 "BriefDescription": "Resource related stall cycles"
493 },
494 {
495 "EventCode": "0xA2",
496 "Counter": "0,1,2,3",
497 "UMask": "0x20",
498 "EventName": "RESOURCE_STALLS.FPCW",
499 "SampleAfterValue": "2000000",
500 "BriefDescription": "FPU control word write stall cycles"
501 },
502 {
503 "EventCode": "0xA2",
504 "Counter": "0,1,2,3",
505 "UMask": "0x2",
506 "EventName": "RESOURCE_STALLS.LOAD",
507 "SampleAfterValue": "2000000",
508 "BriefDescription": "Load buffer stall cycles"
509 },
510 {
511 "EventCode": "0xA2",
512 "Counter": "0,1,2,3",
513 "UMask": "0x40",
514 "EventName": "RESOURCE_STALLS.MXCSR",
515 "SampleAfterValue": "2000000",
516 "BriefDescription": "MXCSR rename stall cycles"
517 },
518 {
519 "EventCode": "0xA2",
520 "Counter": "0,1,2,3",
521 "UMask": "0x80",
522 "EventName": "RESOURCE_STALLS.OTHER",
523 "SampleAfterValue": "2000000",
524 "BriefDescription": "Other Resource related stall cycles"
525 },
526 {
527 "EventCode": "0xA2",
528 "Counter": "0,1,2,3",
529 "UMask": "0x10",
530 "EventName": "RESOURCE_STALLS.ROB_FULL",
531 "SampleAfterValue": "2000000",
532 "BriefDescription": "ROB full stall cycles"
533 },
534 {
535 "EventCode": "0xA2",
536 "Counter": "0,1,2,3",
537 "UMask": "0x4",
538 "EventName": "RESOURCE_STALLS.RS_FULL",
539 "SampleAfterValue": "2000000",
540 "BriefDescription": "Reservation Station full stall cycles"
541 },
542 {
543 "EventCode": "0xA2",
544 "Counter": "0,1,2,3",
545 "UMask": "0x8",
546 "EventName": "RESOURCE_STALLS.STORE",
547 "SampleAfterValue": "2000000",
548 "BriefDescription": "Store buffer stall cycles"
549 },
550 {
551 "PEBS": "1",
552 "EventCode": "0xC7",
553 "Counter": "0,1,2,3",
554 "UMask": "0x4",
555 "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
556 "SampleAfterValue": "200000",
557 "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)"
558 },
559 {
560 "PEBS": "1",
561 "EventCode": "0xC7",
562 "Counter": "0,1,2,3",
563 "UMask": "0x1",
564 "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
565 "SampleAfterValue": "200000",
566 "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)"
567 },
568 {
569 "PEBS": "1",
570 "EventCode": "0xC7",
571 "Counter": "0,1,2,3",
572 "UMask": "0x8",
573 "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
574 "SampleAfterValue": "200000",
575 "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)"
576 },
577 {
578 "PEBS": "1",
579 "EventCode": "0xC7",
580 "Counter": "0,1,2,3",
581 "UMask": "0x2",
582 "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
583 "SampleAfterValue": "200000",
584 "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)"
585 },
586 {
587 "PEBS": "1",
588 "EventCode": "0xC7",
589 "Counter": "0,1,2,3",
590 "UMask": "0x10",
591 "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
592 "SampleAfterValue": "200000",
593 "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)"
594 },
595 {
596 "EventCode": "0x3C",
597 "Counter": "0,1,2,3",
598 "UMask": "0x0",
599 "EventName": "CPU_CLK_UNHALTED.THREAD_P",
600 "SampleAfterValue": "2000000",
601 "BriefDescription": "Cycles thread is active"
602 },
603 {
604 "EventCode": "0xDB",
605 "Counter": "0,1,2,3",
606 "UMask": "0x1",
607 "EventName": "UOP_UNFUSION",
608 "SampleAfterValue": "2000000",
609 "BriefDescription": "Uop unfusions due to FP exceptions"
610 },
611 {
612 "EventCode": "0xD1",
613 "Counter": "0,1,2,3",
614 "UMask": "0x4",
615 "EventName": "UOPS_DECODED.ESP_FOLDING",
616 "SampleAfterValue": "2000000",
617 "BriefDescription": "Stack pointer instructions decoded"
618 },
619 {
620 "EventCode": "0xD1",
621 "Counter": "0,1,2,3",
622 "UMask": "0x8",
623 "EventName": "UOPS_DECODED.ESP_SYNC",
624 "SampleAfterValue": "2000000",
625 "BriefDescription": "Stack pointer sync operations"
626 },
627 {
628 "EventCode": "0xD1",
629 "Counter": "0,1,2,3",
630 "UMask": "0x2",
631 "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
632 "SampleAfterValue": "2000000",
633 "BriefDescription": "Uops decoded by Microcode Sequencer",
634 "CounterMask": "1"
635 },
636 {
637 "EventCode": "0xD1",
638 "Invert": "1",
639 "Counter": "0,1,2,3",
640 "UMask": "0x1",
641 "EventName": "UOPS_DECODED.STALL_CYCLES",
642 "SampleAfterValue": "2000000",
643 "BriefDescription": "Cycles no Uops are decoded",
644 "CounterMask": "1"
645 },
646 {
647 "EventCode": "0xB1",
648 "Counter": "0,1,2,3",
649 "UMask": "0x3f",
650 "AnyThread": "1",
651 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
652 "SampleAfterValue": "2000000",
653 "BriefDescription": "Cycles Uops executed on any port (core count)",
654 "CounterMask": "1"
655 },
656 {
657 "EventCode": "0xB1",
658 "Counter": "0,1,2,3",
659 "UMask": "0x1f",
660 "AnyThread": "1",
661 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
662 "SampleAfterValue": "2000000",
663 "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
664 "CounterMask": "1"
665 },
666 {
667 "EventCode": "0xB1",
668 "Invert": "1",
669 "Counter": "0,1,2,3",
670 "UMask": "0x3f",
671 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
672 "SampleAfterValue": "2000000",
673 "BriefDescription": "Uops executed on any port (core count)",
674 "CounterMask": "1",
675 "EdgeDetect": "1"
676 },
677 {
678 "EventCode": "0xB1",
679 "Invert": "1",
680 "Counter": "0,1,2,3",
681 "UMask": "0x1f",
682 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
683 "SampleAfterValue": "2000000",
684 "BriefDescription": "Uops executed on ports 0-4 (core count)",
685 "CounterMask": "1",
686 "EdgeDetect": "1"
687 },
688 {
689 "EventCode": "0xB1",
690 "Invert": "1",
691 "Counter": "0,1,2,3",
692 "UMask": "0x3f",
693 "AnyThread": "1",
694 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
695 "SampleAfterValue": "2000000",
696 "BriefDescription": "Cycles no Uops issued on any port (core count)",
697 "CounterMask": "1"
698 },
699 {
700 "EventCode": "0xB1",
701 "Invert": "1",
702 "Counter": "0,1,2,3",
703 "UMask": "0x1f",
704 "AnyThread": "1",
705 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
706 "SampleAfterValue": "2000000",
707 "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
708 "CounterMask": "1"
709 },
710 {
711 "EventCode": "0xB1",
712 "Counter": "0,1,2,3",
713 "UMask": "0x1",
714 "EventName": "UOPS_EXECUTED.PORT0",
715 "SampleAfterValue": "2000000",
716 "BriefDescription": "Uops executed on port 0"
717 },
718 {
719 "EventCode": "0xB1",
720 "Counter": "0,1,2,3",
721 "UMask": "0x40",
722 "EventName": "UOPS_EXECUTED.PORT015",
723 "SampleAfterValue": "2000000",
724 "BriefDescription": "Uops issued on ports 0, 1 or 5"
725 },
726 {
727 "EventCode": "0xB1",
728 "Invert": "1",
729 "Counter": "0,1,2,3",
730 "UMask": "0x40",
731 "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
732 "SampleAfterValue": "2000000",
733 "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
734 "CounterMask": "1"
735 },
736 {
737 "EventCode": "0xB1",
738 "Counter": "0,1,2,3",
739 "UMask": "0x2",
740 "EventName": "UOPS_EXECUTED.PORT1",
741 "SampleAfterValue": "2000000",
742 "BriefDescription": "Uops executed on port 1"
743 },
744 {
745 "EventCode": "0xB1",
746 "Counter": "0,1,2,3",
747 "UMask": "0x4",
748 "AnyThread": "1",
749 "EventName": "UOPS_EXECUTED.PORT2_CORE",
750 "SampleAfterValue": "2000000",
751 "BriefDescription": "Uops executed on port 2 (core count)"
752 },
753 {
754 "EventCode": "0xB1",
755 "Counter": "0,1,2,3",
756 "UMask": "0x80",
757 "AnyThread": "1",
758 "EventName": "UOPS_EXECUTED.PORT234_CORE",
759 "SampleAfterValue": "2000000",
760 "BriefDescription": "Uops issued on ports 2, 3 or 4"
761 },
762 {
763 "EventCode": "0xB1",
764 "Counter": "0,1,2,3",
765 "UMask": "0x8",
766 "AnyThread": "1",
767 "EventName": "UOPS_EXECUTED.PORT3_CORE",
768 "SampleAfterValue": "2000000",
769 "BriefDescription": "Uops executed on port 3 (core count)"
770 },
771 {
772 "EventCode": "0xB1",
773 "Counter": "0,1,2,3",
774 "UMask": "0x10",
775 "AnyThread": "1",
776 "EventName": "UOPS_EXECUTED.PORT4_CORE",
777 "SampleAfterValue": "2000000",
778 "BriefDescription": "Uops executed on port 4 (core count)"
779 },
780 {
781 "EventCode": "0xB1",
782 "Counter": "0,1,2,3",
783 "UMask": "0x20",
784 "EventName": "UOPS_EXECUTED.PORT5",
785 "SampleAfterValue": "2000000",
786 "BriefDescription": "Uops executed on port 5"
787 },
788 {
789 "EventCode": "0xE",
790 "Counter": "0,1,2,3",
791 "UMask": "0x1",
792 "EventName": "UOPS_ISSUED.ANY",
793 "SampleAfterValue": "2000000",
794 "BriefDescription": "Uops issued"
795 },
796 {
797 "EventCode": "0xE",
798 "Invert": "1",
799 "Counter": "0,1,2,3",
800 "UMask": "0x1",
801 "AnyThread": "1",
802 "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
803 "SampleAfterValue": "2000000",
804 "BriefDescription": "Cycles no Uops were issued on any thread",
805 "CounterMask": "1"
806 },
807 {
808 "EventCode": "0xE",
809 "Counter": "0,1,2,3",
810 "UMask": "0x1",
811 "AnyThread": "1",
812 "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
813 "SampleAfterValue": "2000000",
814 "BriefDescription": "Cycles Uops were issued on either thread",
815 "CounterMask": "1"
816 },
817 {
818 "EventCode": "0xE",
819 "Counter": "0,1,2,3",
820 "UMask": "0x2",
821 "EventName": "UOPS_ISSUED.FUSED",
822 "SampleAfterValue": "2000000",
823 "BriefDescription": "Fused Uops issued"
824 },
825 {
826 "EventCode": "0xE",
827 "Invert": "1",
828 "Counter": "0,1,2,3",
829 "UMask": "0x1",
830 "EventName": "UOPS_ISSUED.STALL_CYCLES",
831 "SampleAfterValue": "2000000",
832 "BriefDescription": "Cycles no Uops were issued",
833 "CounterMask": "1"
834 },
835 {
836 "PEBS": "1",
837 "EventCode": "0xC2",
838 "Counter": "0,1,2,3",
839 "UMask": "0x1",
840 "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
841 "SampleAfterValue": "2000000",
842 "BriefDescription": "Cycles Uops are being retired",
843 "CounterMask": "1"
844 },
845 {
846 "PEBS": "1",
847 "EventCode": "0xC2",
848 "Counter": "0,1,2,3",
849 "UMask": "0x1",
850 "EventName": "UOPS_RETIRED.ANY",
851 "SampleAfterValue": "2000000",
852 "BriefDescription": "Uops retired (Precise Event)"
853 },
854 {
855 "PEBS": "1",
856 "EventCode": "0xC2",
857 "Counter": "0,1,2,3",
858 "UMask": "0x4",
859 "EventName": "UOPS_RETIRED.MACRO_FUSED",
860 "SampleAfterValue": "2000000",
861 "BriefDescription": "Macro-fused Uops retired (Precise Event)"
862 },
863 {
864 "PEBS": "1",
865 "EventCode": "0xC2",
866 "Counter": "0,1,2,3",
867 "UMask": "0x2",
868 "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
869 "SampleAfterValue": "2000000",
870 "BriefDescription": "Retirement slots used (Precise Event)"
871 },
872 {
873 "PEBS": "1",
874 "EventCode": "0xC2",
875 "Invert": "1",
876 "Counter": "0,1,2,3",
877 "UMask": "0x1",
878 "EventName": "UOPS_RETIRED.STALL_CYCLES",
879 "SampleAfterValue": "2000000",
880 "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
881 "CounterMask": "1"
882 },
883 {
884 "PEBS": "1",
885 "EventCode": "0xC2",
886 "Invert": "1",
887 "Counter": "0,1,2,3",
888 "UMask": "0x1",
889 "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
890 "SampleAfterValue": "2000000",
891 "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
892 "CounterMask": "16"
893 },
894 {
895 "PEBS": "2",
896 "EventCode": "0xC0",
897 "Invert": "1",
898 "Counter": "0,1,2,3",
899 "UMask": "0x1",
900 "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
901 "SampleAfterValue": "2000000",
902 "BriefDescription": "Total cycles (Precise Event)",
903 "CounterMask": "16"
904 }
905] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
new file mode 100644
index 000000000000..ad989207e8f8
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
@@ -0,0 +1,173 @@
1[
2 {
3 "EventCode": "0x8",
4 "Counter": "0,1,2,3",
5 "UMask": "0x1",
6 "EventName": "DTLB_LOAD_MISSES.ANY",
7 "SampleAfterValue": "200000",
8 "BriefDescription": "DTLB load misses"
9 },
10 {
11 "EventCode": "0x8",
12 "Counter": "0,1,2,3",
13 "UMask": "0x80",
14 "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
15 "SampleAfterValue": "200000",
16 "BriefDescription": "DTLB load miss large page walks"
17 },
18 {
19 "EventCode": "0x8",
20 "Counter": "0,1,2,3",
21 "UMask": "0x20",
22 "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
23 "SampleAfterValue": "200000",
24 "BriefDescription": "DTLB load miss caused by low part of address"
25 },
26 {
27 "EventCode": "0x8",
28 "Counter": "0,1,2,3",
29 "UMask": "0x10",
30 "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
31 "SampleAfterValue": "2000000",
32 "BriefDescription": "DTLB second level hit"
33 },
34 {
35 "EventCode": "0x8",
36 "Counter": "0,1,2,3",
37 "UMask": "0x2",
38 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
39 "SampleAfterValue": "200000",
40 "BriefDescription": "DTLB load miss page walks complete"
41 },
42 {
43 "EventCode": "0x8",
44 "Counter": "0,1,2,3",
45 "UMask": "0x4",
46 "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
47 "SampleAfterValue": "200000",
48 "BriefDescription": "DTLB load miss page walk cycles"
49 },
50 {
51 "EventCode": "0x49",
52 "Counter": "0,1,2,3",
53 "UMask": "0x1",
54 "EventName": "DTLB_MISSES.ANY",
55 "SampleAfterValue": "200000",
56 "BriefDescription": "DTLB misses"
57 },
58 {
59 "EventCode": "0x49",
60 "Counter": "0,1,2,3",
61 "UMask": "0x80",
62 "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
63 "SampleAfterValue": "200000",
64 "BriefDescription": "DTLB miss large page walks"
65 },
66 {
67 "EventCode": "0x49",
68 "Counter": "0,1,2,3",
69 "UMask": "0x20",
70 "EventName": "DTLB_MISSES.PDE_MISS",
71 "SampleAfterValue": "200000",
72 "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE."
73 },
74 {
75 "EventCode": "0x49",
76 "Counter": "0,1,2,3",
77 "UMask": "0x10",
78 "EventName": "DTLB_MISSES.STLB_HIT",
79 "SampleAfterValue": "200000",
80 "BriefDescription": "DTLB first level misses but second level hit"
81 },
82 {
83 "EventCode": "0x49",
84 "Counter": "0,1,2,3",
85 "UMask": "0x2",
86 "EventName": "DTLB_MISSES.WALK_COMPLETED",
87 "SampleAfterValue": "200000",
88 "BriefDescription": "DTLB miss page walks"
89 },
90 {
91 "EventCode": "0x49",
92 "Counter": "0,1,2,3",
93 "UMask": "0x4",
94 "EventName": "DTLB_MISSES.WALK_CYCLES",
95 "SampleAfterValue": "2000000",
96 "BriefDescription": "DTLB miss page walk cycles"
97 },
98 {
99 "EventCode": "0x4F",
100 "Counter": "0,1,2,3",
101 "UMask": "0x10",
102 "EventName": "EPT.WALK_CYCLES",
103 "SampleAfterValue": "2000000",
104 "BriefDescription": "Extended Page Table walk cycles"
105 },
106 {
107 "EventCode": "0xAE",
108 "Counter": "0,1,2,3",
109 "UMask": "0x1",
110 "EventName": "ITLB_FLUSH",
111 "SampleAfterValue": "2000000",
112 "BriefDescription": "ITLB flushes"
113 },
114 {
115 "PEBS": "1",
116 "EventCode": "0xC8",
117 "Counter": "0,1,2,3",
118 "UMask": "0x20",
119 "EventName": "ITLB_MISS_RETIRED",
120 "SampleAfterValue": "200000",
121 "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
122 },
123 {
124 "EventCode": "0x85",
125 "Counter": "0,1,2,3",
126 "UMask": "0x1",
127 "EventName": "ITLB_MISSES.ANY",
128 "SampleAfterValue": "200000",
129 "BriefDescription": "ITLB miss"
130 },
131 {
132 "EventCode": "0x85",
133 "Counter": "0,1,2,3",
134 "UMask": "0x80",
135 "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
136 "SampleAfterValue": "200000",
137 "BriefDescription": "ITLB miss large page walks"
138 },
139 {
140 "EventCode": "0x85",
141 "Counter": "0,1,2,3",
142 "UMask": "0x2",
143 "EventName": "ITLB_MISSES.WALK_COMPLETED",
144 "SampleAfterValue": "200000",
145 "BriefDescription": "ITLB miss page walks"
146 },
147 {
148 "EventCode": "0x85",
149 "Counter": "0,1,2,3",
150 "UMask": "0x4",
151 "EventName": "ITLB_MISSES.WALK_CYCLES",
152 "SampleAfterValue": "2000000",
153 "BriefDescription": "ITLB miss page walk cycles"
154 },
155 {
156 "PEBS": "1",
157 "EventCode": "0xCB",
158 "Counter": "0,1,2,3",
159 "UMask": "0x80",
160 "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
161 "SampleAfterValue": "200000",
162 "BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
163 },
164 {
165 "PEBS": "1",
166 "EventCode": "0xC",
167 "Counter": "0,1,2,3",
168 "UMask": "0x1",
169 "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
170 "SampleAfterValue": "200000",
171 "BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
172 }
173] \ No newline at end of file
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 00:28:31 -0400