diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-05-03 03:37:08 -0400 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-06-06 05:58:23 -0400 |
| commit | 1faf8692bdc2da1e12c7f2ecda3a9e629ac9b05b (patch) | |
| tree | f0baeb075c90a68398eb7367133e0943b81d7297 | |
| parent | 1a695a905c18548062509178b98bc91e67510864 (diff) | |
clk: renesas: cpg-mssr: Document r8a7796 support
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index fefb8023020f..394d725ac7e0 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | |||
| @@ -13,7 +13,8 @@ They provide the following functionalities: | |||
| 13 | 13 | ||
| 14 | Required Properties: | 14 | Required Properties: |
| 15 | - compatible: Must be one of: | 15 | - compatible: Must be one of: |
| 16 | - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC | 16 | - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) |
| 17 | - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) | ||
| 17 | 18 | ||
| 18 | - reg: Base address and length of the memory resource used by the CPG/MSSR | 19 | - reg: Base address and length of the memory resource used by the CPG/MSSR |
| 19 | block | 20 | block |
| @@ -21,8 +22,8 @@ Required Properties: | |||
| 21 | - clocks: References to external parent clocks, one entry for each entry in | 22 | - clocks: References to external parent clocks, one entry for each entry in |
| 22 | clock-names | 23 | clock-names |
| 23 | - clock-names: List of external parent clock names. Valid names are: | 24 | - clock-names: List of external parent clock names. Valid names are: |
| 24 | - "extal" (r8a7795) | 25 | - "extal" (r8a7795, r8a7796) |
| 25 | - "extalr" (r8a7795) | 26 | - "extalr" (r8a7795, r8a7796) |
| 26 | 27 | ||
| 27 | - #clock-cells: Must be 2 | 28 | - #clock-cells: Must be 2 |
| 28 | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" | 29 | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" |