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authorChunfeng Yun <chunfeng.yun@mediatek.com>2018-11-28 21:34:36 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-12-05 04:14:06 -0500
commit1fab219e65c45cf6e294c757b10e514a15f55f8d (patch)
tree2bd84f7c79657ac3802c59b835802c7d073c969b
parent94552090cd188751afdc58a311aa2f3456f5fac0 (diff)
usb: mtu3: clear SOFTCONN when clear USB3_EN if work as HS mode
When the controller supports SS mode, but works as HS mode, the SOFTCONN will not be cleared automatically when clear USB3_EN by default, this cause an issue that can't disconnect from host, so clear SOFTCONN when clear USB3_EN when the class driver want to disable the D+ pullup. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/usb/mtu3/mtu3_core.c2
-rw-r--r--drivers/usb/mtu3/mtu3_hw_regs.h5
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c
index b6b20949d63a..4fee200795a5 100644
--- a/drivers/usb/mtu3/mtu3_core.c
+++ b/drivers/usb/mtu3/mtu3_core.c
@@ -586,6 +586,8 @@ static void mtu3_regs_init(struct mtu3 *mtu)
586 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN); 586 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
587 /* automatically build U2 link when U3 detect fail */ 587 /* automatically build U2 link when U3 detect fail */
588 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH); 588 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
589 /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
590 mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
589 } 591 }
590 592
591 mtu3_set_speed(mtu); 593 mtu3_set_speed(mtu);
diff --git a/drivers/usb/mtu3/mtu3_hw_regs.h b/drivers/usb/mtu3/mtu3_hw_regs.h
index d11fcd64c19d..1d65b7476f23 100644
--- a/drivers/usb/mtu3/mtu3_hw_regs.h
+++ b/drivers/usb/mtu3/mtu3_hw_regs.h
@@ -268,6 +268,8 @@
268#define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C) 268#define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C)
269#define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140) 269#define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140)
270 270
271#define U3D_U3U2_SWITCH_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0170)
272
271/*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/ 273/*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/
272 274
273/* U3D_LTSSM_CTRL */ 275/* U3D_LTSSM_CTRL */
@@ -302,6 +304,9 @@
302#define SS_DISABLE_INTR BIT(1) 304#define SS_DISABLE_INTR BIT(1)
303#define SS_INACTIVE_INTR BIT(0) 305#define SS_INACTIVE_INTR BIT(0)
304 306
307/* U3D_U3U2_SWITCH_CTRL */
308#define SOFTCON_CLR_AUTO_EN BIT(0)
309
305/*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/ 310/*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/
306 311
307#define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C) 312#define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)