drm/i915/icl: start adding the TBT pll

This commit just adds the register addresses and the basic skeleton of
the code. The next commits will expand on more specific functions.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-15-paulo.r.zanoni@intel.com

4 files changed, 47 insertions, 9 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 140f6a27d696..dd6076188319 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8836,6 +8836,10 @@ enum skl_power_gate {
 #define DDI_CLK_SEL(port)               PORT_CLK_SEL(port)
 #define  DDI_CLK_SEL_NONE               (0x0 << 28)
 #define  DDI_CLK_SEL_MG                 (0x8 << 28)
+#define  DDI_CLK_SEL_TBT_162            (0xC << 28)
+#define  DDI_CLK_SEL_TBT_270            (0xD << 28)
+#define  DDI_CLK_SEL_TBT_540            (0xE << 28)
+#define  DDI_CLK_SEL_TBT_810            (0xF << 28)
 #define  DDI_CLK_SEL_MASK               (0xF << 28)
 
 /* Transcoder clock selection */
@@ -8985,6 +8989,8 @@ enum skl_power_gate {
 #define  PLL_POWER_STATE        (1 << 26)
 #define CNL_DPLL_ENABLE(pll)    _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
 
+#define TBT_PLL_ENABLE          _MMIO(0x46020)
+
 #define _MG_PLL1_ENABLE         0x46030
 #define _MG_PLL2_ENABLE         0x46034
 #define _MG_PLL3_ENABLE         0x46038
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 936ff5a0b522..ce153b11c765 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1062,6 +1062,8 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
                                        const struct intel_shared_dpll *pll)
 {
+        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+        int clock = crtc->config->port_clock;
         const enum intel_dpll_id id = pll->info->id;
 
         switch (id) {
@@ -1070,6 +1072,20 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
         case DPLL_ID_ICL_DPLL0:
         case DPLL_ID_ICL_DPLL1:
                 return DDI_CLK_SEL_NONE;
+        case DPLL_ID_ICL_TBTPLL:
+                switch (clock) {
+                case 162000:
+                        return DDI_CLK_SEL_TBT_162;
+                case 270000:
+                        return DDI_CLK_SEL_TBT_270;
+                case 540000:
+                        return DDI_CLK_SEL_TBT_540;
+                case 810000:
+                        return DDI_CLK_SEL_TBT_810;
+                default:
+                        MISSING_CASE(clock);
+                        break;
+                }
         case DPLL_ID_ICL_MGPLL1:
         case DPLL_ID_ICL_MGPLL2:
         case DPLL_ID_ICL_MGPLL3:
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 07bdbf2582ba..132fe63e042a 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2857,10 +2857,17 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
         case PORT_D:
         case PORT_E:
         case PORT_F:
-                min = icl_port_to_mg_pll_id(port);
-                max = min;
-                ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
-                                            &pll_state);
+                if (0 /* TODO: TBT PLLs */) {
+                        min = DPLL_ID_ICL_TBTPLL;
+                        max = min;
+                        ret = icl_calc_dpll_state(crtc_state, encoder, clock,
+                                                  &pll_state);
+                } else {
+                        min = icl_port_to_mg_pll_id(port);
+                        max = min;
+                        ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
+                                                    &pll_state);
+                }
                 break;
         default:
                 MISSING_CASE(port);
@@ -2893,6 +2900,8 @@ static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
         case DPLL_ID_ICL_DPLL0:
         case DPLL_ID_ICL_DPLL1:
                 return CNL_DPLL_ENABLE(id);
+        case DPLL_ID_ICL_TBTPLL:
+                return TBT_PLL_ENABLE;
         case DPLL_ID_ICL_MGPLL1:
         case DPLL_ID_ICL_MGPLL2:
         case DPLL_ID_ICL_MGPLL3:
@@ -2920,6 +2929,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
         switch (id) {
         case DPLL_ID_ICL_DPLL0:
         case DPLL_ID_ICL_DPLL1:
+        case DPLL_ID_ICL_TBTPLL:
                 hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
                 hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
                 break;
@@ -3006,6 +3016,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
         switch (id) {
         case DPLL_ID_ICL_DPLL0:
         case DPLL_ID_ICL_DPLL1:
+        case DPLL_ID_ICL_TBTPLL:
                 icl_dpll_write(dev_priv, pll);
                 break;
         case DPLL_ID_ICL_MGPLL1:
@@ -3104,6 +3115,7 @@ static const struct intel_shared_dpll_funcs icl_pll_funcs = {
 static const struct dpll_info icl_plls[] = {
         { "DPLL 0",   &icl_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
         { "DPLL 1",   &icl_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
+        { "TBT PLL",  &icl_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
         { "MG PLL 1", &icl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
         { "MG PLL 2", &icl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
         { "MG PLL 3", &icl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 78915057d2e6..ba925c7ee482 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -114,23 +114,27 @@ enum intel_dpll_id {
          */
         DPLL_ID_ICL_DPLL1 = 1,
         /**
+         * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
+         */
+        DPLL_ID_ICL_TBTPLL = 2,
+        /**
          * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
          */
-        DPLL_ID_ICL_MGPLL1 = 2,
+        DPLL_ID_ICL_MGPLL1 = 3,
         /**
          * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
          */
-        DPLL_ID_ICL_MGPLL2 = 3,
+        DPLL_ID_ICL_MGPLL2 = 4,
         /**
          * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
          */
-        DPLL_ID_ICL_MGPLL3 = 4,
+        DPLL_ID_ICL_MGPLL3 = 5,
         /**
          * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
          */
-        DPLL_ID_ICL_MGPLL4 = 5,
+        DPLL_ID_ICL_MGPLL4 = 6,
 };
-#define I915_NUM_PLLS 6
+#define I915_NUM_PLLS 7
 
 struct intel_dpll_hw_state {
         /* i9xx, pch plls */