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authorPaolo Bonzini <pbonzini@redhat.com>2017-12-20 05:32:16 -0500
committerRadim Krčmář <rkrcmar@redhat.com>2018-01-16 10:52:48 -0500
commit1f6e5b25643e539e55a4c7553e4be6562c88fb76 (patch)
treed3e1ea94cf2411764759d5bce1e6f43450be11ff
parent07f36616cde482a9fd65da9a64f504190c7a0edb (diff)
KVM: vmx: simplify MSR bitmap setup
The APICv-enabled MSR bitmap is a superset of the APICv-disabled bitmap. Make that obvious in vmx_disable_intercept_msr_x2apic. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [Resolved rebase conflict after removing Intel PT. - Radim] Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
-rw-r--r--arch/x86/kvm/vmx.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index bbadd8c7e592..1f4a3037b99e 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -5017,14 +5017,13 @@ static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
5017 msr, MSR_TYPE_R | MSR_TYPE_W); 5017 msr, MSR_TYPE_R | MSR_TYPE_W);
5018} 5018}
5019 5019
5020static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active) 5020static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_only)
5021{ 5021{
5022 if (apicv_active) { 5022 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
5023 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv, 5023 msr, type);
5024 msr, type); 5024 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
5025 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, 5025 msr, type);
5026 msr, type); 5026 if (!apicv_only) {
5027 } else {
5028 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, 5027 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
5029 msr, type); 5028 msr, type);
5030 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, 5029 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
@@ -6872,7 +6871,6 @@ static __init int hardware_setup(void)
6872 * TPR reads and writes can be virtualized even if virtual interrupt 6871 * TPR reads and writes can be virtualized even if virtual interrupt
6873 * delivery is not in use. 6872 * delivery is not in use.
6874 */ 6873 */
6875 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6876 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false); 6874 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6877 6875
6878 /* EOI */ 6876 /* EOI */