diff options
author | Tomasz Figa <t.figa@samsung.com> | 2013-04-04 00:35:22 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-04-04 02:51:16 -0400 |
commit | 1f1f326763cf2352173eca1fc4116de6950ba773 (patch) | |
tree | 69ed402e3c49e88527fd12575f0970d5d2f54515 | |
parent | 7406ee7c2a31c0fad0d8062de93fcb58d1fa498c (diff) |
clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
This definition is specific for Exynos4210 (which has another location
than the same register on Exynos4x12 SoCs) and so needs appropriate
prefix.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 3d8a8a6fc5d0..b4daffaeb3f9 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c | |||
@@ -91,7 +91,7 @@ | |||
91 | #define GATE_IP_FSYS 0xc940 | 91 | #define GATE_IP_FSYS 0xc940 |
92 | #define GATE_IP_GPS 0xc94c | 92 | #define GATE_IP_GPS 0xc94c |
93 | #define GATE_IP_PERIL 0xc950 | 93 | #define GATE_IP_PERIL 0xc950 |
94 | #define GATE_IP_PERIR 0xc960 | 94 | #define E4210_GATE_IP_PERIR 0xc960 |
95 | #define E4X12_MPLL_CON0 0x10108 | 95 | #define E4X12_MPLL_CON0 0x10108 |
96 | #define E4X12_SRC_DMC 0x10200 | 96 | #define E4X12_SRC_DMC 0x10200 |
97 | #define APLL_CON0 0x14100 | 97 | #define APLL_CON0 0x14100 |
@@ -732,9 +732,9 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { | |||
732 | GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), | 732 | GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), |
733 | GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), | 733 | GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), |
734 | GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), | 734 | GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), |
735 | GATE(chipid, "chipid", "aclk100", GATE_IP_PERIR, 0, 0, 0), | 735 | GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), |
736 | GATE(sysreg, "sysreg", "aclk100", GATE_IP_PERIR, 0, 0, 0), | 736 | GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), |
737 | GATE(hdmi_cec, "hdmi_cec", "aclk100", GATE_IP_PERIR, 11, 0, 0), | 737 | GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0), |
738 | GATE(smmu_rotator, "smmu_rotator", "aclk200", | 738 | GATE(smmu_rotator, "smmu_rotator", "aclk200", |
739 | E4210_GATE_IP_IMAGE, 4, 0, 0), | 739 | E4210_GATE_IP_IMAGE, 4, 0, 0), |
740 | GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", | 740 | GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", |
@@ -744,10 +744,10 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { | |||
744 | GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), | 744 | GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), |
745 | GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), | 745 | GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), |
746 | GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"), | 746 | GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"), |
747 | GATE_A(mct, "mct", "aclk100", GATE_IP_PERIR, 13, 0, 0, "mct"), | 747 | GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"), |
748 | GATE_A(wdt, "watchdog", "aclk100", GATE_IP_PERIR, 14, 0, 0, "watchdog"), | 748 | GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"), |
749 | GATE_A(rtc, "rtc", "aclk100", GATE_IP_PERIR, 15, 0, 0, "rtc"), | 749 | GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"), |
750 | GATE_A(keyif, "keyif", "aclk100", GATE_IP_PERIR, 16, 0, 0, "keypad"), | 750 | GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"), |
751 | GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", | 751 | GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", |
752 | E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), | 752 | E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), |
753 | }; | 753 | }; |