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authorMatt Redfearn <matt.redfearn@mips.com>2017-11-09 06:02:44 -0500
committerMarc Zyngier <marc.zyngier@arm.com>2017-11-09 06:35:21 -0500
commit1f19aee0ec404112cec08f0c852fcd291690fbc7 (patch)
treec44e52c0f0ad74056ed568369bd5f37837b2083f
parent90af7c254ffb94b0df47bf6f613e3f3173df05d1 (diff)
irqchip/mips-gic: Add pr_fmt and reword pr_* messages
Several messages from the MIPS GIC driver include the text "GIC", but the format is not standard. Add a pr_fmt of "irq-mips-gic: " and reword the messages now that they will be prefixed with the driver name. Signed-off-by: Matt Redfearn <matt.redfearn@mips.com> Reviewed-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
-rw-r--r--drivers/irqchip/irq-mips-gic.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 3ccebb020f40..9b768899f07b 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -6,6 +6,9 @@
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) 6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 */ 8 */
9
10#define pr_fmt(fmt) "irq-mips-gic: " fmt
11
9#include <linux/bitmap.h> 12#include <linux/bitmap.h>
10#include <linux/clocksource.h> 13#include <linux/clocksource.h>
11#include <linux/cpuhotplug.h> 14#include <linux/cpuhotplug.h>
@@ -685,7 +688,7 @@ static int __init gic_of_init(struct device_node *node,
685 688
686 cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM)); 689 cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
687 if (cpu_vec == hweight_long(ST0_IM)) { 690 if (cpu_vec == hweight_long(ST0_IM)) {
688 pr_err("No CPU vectors available for GIC\n"); 691 pr_err("No CPU vectors available\n");
689 return -ENODEV; 692 return -ENODEV;
690 } 693 }
691 694
@@ -699,7 +702,7 @@ static int __init gic_of_init(struct device_node *node,
699 ~CM_GCR_GIC_BASE_GICEN; 702 ~CM_GCR_GIC_BASE_GICEN;
700 gic_len = 0x20000; 703 gic_len = 0x20000;
701 } else { 704 } else {
702 pr_err("Failed to get GIC memory range\n"); 705 pr_err("Failed to get memory range\n");
703 return -ENODEV; 706 return -ENODEV;
704 } 707 }
705 } else { 708 } else {
@@ -757,7 +760,7 @@ static int __init gic_of_init(struct device_node *node,
757 gic_shared_intrs, 0, 760 gic_shared_intrs, 0,
758 &gic_irq_domain_ops, NULL); 761 &gic_irq_domain_ops, NULL);
759 if (!gic_irq_domain) { 762 if (!gic_irq_domain) {
760 pr_err("Failed to add GIC IRQ domain"); 763 pr_err("Failed to add IRQ domain");
761 return -ENXIO; 764 return -ENXIO;
762 } 765 }
763 766
@@ -766,7 +769,7 @@ static int __init gic_of_init(struct device_node *node,
766 GIC_NUM_LOCAL_INTRS + gic_shared_intrs, 769 GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
767 node, &gic_ipi_domain_ops, NULL); 770 node, &gic_ipi_domain_ops, NULL);
768 if (!gic_ipi_domain) { 771 if (!gic_ipi_domain) {
769 pr_err("Failed to add GIC IPI domain"); 772 pr_err("Failed to add IPI domain");
770 return -ENXIO; 773 return -ENXIO;
771 } 774 }
772 775