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authorMarc Zyngier <marc.zyngier@arm.com>2015-03-11 11:43:45 -0400
committerJason Cooper <jason@lakedaemon.net>2015-03-14 20:55:30 -0400
commit1e7449ba67506b84f23dbd4a0667c09184df1368 (patch)
tree9a03e20d43cc5f3dc173d4778814af98e2f429fe
parent783d31863fb826f1a3754a2d5959a022a1b12d54 (diff)
DT: update ti,irq-crossbar binding
Make it look like a real interrupt controller. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088629-15377-4-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r--Documentation/devicetree/bindings/arm/omap/crossbar.txt18
1 files changed, 5 insertions, 13 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db353d0a..a9b28d74d902 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
9Required properties: 9Required properties:
10- compatible : Should be "ti,irq-crossbar" 10- compatible : Should be "ti,irq-crossbar"
11- reg: Base address and the size of the crossbar registers. 11- reg: Base address and the size of the crossbar registers.
12- ti,max-irqs: Total number of irqs available at the interrupt controller. 12- interrupt-controller: indicates that this block is an interrupt controller.
13- interrupt-parent: the interrupt controller this block is connected to.
14- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
13- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. 15- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
14- ti,reg-size: Size of a individual register in bytes. Every individual 16- ti,reg-size: Size of a individual register in bytes. Every individual
15 register is assumed to be of same size. Valid sizes are 1, 2, 4. 17 register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
27 when the interrupt controller irq is unused (when not provided, default is 0) 29 when the interrupt controller irq is unused (when not provided, default is 0)
28 30
29Examples: 31Examples:
30 crossbar_mpu: @4a020000 { 32 crossbar_mpu: crossbar@4a002a48 {
31 compatible = "ti,irq-crossbar"; 33 compatible = "ti,irq-crossbar";
32 reg = <0x4a002a48 0x130>; 34 reg = <0x4a002a48 0x130>;
33 ti,max-irqs = <160>; 35 ti,max-irqs = <160>;
34 ti,max-crossbar-sources = <400>; 36 ti,max-crossbar-sources = <400>;
35 ti,reg-size = <2>; 37 ti,reg-size = <2>;
36 ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; 38 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
37 ti,irqs-skip = <10 133 139 140>; 39 ti,irqs-skip = <10 133 139 140>;
38 }; 40 };
39 41
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details.
44 46
45An interrupt consumer on an SoC using crossbar will use: 47An interrupt consumer on an SoC using crossbar will use:
46 interrupts = <GIC_SPI request_number interrupt_level> 48 interrupts = <GIC_SPI request_number interrupt_level>
47When the request number is between 0 to that described by
48"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
49request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
50quirky hardware mapping direct to GIC.
51 49
52Example: 50Example:
53 device_x@0x4a023000 { 51 device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
55 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 53 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
56 ... 54 ...
57 }; 55 };
58
59 device_y@0x4a033000 {
60 /* Direct mapped GIC SPI 1 used */
61 interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
62 ...
63 };