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authorAndrzej Hajda <a.hajda@samsung.com>2018-02-20 02:05:39 -0500
committerSylwester Nawrocki <s.nawrocki@samsung.com>2018-02-23 09:15:20 -0500
commit1d5013f1b64dbd692975be5db0e42bac291c6de9 (patch)
tree2350d997075252d6895efe1541ad27274cd7b776
parent179db533c08431f509a3823077549773d519358b (diff)
clk: samsung: Add compile time PLL rate validators
Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c114
-rw-r--r--drivers/clk/samsung/clk-exynos4.c102
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c54
-rw-r--r--drivers/clk/samsung/clk-exynos5260.c90
-rw-r--r--drivers/clk/samsung/clk-exynos5410.c20
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c62
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c116
-rw-r--r--drivers/clk/samsung/clk-exynos7.c2
-rw-r--r--drivers/clk/samsung/clk-pll.h48
-rw-r--r--drivers/clk/samsung/clk-s3c2410.c108
10 files changed, 372 insertions, 344 deletions
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index ed36728424a2..27c9d23657b3 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -670,73 +670,73 @@ static const struct samsung_gate_clock gate_clks[] __initconst = {
670 670
671/* APLL & MPLL & BPLL & UPLL */ 671/* APLL & MPLL & BPLL & UPLL */
672static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = { 672static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {
673 PLL_35XX_RATE(1200000000, 400, 4, 1), 673 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
674 PLL_35XX_RATE(1100000000, 275, 3, 1), 674 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
675 PLL_35XX_RATE(1066000000, 533, 6, 1), 675 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
676 PLL_35XX_RATE(1000000000, 250, 3, 1), 676 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
677 PLL_35XX_RATE( 960000000, 320, 4, 1), 677 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
678 PLL_35XX_RATE( 900000000, 300, 4, 1), 678 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
679 PLL_35XX_RATE( 850000000, 425, 6, 1), 679 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
680 PLL_35XX_RATE( 800000000, 200, 3, 1), 680 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
681 PLL_35XX_RATE( 700000000, 175, 3, 1), 681 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
682 PLL_35XX_RATE( 667000000, 667, 12, 1), 682 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
683 PLL_35XX_RATE( 600000000, 400, 4, 2), 683 PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
684 PLL_35XX_RATE( 533000000, 533, 6, 2), 684 PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
685 PLL_35XX_RATE( 520000000, 260, 3, 2), 685 PLL_35XX_RATE(24 * MHZ, 520000000, 260, 3, 2),
686 PLL_35XX_RATE( 500000000, 250, 3, 2), 686 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
687 PLL_35XX_RATE( 400000000, 200, 3, 2), 687 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
688 PLL_35XX_RATE( 200000000, 200, 3, 3), 688 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
689 PLL_35XX_RATE( 100000000, 200, 3, 4), 689 PLL_35XX_RATE(24 * MHZ, 100000000, 200, 3, 4),
690 { /* sentinel */ } 690 { /* sentinel */ }
691}; 691};
692 692
693/* EPLL */ 693/* EPLL */
694static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = { 694static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {
695 PLL_36XX_RATE(800000000, 200, 3, 1, 0), 695 PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
696 PLL_36XX_RATE(288000000, 96, 2, 2, 0), 696 PLL_36XX_RATE(24 * MHZ, 288000000, 96, 2, 2, 0),
697 PLL_36XX_RATE(192000000, 128, 2, 3, 0), 697 PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3, 0),
698 PLL_36XX_RATE(144000000, 96, 2, 3, 0), 698 PLL_36XX_RATE(24 * MHZ, 144000000, 96, 2, 3, 0),
699 PLL_36XX_RATE( 96000000, 128, 2, 4, 0), 699 PLL_36XX_RATE(24 * MHZ, 96000000, 128, 2, 4, 0),
700 PLL_36XX_RATE( 84000000, 112, 2, 4, 0), 700 PLL_36XX_RATE(24 * MHZ, 84000000, 112, 2, 4, 0),
701 PLL_36XX_RATE( 80000003, 106, 2, 4, 43691), 701 PLL_36XX_RATE(24 * MHZ, 80000003, 106, 2, 4, 43691),
702 PLL_36XX_RATE( 73728000, 98, 2, 4, 19923), 702 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
703 PLL_36XX_RATE( 67737598, 270, 3, 5, 62285), 703 PLL_36XX_RATE(24 * MHZ, 67737598, 270, 3, 5, 62285),
704 PLL_36XX_RATE( 65535999, 174, 2, 5, 49982), 704 PLL_36XX_RATE(24 * MHZ, 65535999, 174, 2, 5, 49982),
705 PLL_36XX_RATE( 50000000, 200, 3, 5, 0), 705 PLL_36XX_RATE(24 * MHZ, 50000000, 200, 3, 5, 0),
706 PLL_36XX_RATE( 49152002, 131, 2, 5, 4719), 706 PLL_36XX_RATE(24 * MHZ, 49152002, 131, 2, 5, 4719),
707 PLL_36XX_RATE( 48000000, 128, 2, 5, 0), 707 PLL_36XX_RATE(24 * MHZ, 48000000, 128, 2, 5, 0),
708 PLL_36XX_RATE( 45158401, 180, 3, 5, 41524), 708 PLL_36XX_RATE(24 * MHZ, 45158401, 180, 3, 5, 41524),
709 { /* sentinel */ } 709 { /* sentinel */ }
710}; 710};
711 711
712/* VPLL */ 712/* VPLL */
713static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = { 713static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {
714 PLL_36XX_RATE(600000000, 100, 2, 1, 0), 714 PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
715 PLL_36XX_RATE(533000000, 266, 3, 2, 32768), 715 PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),
716 PLL_36XX_RATE(519230987, 173, 2, 2, 5046), 716 PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2, 5046),
717 PLL_36XX_RATE(500000000, 250, 3, 2, 0), 717 PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2, 0),
718 PLL_36XX_RATE(445500000, 148, 2, 2, 32768), 718 PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),
719 PLL_36XX_RATE(445055007, 148, 2, 2, 23047), 719 PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),
720 PLL_36XX_RATE(400000000, 200, 3, 2, 0), 720 PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
721 PLL_36XX_RATE(371250000, 123, 2, 2, 49152), 721 PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),
722 PLL_36XX_RATE(370878997, 185, 3, 2, 28803), 722 PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),
723 PLL_36XX_RATE(340000000, 170, 3, 2, 0), 723 PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2, 0),
724 PLL_36XX_RATE(335000015, 111, 2, 2, 43691), 724 PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),
725 PLL_36XX_RATE(333000000, 111, 2, 2, 0), 725 PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
726 PLL_36XX_RATE(330000000, 110, 2, 2, 0), 726 PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2, 0),
727 PLL_36XX_RATE(320000015, 106, 2, 2, 43691), 727 PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),
728 PLL_36XX_RATE(300000000, 100, 2, 2, 0), 728 PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
729 PLL_36XX_RATE(275000000, 275, 3, 3, 0), 729 PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3, 0),
730 PLL_36XX_RATE(222750000, 148, 2, 3, 32768), 730 PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),
731 PLL_36XX_RATE(222528007, 148, 2, 3, 23069), 731 PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),
732 PLL_36XX_RATE(160000000, 160, 3, 3, 0), 732 PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
733 PLL_36XX_RATE(148500000, 99, 2, 3, 0), 733 PLL_36XX_RATE(24 * MHZ, 148500000, 99, 2, 3, 0),
734 PLL_36XX_RATE(148352005, 98, 2, 3, 59070), 734 PLL_36XX_RATE(24 * MHZ, 148352005, 98, 2, 3, 59070),
735 PLL_36XX_RATE(108000000, 144, 2, 4, 0), 735 PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4, 0),
736 PLL_36XX_RATE( 74250000, 99, 2, 4, 0), 736 PLL_36XX_RATE(24 * MHZ, 74250000, 99, 2, 4, 0),
737 PLL_36XX_RATE( 74176002, 98, 2, 4, 59070), 737 PLL_36XX_RATE(24 * MHZ, 74176002, 98, 2, 4, 59070),
738 PLL_36XX_RATE( 54054000, 216, 3, 5, 14156), 738 PLL_36XX_RATE(24 * MHZ, 54054000, 216, 3, 5, 14156),
739 PLL_36XX_RATE( 54000000, 144, 2, 5, 0), 739 PLL_36XX_RATE(24 * MHZ, 54000000, 144, 2, 5, 0),
740 { /* sentinel */ } 740 { /* sentinel */ }
741}; 741};
742 742
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 134f25f2a913..edf125525a36 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1266,77 +1266,77 @@ static const struct of_device_id ext_clk_match[] __initconst = {
1266 1266
1267/* PLLs PMS values */ 1267/* PLLs PMS values */
1268static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = { 1268static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
1269 PLL_45XX_RATE(1200000000, 150, 3, 1, 28), 1269 PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
1270 PLL_45XX_RATE(1000000000, 250, 6, 1, 28), 1270 PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
1271 PLL_45XX_RATE( 800000000, 200, 6, 1, 28), 1271 PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
1272 PLL_45XX_RATE( 666857142, 389, 14, 1, 13), 1272 PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
1273 PLL_45XX_RATE( 600000000, 100, 4, 1, 13), 1273 PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
1274 PLL_45XX_RATE( 533000000, 533, 24, 1, 5), 1274 PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
1275 PLL_45XX_RATE( 500000000, 250, 6, 2, 28), 1275 PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
1276 PLL_45XX_RATE( 400000000, 200, 6, 2, 28), 1276 PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
1277 PLL_45XX_RATE( 200000000, 200, 6, 3, 28), 1277 PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
1278 { /* sentinel */ } 1278 { /* sentinel */ }
1279}; 1279};
1280 1280
1281static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = { 1281static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
1282 PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), 1282 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
1283 PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), 1283 PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),
1284 PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), 1284 PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0),
1285 PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1), 1285 PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1),
1286 PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1), 1286 PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1),
1287 PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0), 1287 PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0),
1288 PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0), 1288 PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0),
1289 { /* sentinel */ } 1289 { /* sentinel */ }
1290}; 1290};
1291 1291
1292static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = { 1292static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
1293 PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), 1293 PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),
1294 PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), 1294 PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1),
1295 PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), 1295 PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),
1296 PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0), 1296 PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),
1297 PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0), 1297 PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0),
1298 { /* sentinel */ } 1298 { /* sentinel */ }
1299}; 1299};
1300 1300
1301static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = { 1301static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
1302 PLL_35XX_RATE(1704000000, 213, 3, 0), 1302 PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
1303 PLL_35XX_RATE(1600000000, 200, 3, 0), 1303 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1304 PLL_35XX_RATE(1500000000, 250, 4, 0), 1304 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1305 PLL_35XX_RATE(1400000000, 175, 3, 0), 1305 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1306 PLL_35XX_RATE(1300000000, 325, 6, 0), 1306 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1307 PLL_35XX_RATE(1200000000, 200, 4, 0), 1307 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
1308 PLL_35XX_RATE(1100000000, 275, 6, 0), 1308 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
1309 PLL_35XX_RATE(1000000000, 125, 3, 0), 1309 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
1310 PLL_35XX_RATE( 900000000, 150, 4, 0), 1310 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
1311 PLL_35XX_RATE( 800000000, 100, 3, 0), 1311 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
1312 PLL_35XX_RATE( 700000000, 175, 3, 1), 1312 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
1313 PLL_35XX_RATE( 600000000, 200, 4, 1), 1313 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
1314 PLL_35XX_RATE( 500000000, 125, 3, 1), 1314 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
1315 PLL_35XX_RATE( 400000000, 100, 3, 1), 1315 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
1316 PLL_35XX_RATE( 300000000, 200, 4, 2), 1316 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
1317 PLL_35XX_RATE( 200000000, 100, 3, 2), 1317 PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
1318 { /* sentinel */ } 1318 { /* sentinel */ }
1319}; 1319};
1320 1320
1321static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = { 1321static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
1322 PLL_36XX_RATE(192000000, 48, 3, 1, 0), 1322 PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
1323 PLL_36XX_RATE(180633605, 45, 3, 1, 10381), 1323 PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
1324 PLL_36XX_RATE(180000000, 45, 3, 1, 0), 1324 PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),
1325 PLL_36XX_RATE( 73727996, 73, 3, 3, 47710), 1325 PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710),
1326 PLL_36XX_RATE( 67737602, 90, 4, 3, 20762), 1326 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762),
1327 PLL_36XX_RATE( 49151992, 49, 3, 3, 9961), 1327 PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961),
1328 PLL_36XX_RATE( 45158401, 45, 3, 3, 10381), 1328 PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381),
1329 { /* sentinel */ } 1329 { /* sentinel */ }
1330}; 1330};
1331 1331
1332static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = { 1332static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
1333 PLL_36XX_RATE(533000000, 133, 3, 1, 16384), 1333 PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),
1334 PLL_36XX_RATE(440000000, 110, 3, 1, 0), 1334 PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0),
1335 PLL_36XX_RATE(350000000, 175, 3, 2, 0), 1335 PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0),
1336 PLL_36XX_RATE(266000000, 133, 3, 2, 0), 1336 PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0),
1337 PLL_36XX_RATE(160000000, 160, 3, 3, 0), 1337 PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
1338 PLL_36XX_RATE(106031250, 53, 3, 2, 1024), 1338 PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024),
1339 PLL_36XX_RATE( 53015625, 53, 3, 3, 1024), 1339 PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024),
1340 { /* sentinel */ } 1340 { /* sentinel */ }
1341}; 1341};
1342 1342
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 923c608b1b95..1b3a8f9cd519 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -701,45 +701,45 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {
701static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = { 701static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
702 /* sorted in descending order */ 702 /* sorted in descending order */
703 /* PLL_36XX_RATE(rate, m, p, s, k) */ 703 /* PLL_36XX_RATE(rate, m, p, s, k) */
704 PLL_36XX_RATE(266000000, 266, 3, 3, 0), 704 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
705 /* Not in UM, but need for eDP on snow */ 705 /* Not in UM, but need for eDP on snow */
706 PLL_36XX_RATE(70500000, 94, 2, 4, 0), 706 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
707 { }, 707 { },
708}; 708};
709 709
710static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = { 710static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
711 /* sorted in descending order */ 711 /* sorted in descending order */
712 /* PLL_36XX_RATE(rate, m, p, s, k) */ 712 /* PLL_36XX_RATE(rate, m, p, s, k) */
713 PLL_36XX_RATE(192000000, 64, 2, 2, 0), 713 PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
714 PLL_36XX_RATE(180633605, 90, 3, 2, 20762), 714 PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
715 PLL_36XX_RATE(180000000, 90, 3, 2, 0), 715 PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
716 PLL_36XX_RATE(73728000, 98, 2, 4, 19923), 716 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
717 PLL_36XX_RATE(67737602, 90, 2, 4, 20762), 717 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
718 PLL_36XX_RATE(49152000, 98, 3, 4, 19923), 718 PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
719 PLL_36XX_RATE(45158401, 90, 3, 4, 20762), 719 PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
720 PLL_36XX_RATE(32768001, 131, 3, 5, 4719), 720 PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
721 { }, 721 { },
722}; 722};
723 723
724static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = { 724static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
725 /* sorted in descending order */ 725 /* sorted in descending order */
726 /* PLL_35XX_RATE(rate, m, p, s) */ 726 /* PLL_35XX_RATE(fin, rate, m, p, s) */
727 PLL_35XX_RATE(1700000000, 425, 6, 0), 727 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
728 PLL_35XX_RATE(1600000000, 200, 3, 0), 728 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
729 PLL_35XX_RATE(1500000000, 250, 4, 0), 729 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
730 PLL_35XX_RATE(1400000000, 175, 3, 0), 730 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
731 PLL_35XX_RATE(1300000000, 325, 6, 0), 731 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
732 PLL_35XX_RATE(1200000000, 200, 4, 0), 732 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
733 PLL_35XX_RATE(1100000000, 275, 6, 0), 733 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
734 PLL_35XX_RATE(1000000000, 125, 3, 0), 734 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
735 PLL_35XX_RATE(900000000, 150, 4, 0), 735 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
736 PLL_35XX_RATE(800000000, 100, 3, 0), 736 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
737 PLL_35XX_RATE(700000000, 175, 3, 1), 737 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
738 PLL_35XX_RATE(600000000, 200, 4, 1), 738 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
739 PLL_35XX_RATE(500000000, 125, 3, 1), 739 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
740 PLL_35XX_RATE(400000000, 100, 3, 1), 740 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
741 PLL_35XX_RATE(300000000, 200, 4, 2), 741 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
742 PLL_35XX_RATE(200000000, 100, 3, 2), 742 PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
743}; 743};
744 744
745static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 745static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
index 8eae1752d700..2cc2583abd87 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -23,57 +23,57 @@
23 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL. 23 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
24 */ 24 */
25static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = { 25static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
26 PLL_35XX_RATE(1700000000, 425, 6, 0), 26 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
27 PLL_35XX_RATE(1600000000, 200, 3, 0), 27 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
28 PLL_35XX_RATE(1500000000, 250, 4, 0), 28 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
29 PLL_35XX_RATE(1400000000, 175, 3, 0), 29 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
30 PLL_35XX_RATE(1300000000, 325, 6, 0), 30 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
31 PLL_35XX_RATE(1200000000, 400, 4, 1), 31 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
32 PLL_35XX_RATE(1100000000, 275, 3, 1), 32 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
33 PLL_35XX_RATE(1000000000, 250, 3, 1), 33 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
34 PLL_35XX_RATE(933000000, 311, 4, 1), 34 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
35 PLL_35XX_RATE(900000000, 300, 4, 1), 35 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
36 PLL_35XX_RATE(800000000, 200, 3, 1), 36 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
37 PLL_35XX_RATE(733000000, 733, 12, 1), 37 PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1),
38 PLL_35XX_RATE(700000000, 175, 3, 1), 38 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
39 PLL_35XX_RATE(667000000, 667, 12, 1), 39 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
40 PLL_35XX_RATE(633000000, 211, 4, 1), 40 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
41 PLL_35XX_RATE(620000000, 310, 3, 2), 41 PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2),
42 PLL_35XX_RATE(600000000, 400, 4, 2), 42 PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
43 PLL_35XX_RATE(543000000, 362, 4, 2), 43 PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2),
44 PLL_35XX_RATE(533000000, 533, 6, 2), 44 PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
45 PLL_35XX_RATE(500000000, 250, 3, 2), 45 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
46 PLL_35XX_RATE(450000000, 300, 4, 2), 46 PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2),
47 PLL_35XX_RATE(400000000, 200, 3, 2), 47 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
48 PLL_35XX_RATE(350000000, 175, 3, 2), 48 PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2),
49 PLL_35XX_RATE(300000000, 400, 4, 3), 49 PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3),
50 PLL_35XX_RATE(266000000, 266, 3, 3), 50 PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3),
51 PLL_35XX_RATE(200000000, 200, 3, 3), 51 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
52 PLL_35XX_RATE(160000000, 160, 3, 3), 52 PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3),
53}; 53};
54 54
55/* 55/*
56 * Applicable for 2650 Type PLL for AUD_PLL. 56 * Applicable for 2650 Type PLL for AUD_PLL.
57 */ 57 */
58static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = { 58static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
59 PLL_36XX_RATE(1600000000, 200, 3, 0, 0), 59 PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0),
60 PLL_36XX_RATE(1200000000, 100, 2, 0, 0), 60 PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0),
61 PLL_36XX_RATE(1000000000, 250, 3, 1, 0), 61 PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0),
62 PLL_36XX_RATE(800000000, 200, 3, 1, 0), 62 PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
63 PLL_36XX_RATE(600000000, 100, 2, 1, 0), 63 PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
64 PLL_36XX_RATE(532000000, 266, 3, 2, 0), 64 PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0),
65 PLL_36XX_RATE(480000000, 160, 2, 2, 0), 65 PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0),
66 PLL_36XX_RATE(432000000, 144, 2, 2, 0), 66 PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0),
67 PLL_36XX_RATE(400000000, 200, 3, 2, 0), 67 PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
68 PLL_36XX_RATE(394073128, 459, 7, 2, 49282), 68 PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282),
69 PLL_36XX_RATE(333000000, 111, 2, 2, 0), 69 PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
70 PLL_36XX_RATE(300000000, 100, 2, 2, 0), 70 PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
71 PLL_36XX_RATE(266000000, 266, 3, 3, 0), 71 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
72 PLL_36XX_RATE(200000000, 200, 3, 3, 0), 72 PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0),
73 PLL_36XX_RATE(166000000, 166, 3, 3, 0), 73 PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0),
74 PLL_36XX_RATE(133000000, 266, 3, 4, 0), 74 PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0),
75 PLL_36XX_RATE(100000000, 200, 3, 4, 0), 75 PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0),
76 PLL_36XX_RATE(66000000, 176, 2, 5, 0), 76 PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0),
77}; 77};
78 78
79/* CMU_AUD */ 79/* CMU_AUD */
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index fc471a49e8f4..0a0b09591e6f 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -226,16 +226,16 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
226}; 226};
227 227
228static const struct samsung_pll_rate_table exynos5410_pll2550x_24mhz_tbl[] __initconst = { 228static const struct samsung_pll_rate_table exynos5410_pll2550x_24mhz_tbl[] __initconst = {
229 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 229 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
230 PLL_36XX_RATE(333000000U, 111, 2, 2, 0), 230 PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
231 PLL_36XX_RATE(300000000U, 100, 2, 2, 0), 231 PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
232 PLL_36XX_RATE(266000000U, 266, 3, 3, 0), 232 PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
233 PLL_36XX_RATE(200000000U, 200, 3, 3, 0), 233 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
234 PLL_36XX_RATE(192000000U, 192, 3, 3, 0), 234 PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
235 PLL_36XX_RATE(166000000U, 166, 3, 3, 0), 235 PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
236 PLL_36XX_RATE(133000000U, 266, 3, 4, 0), 236 PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
237 PLL_36XX_RATE(100000000U, 200, 3, 4, 0), 237 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
238 PLL_36XX_RATE(66000000U, 176, 2, 5, 0), 238 PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
239}; 239};
240 240
241static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = { 241static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 45d34f601e9e..6b10b70f7d72 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1263,40 +1263,40 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
1263}; 1263};
1264 1264
1265static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 1265static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
1266 PLL_35XX_RATE(2000000000, 250, 3, 0), 1266 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1267 PLL_35XX_RATE(1900000000, 475, 6, 0), 1267 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1268 PLL_35XX_RATE(1800000000, 225, 3, 0), 1268 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1269 PLL_35XX_RATE(1700000000, 425, 6, 0), 1269 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1270 PLL_35XX_RATE(1600000000, 200, 3, 0), 1270 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1271 PLL_35XX_RATE(1500000000, 250, 4, 0), 1271 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1272 PLL_35XX_RATE(1400000000, 175, 3, 0), 1272 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1273 PLL_35XX_RATE(1300000000, 325, 6, 0), 1273 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1274 PLL_35XX_RATE(1200000000, 200, 2, 1), 1274 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1275 PLL_35XX_RATE(1100000000, 275, 3, 1), 1275 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
1276 PLL_35XX_RATE(1000000000, 250, 3, 1), 1276 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
1277 PLL_35XX_RATE(900000000, 150, 2, 1), 1277 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1),
1278 PLL_35XX_RATE(800000000, 200, 3, 1), 1278 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
1279 PLL_35XX_RATE(700000000, 175, 3, 1), 1279 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
1280 PLL_35XX_RATE(600000000, 200, 2, 2), 1280 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2),
1281 PLL_35XX_RATE(500000000, 250, 3, 2), 1281 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
1282 PLL_35XX_RATE(400000000, 200, 3, 2), 1282 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
1283 PLL_35XX_RATE(300000000, 200, 2, 3), 1283 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3),
1284 PLL_35XX_RATE(200000000, 200, 3, 3), 1284 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
1285}; 1285};
1286 1286
1287static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 1287static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
1288 PLL_36XX_RATE(600000000U, 100, 2, 1, 0), 1288 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
1289 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 1289 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
1290 PLL_36XX_RATE(393216003U, 197, 3, 2, -25690), 1290 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
1291 PLL_36XX_RATE(361267218U, 301, 5, 2, 3671), 1291 PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
1292 PLL_36XX_RATE(200000000U, 200, 3, 3, 0), 1292 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
1293 PLL_36XX_RATE(196608001U, 197, 3, 3, -25690), 1293 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
1294 PLL_36XX_RATE(180633609U, 301, 5, 3, 3671), 1294 PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
1295 PLL_36XX_RATE(131072006U, 131, 3, 3, 4719), 1295 PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
1296 PLL_36XX_RATE(100000000U, 200, 3, 4, 0), 1296 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
1297 PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719), 1297 PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719),
1298 PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690), 1298 PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690),
1299 PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719), 1299 PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
1300}; 1300};
1301 1301
1302static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1302static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 7985352ceb2f..5305ace514b2 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -703,69 +703,69 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
703 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL 703 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
704 */ 704 */
705static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = { 705static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
706 PLL_35XX_RATE(2500000000U, 625, 6, 0), 706 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
707 PLL_35XX_RATE(2400000000U, 500, 5, 0), 707 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
708 PLL_35XX_RATE(2300000000U, 575, 6, 0), 708 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
709 PLL_35XX_RATE(2200000000U, 550, 6, 0), 709 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
710 PLL_35XX_RATE(2100000000U, 350, 4, 0), 710 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
711 PLL_35XX_RATE(2000000000U, 500, 6, 0), 711 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
712 PLL_35XX_RATE(1900000000U, 475, 6, 0), 712 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
713 PLL_35XX_RATE(1800000000U, 375, 5, 0), 713 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
714 PLL_35XX_RATE(1700000000U, 425, 6, 0), 714 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
715 PLL_35XX_RATE(1600000000U, 400, 6, 0), 715 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
716 PLL_35XX_RATE(1500000000U, 250, 4, 0), 716 PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0),
717 PLL_35XX_RATE(1400000000U, 350, 6, 0), 717 PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0),
718 PLL_35XX_RATE(1332000000U, 222, 4, 0), 718 PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0),
719 PLL_35XX_RATE(1300000000U, 325, 6, 0), 719 PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0),
720 PLL_35XX_RATE(1200000000U, 500, 5, 1), 720 PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5, 1),
721 PLL_35XX_RATE(1100000000U, 550, 6, 1), 721 PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6, 1),
722 PLL_35XX_RATE(1086000000U, 362, 4, 1), 722 PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4, 1),
723 PLL_35XX_RATE(1066000000U, 533, 6, 1), 723 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6, 1),
724 PLL_35XX_RATE(1000000000U, 500, 6, 1), 724 PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6, 1),
725 PLL_35XX_RATE(933000000U, 311, 4, 1), 725 PLL_35XX_RATE(24 * MHZ, 933000000U, 311, 4, 1),
726 PLL_35XX_RATE(921000000U, 307, 4, 1), 726 PLL_35XX_RATE(24 * MHZ, 921000000U, 307, 4, 1),
727 PLL_35XX_RATE(900000000U, 375, 5, 1), 727 PLL_35XX_RATE(24 * MHZ, 900000000U, 375, 5, 1),
728 PLL_35XX_RATE(825000000U, 275, 4, 1), 728 PLL_35XX_RATE(24 * MHZ, 825000000U, 275, 4, 1),
729 PLL_35XX_RATE(800000000U, 400, 6, 1), 729 PLL_35XX_RATE(24 * MHZ, 800000000U, 400, 6, 1),
730 PLL_35XX_RATE(733000000U, 733, 12, 1), 730 PLL_35XX_RATE(24 * MHZ, 733000000U, 733, 12, 1),
731 PLL_35XX_RATE(700000000U, 175, 3, 1), 731 PLL_35XX_RATE(24 * MHZ, 700000000U, 175, 3, 1),
732 PLL_35XX_RATE(666000000U, 222, 4, 1), 732 PLL_35XX_RATE(24 * MHZ, 666000000U, 222, 4, 1),
733 PLL_35XX_RATE(633000000U, 211, 4, 1), 733 PLL_35XX_RATE(24 * MHZ, 633000000U, 211, 4, 1),
734 PLL_35XX_RATE(600000000U, 500, 5, 2), 734 PLL_35XX_RATE(24 * MHZ, 600000000U, 500, 5, 2),
735 PLL_35XX_RATE(552000000U, 460, 5, 2), 735 PLL_35XX_RATE(24 * MHZ, 552000000U, 460, 5, 2),
736 PLL_35XX_RATE(550000000U, 550, 6, 2), 736 PLL_35XX_RATE(24 * MHZ, 550000000U, 550, 6, 2),
737 PLL_35XX_RATE(543000000U, 362, 4, 2), 737 PLL_35XX_RATE(24 * MHZ, 543000000U, 362, 4, 2),
738 PLL_35XX_RATE(533000000U, 533, 6, 2), 738 PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2),
739 PLL_35XX_RATE(500000000U, 500, 6, 2), 739 PLL_35XX_RATE(24 * MHZ, 500000000U, 500, 6, 2),
740 PLL_35XX_RATE(444000000U, 370, 5, 2), 740 PLL_35XX_RATE(24 * MHZ, 444000000U, 370, 5, 2),
741 PLL_35XX_RATE(420000000U, 350, 5, 2), 741 PLL_35XX_RATE(24 * MHZ, 420000000U, 350, 5, 2),
742 PLL_35XX_RATE(400000000U, 400, 6, 2), 742 PLL_35XX_RATE(24 * MHZ, 400000000U, 400, 6, 2),
743 PLL_35XX_RATE(350000000U, 350, 6, 2), 743 PLL_35XX_RATE(24 * MHZ, 350000000U, 350, 6, 2),
744 PLL_35XX_RATE(333000000U, 222, 4, 2), 744 PLL_35XX_RATE(24 * MHZ, 333000000U, 222, 4, 2),
745 PLL_35XX_RATE(300000000U, 500, 5, 3), 745 PLL_35XX_RATE(24 * MHZ, 300000000U, 500, 5, 3),
746 PLL_35XX_RATE(278000000U, 556, 6, 3), 746 PLL_35XX_RATE(24 * MHZ, 278000000U, 556, 6, 3),
747 PLL_35XX_RATE(266000000U, 532, 6, 3), 747 PLL_35XX_RATE(24 * MHZ, 266000000U, 532, 6, 3),
748 PLL_35XX_RATE(250000000U, 500, 6, 3), 748 PLL_35XX_RATE(24 * MHZ, 250000000U, 500, 6, 3),
749 PLL_35XX_RATE(200000000U, 400, 6, 3), 749 PLL_35XX_RATE(24 * MHZ, 200000000U, 400, 6, 3),
750 PLL_35XX_RATE(166000000U, 332, 6, 3), 750 PLL_35XX_RATE(24 * MHZ, 166000000U, 332, 6, 3),
751 PLL_35XX_RATE(160000000U, 320, 6, 3), 751 PLL_35XX_RATE(24 * MHZ, 160000000U, 320, 6, 3),
752 PLL_35XX_RATE(133000000U, 532, 6, 4), 752 PLL_35XX_RATE(24 * MHZ, 133000000U, 532, 6, 4),
753 PLL_35XX_RATE(100000000U, 400, 6, 4), 753 PLL_35XX_RATE(24 * MHZ, 100000000U, 400, 6, 4),
754 { /* sentinel */ } 754 { /* sentinel */ }
755}; 755};
756 756
757/* AUD_PLL */ 757/* AUD_PLL */
758static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { 758static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
759 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 759 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
760 PLL_36XX_RATE(393216003U, 197, 3, 2, -25690), 760 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
761 PLL_36XX_RATE(384000000U, 128, 2, 2, 0), 761 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
762 PLL_36XX_RATE(368639991U, 246, 4, 2, -15729), 762 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
763 PLL_36XX_RATE(361507202U, 181, 3, 2, -16148), 763 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
764 PLL_36XX_RATE(338687988U, 113, 2, 2, -6816), 764 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
765 PLL_36XX_RATE(294912002U, 98, 1, 3, 19923), 765 PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923),
766 PLL_36XX_RATE(288000000U, 96, 1, 3, 0), 766 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
767 PLL_36XX_RATE(252000000U, 84, 1, 3, 0), 767 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
768 PLL_36XX_RATE(196608001U, 197, 3, 3, -25690), 768 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
769 { /* sentinel */ } 769 { /* sentinel */ }
770}; 770};
771 771
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index bbfa57b4e017..492d51691080 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -140,7 +140,7 @@ static const struct samsung_div_clock topc_div_clks[] __initconst = {
140}; 140};
141 141
142static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = { 142static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
143 PLL_36XX_RATE(491519897, 20, 1, 0, 31457), 143 PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457),
144 {}, 144 {},
145}; 145};
146 146
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 61eb8abbfd9c..ca57b3dfa814 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -41,35 +41,62 @@ enum samsung_pll_type {
41 pll_1460x, 41 pll_1460x,
42}; 42};
43 43
44#define PLL_35XX_RATE(_rate, _m, _p, _s) \ 44#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
45 ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
46#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
47 BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
48
49#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \
50 { \
51 .rate = PLL_VALID_RATE(_fin, _rate, \
52 _m, _p, _s, 0, 16), \
53 .mdiv = (_m), \
54 .pdiv = (_p), \
55 .sdiv = (_s), \
56 }
57
58#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \
59 { \
60 .rate = PLL_VALID_RATE(_fin, _rate, \
61 _m + 8, _p + 2, _s, 0, 16), \
62 .mdiv = (_m), \
63 .pdiv = (_p), \
64 .sdiv = (_s), \
65 }
66
67#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \
45 { \ 68 { \
46 .rate = (_rate), \ 69 .rate = PLL_VALID_RATE(_fin, _rate, \
70 2 * (_m + 8), _p + 2, _s, 0, 16), \
47 .mdiv = (_m), \ 71 .mdiv = (_m), \
48 .pdiv = (_p), \ 72 .pdiv = (_p), \
49 .sdiv = (_s), \ 73 .sdiv = (_s), \
50 } 74 }
51 75
52#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \ 76#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
53 { \ 77 { \
54 .rate = (_rate), \ 78 .rate = PLL_VALID_RATE(_fin, _rate, \
79 _m, _p, _s, _k, 16), \
55 .mdiv = (_m), \ 80 .mdiv = (_m), \
56 .pdiv = (_p), \ 81 .pdiv = (_p), \
57 .sdiv = (_s), \ 82 .sdiv = (_s), \
58 .kdiv = (_k), \ 83 .kdiv = (_k), \
59 } 84 }
60 85
61#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \ 86#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \
62 { \ 87 { \
63 .rate = (_rate), \ 88 .rate = PLL_VALID_RATE(_fin, _rate, \
89 _m, _p, _s - 1, 0, 16), \
64 .mdiv = (_m), \ 90 .mdiv = (_m), \
65 .pdiv = (_p), \ 91 .pdiv = (_p), \
66 .sdiv = (_s), \ 92 .sdiv = (_s), \
67 .afc = (_afc), \ 93 .afc = (_afc), \
68 } 94 }
69 95
70#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel) \ 96#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \
71 { \ 97 { \
72 .rate = (_rate), \ 98 .rate = PLL_VALID_RATE(_fin, _rate, \
99 _m, _p, _s, _k, 16), \
73 .mdiv = (_m), \ 100 .mdiv = (_m), \
74 .pdiv = (_p), \ 101 .pdiv = (_p), \
75 .sdiv = (_s), \ 102 .sdiv = (_s), \
@@ -77,9 +104,10 @@ enum samsung_pll_type {
77 .vsel = (_vsel), \ 104 .vsel = (_vsel), \
78 } 105 }
79 106
80#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \ 107#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
81 { \ 108 { \
82 .rate = (_rate), \ 109 .rate = PLL_VALID_RATE(_fin, _rate, \
110 _m, _p, _s, _k, 10), \
83 .mdiv = (_m), \ 111 .mdiv = (_m), \
84 .pdiv = (_p), \ 112 .pdiv = (_p), \
85 .sdiv = (_s), \ 113 .sdiv = (_s), \
diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c
index d8e58a659467..0c6aa3e51336 100644
--- a/drivers/clk/samsung/clk-s3c2410.c
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -162,34 +162,34 @@ struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
162static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = { 162static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
163 /* sorted in descending order */ 163 /* sorted in descending order */
164 /* 2410A extras */ 164 /* 2410A extras */
165 PLL_35XX_RATE(270000000, 127, 1, 1), 165 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
166 PLL_35XX_RATE(268000000, 126, 1, 1), 166 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
167 PLL_35XX_RATE(266000000, 125, 1, 1), 167 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
168 PLL_35XX_RATE(226000000, 105, 1, 1), 168 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
169 PLL_35XX_RATE(210000000, 132, 2, 1), 169 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
170 /* 2410 common */ 170 /* 2410 common */
171 PLL_35XX_RATE(202800000, 161, 3, 1), 171 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
172 PLL_35XX_RATE(192000000, 88, 1, 1), 172 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
173 PLL_35XX_RATE(186000000, 85, 1, 1), 173 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
174 PLL_35XX_RATE(180000000, 82, 1, 1), 174 PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
175 PLL_35XX_RATE(170000000, 77, 1, 1), 175 PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
176 PLL_35XX_RATE(158000000, 71, 1, 1), 176 PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
177 PLL_35XX_RATE(152000000, 68, 1, 1), 177 PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
178 PLL_35XX_RATE(147000000, 90, 2, 1), 178 PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
179 PLL_35XX_RATE(135000000, 82, 2, 1), 179 PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
180 PLL_35XX_RATE(124000000, 116, 1, 2), 180 PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
181 PLL_35XX_RATE(118500000, 150, 2, 2), 181 PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
182 PLL_35XX_RATE(113000000, 105, 1, 2), 182 PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
183 PLL_35XX_RATE(101250000, 127, 2, 2), 183 PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
184 PLL_35XX_RATE(90000000, 112, 2, 2), 184 PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
185 PLL_35XX_RATE(84750000, 105, 2, 2), 185 PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
186 PLL_35XX_RATE(79000000, 71, 1, 2), 186 PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
187 PLL_35XX_RATE(67500000, 82, 2, 2), 187 PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
188 PLL_35XX_RATE(56250000, 142, 2, 3), 188 PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
189 PLL_35XX_RATE(48000000, 120, 2, 3), 189 PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
190 PLL_35XX_RATE(50700000, 161, 3, 3), 190 PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
191 PLL_35XX_RATE(45000000, 82, 1, 3), 191 PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
192 PLL_35XX_RATE(33750000, 82, 2, 3), 192 PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
193 { /* sentinel */ }, 193 { /* sentinel */ },
194}; 194};
195 195
@@ -229,33 +229,33 @@ struct samsung_clock_alias s3c2410_aliases[] __initdata = {
229 229
230static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = { 230static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
231 /* sorted in descending order */ 231 /* sorted in descending order */
232 PLL_35XX_RATE(400000000, 0x5c, 1, 1), 232 PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
233 PLL_35XX_RATE(390000000, 0x7a, 2, 1), 233 PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
234 PLL_35XX_RATE(380000000, 0x57, 1, 1), 234 PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
235 PLL_35XX_RATE(370000000, 0xb1, 4, 1), 235 PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
236 PLL_35XX_RATE(360000000, 0x70, 2, 1), 236 PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
237 PLL_35XX_RATE(350000000, 0xa7, 4, 1), 237 PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
238 PLL_35XX_RATE(340000000, 0x4d, 1, 1), 238 PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
239 PLL_35XX_RATE(330000000, 0x66, 2, 1), 239 PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
240 PLL_35XX_RATE(320000000, 0x98, 4, 1), 240 PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
241 PLL_35XX_RATE(310000000, 0x93, 4, 1), 241 PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
242 PLL_35XX_RATE(300000000, 0x75, 3, 1), 242 PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
243 PLL_35XX_RATE(240000000, 0x70, 1, 2), 243 PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
244 PLL_35XX_RATE(230000000, 0x6b, 1, 2), 244 PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
245 PLL_35XX_RATE(220000000, 0x66, 1, 2), 245 PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
246 PLL_35XX_RATE(210000000, 0x84, 2, 2), 246 PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
247 PLL_35XX_RATE(200000000, 0x5c, 1, 2), 247 PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
248 PLL_35XX_RATE(190000000, 0x57, 1, 2), 248 PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
249 PLL_35XX_RATE(180000000, 0x70, 2, 2), 249 PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
250 PLL_35XX_RATE(170000000, 0x4d, 1, 2), 250 PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
251 PLL_35XX_RATE(160000000, 0x98, 4, 2), 251 PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
252 PLL_35XX_RATE(150000000, 0x75, 3, 2), 252 PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
253 PLL_35XX_RATE(120000000, 0x70, 1, 3), 253 PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
254 PLL_35XX_RATE(110000000, 0x66, 1, 3), 254 PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
255 PLL_35XX_RATE(100000000, 0x5c, 1, 3), 255 PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
256 PLL_35XX_RATE(90000000, 0x70, 2, 3), 256 PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
257 PLL_35XX_RATE(80000000, 0x98, 4, 3), 257 PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
258 PLL_35XX_RATE(75000000, 0x75, 3, 3), 258 PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
259 { /* sentinel */ }, 259 { /* sentinel */ },
260}; 260};
261 261
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 10:14:22 -0400