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authorDouglas Anderson <dianders@chromium.org>2019-05-20 13:56:05 -0400
committerFelipe Balbi <felipe.balbi@linux.intel.com>2019-06-18 04:58:28 -0400
commit1d390437f605db28596ad4c4bfeca2fed052c025 (patch)
tree6471c13c669480a7380af743d03dc400be3fe423
parentcd5f9726773b654f8e1cfd6ec1a989c558fa164b (diff)
ARM: dts: rockchip: Allow wakeup from rk3288-veyron's dwc2 USB ports
We want to be able to wake from USB if a device is plugged in that wants remote wakeup. Enable it on both dwc2 controllers. NOTE: this is added specifically to veyron and not to rk3288 in general since it's not known whether all rk3288 boards are designed to support USB wakeup. It is plausible that some boards could shut down important rails in S3. Also note that currently wakeup doesn't seem to happen unless you use the "deep" suspend mode (where SDRAM is turned off). Presumably the shallow suspend mode is gating some sort of clock that's important but I couldn't easily figure out how to get it working. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
-rw-r--r--arch/arm/boot/dts/rk3288-veyron.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 1252522392c7..1d8bfed7830c 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -424,6 +424,7 @@
424 424
425&usb_host1 { 425&usb_host1 {
426 status = "okay"; 426 status = "okay";
427 snps,need-phy-for-wake;
427}; 428};
428 429
429&usb_otg { 430&usb_otg {
@@ -432,6 +433,7 @@
432 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; 433 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
433 assigned-clock-parents = <&usbphy0>; 434 assigned-clock-parents = <&usbphy0>;
434 dr_mode = "host"; 435 dr_mode = "host";
436 snps,need-phy-for-wake;
435}; 437};
436 438
437&vopb { 439&vopb {