diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-07-08 11:55:27 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-07-08 11:55:27 -0400 |
commit | 1d110cf5d307bd52e826a2ceaa7daab83be61b7a (patch) | |
tree | a322590480d0ca5bbb06a1d57023d4344271fea5 | |
parent | cc23c619f8da3ccbe6a856c79fb5a3d245b68daf (diff) | |
parent | 39c8859418d5d2d29482fcd7d58daba6e299fac5 (diff) |
Merge tag 'drm-fixes-for-v4.7-rc7' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"One nouveau fix, and a few AMD Polaris fixes and some Allwinner fixes.
I've got some vmware fixes that I might send separate over the
weekend, they fix some black screens, but I'm still debating them"
* tag 'drm-fixes-for-v4.7-rc7' of git://people.freedesktop.org/~airlied/linux:
drm/amd/powerplay: Update CKS on/ CKS off voltage offset calculation.
drm/amd/powerplay: fix bug that get wrong polaris evv voltage.
drm/amd/powerplay: incorrectly use of the function return value
drm/amd/powerplay: fix incorrect voltage table value for tonga
drm/amd/powerplay: fix incorrect voltage table value for polaris10
drm/nouveau/disp/sor/gf119: select correct sor when poking training pattern
gpu: drm: sun4i_drv: add missing of_node_put after calling of_parse_phandle
drm/sun4i: Send vblank event when the CRTC is disabled
drm/sun4i: Report proper vblank
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 32 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_crtc.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_drv.c | 3 |
8 files changed, 32 insertions, 24 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c index ec2a7ada346a..91e25f942d90 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | |||
@@ -98,7 +98,6 @@ | |||
98 | #define PCIE_BUS_CLK 10000 | 98 | #define PCIE_BUS_CLK 10000 |
99 | #define TCLK (PCIE_BUS_CLK / 10) | 99 | #define TCLK (PCIE_BUS_CLK / 10) |
100 | 100 | ||
101 | #define CEILING_UCHAR(double) ((double-(uint8_t)(double)) > 0 ? (uint8_t)(double+1) : (uint8_t)(double)) | ||
102 | 101 | ||
103 | static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] = | 102 | static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] = |
104 | { {600, 1050, 3, 0}, {600, 1050, 6, 1} }; | 103 | { {600, 1050, 3, 0}, {600, 1050, 6, 1} }; |
@@ -733,7 +732,7 @@ static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, | |||
733 | table->Smio[level] |= | 732 | table->Smio[level] |= |
734 | data->mvdd_voltage_table.entries[level].smio_low; | 733 | data->mvdd_voltage_table.entries[level].smio_low; |
735 | } | 734 | } |
736 | table->SmioMask2 = data->vddci_voltage_table.mask_low; | 735 | table->SmioMask2 = data->mvdd_voltage_table.mask_low; |
737 | 736 | ||
738 | table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); | 737 | table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); |
739 | } | 738 | } |
@@ -1807,27 +1806,25 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) | |||
1807 | 1806 | ||
1808 | ro = efuse * (max -min)/255 + min; | 1807 | ro = efuse * (max -min)/255 + min; |
1809 | 1808 | ||
1810 | /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset | 1809 | /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ |
1811 | * there is a little difference in calculating | ||
1812 | * volt_with_cks with windows */ | ||
1813 | for (i = 0; i < sclk_table->count; i++) { | 1810 | for (i = 0; i < sclk_table->count; i++) { |
1814 | data->smc_state_table.Sclk_CKS_masterEn0_7 |= | 1811 | data->smc_state_table.Sclk_CKS_masterEn0_7 |= |
1815 | sclk_table->entries[i].cks_enable << i; | 1812 | sclk_table->entries[i].cks_enable << i; |
1816 | if (hwmgr->chip_id == CHIP_POLARIS10) { | 1813 | if (hwmgr->chip_id == CHIP_POLARIS10) { |
1817 | volt_without_cks = (uint32_t)((2753594000 + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \ | 1814 | volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \ |
1818 | (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000)); | 1815 | (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000)); |
1819 | volt_with_cks = (uint32_t)((279720200 + sclk_table->entries[i].clk * 3232 - (ro - 65) * 100000000) / \ | 1816 | volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \ |
1820 | (252248000 - sclk_table->entries[i].clk/100 * 115764)); | 1817 | (2522480 - sclk_table->entries[i].clk/100 * 115764/100)); |
1821 | } else { | 1818 | } else { |
1822 | volt_without_cks = (uint32_t)((2416794800 + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \ | 1819 | volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \ |
1823 | (2625416 - (sclk_table->entries[i].clk/100) * 12586807/10000)); | 1820 | (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000))); |
1824 | volt_with_cks = (uint32_t)((2999656000 + sclk_table->entries[i].clk * 392803/100 - (ro - 44) * 1000000) / \ | 1821 | volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \ |
1825 | (3422454 - sclk_table->entries[i].clk/100 * 18886376/10000)); | 1822 | (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000))); |
1826 | } | 1823 | } |
1827 | 1824 | ||
1828 | if (volt_without_cks >= volt_with_cks) | 1825 | if (volt_without_cks >= volt_with_cks) |
1829 | volt_offset = (uint8_t)CEILING_UCHAR((volt_without_cks - volt_with_cks + | 1826 | volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + |
1830 | sclk_table->entries[i].cks_voffset) * 100 / 625); | 1827 | sclk_table->entries[i].cks_voffset) * 100 + 624) / 625); |
1831 | 1828 | ||
1832 | data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; | 1829 | data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; |
1833 | } | 1830 | } |
@@ -2685,7 +2682,7 @@ static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr) | |||
2685 | { | 2682 | { |
2686 | struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); | 2683 | struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); |
2687 | uint16_t vv_id; | 2684 | uint16_t vv_id; |
2688 | uint16_t vddc = 0; | 2685 | uint32_t vddc = 0; |
2689 | uint16_t i, j; | 2686 | uint16_t i, j; |
2690 | uint32_t sclk = 0; | 2687 | uint32_t sclk = 0; |
2691 | struct phm_ppt_v1_information *table_info = | 2688 | struct phm_ppt_v1_information *table_info = |
@@ -2716,8 +2713,9 @@ static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr) | |||
2716 | continue); | 2713 | continue); |
2717 | 2714 | ||
2718 | 2715 | ||
2719 | /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ | 2716 | /* need to make sure vddc is less than 2v or else, it could burn the ASIC. |
2720 | PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), | 2717 | * real voltage level in unit of 0.01mv */ |
2718 | PP_ASSERT_WITH_CODE((vddc < 200000 && vddc != 0), | ||
2721 | "Invalid VDDC value", result = -EINVAL;); | 2719 | "Invalid VDDC value", result = -EINVAL;); |
2722 | 2720 | ||
2723 | /* the voltage should not be zero nor equal to leakage ID */ | 2721 | /* the voltage should not be zero nor equal to leakage ID */ |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c index bf4e18fd3872..90b35c5c10a4 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c | |||
@@ -1256,7 +1256,7 @@ int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, | |||
1256 | } | 1256 | } |
1257 | 1257 | ||
1258 | int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, | 1258 | int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, |
1259 | uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage) | 1259 | uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage) |
1260 | { | 1260 | { |
1261 | 1261 | ||
1262 | int result; | 1262 | int result; |
@@ -1274,7 +1274,7 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_ | |||
1274 | if (0 != result) | 1274 | if (0 != result) |
1275 | return result; | 1275 | return result; |
1276 | 1276 | ||
1277 | *voltage = get_voltage_info_param_space.usVoltageLevel; | 1277 | *voltage = ((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel; |
1278 | 1278 | ||
1279 | return result; | 1279 | return result; |
1280 | } | 1280 | } |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h index 248c5db5f380..1e35a9625baf 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h | |||
@@ -305,7 +305,7 @@ extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t | |||
305 | extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, | 305 | extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, |
306 | uint8_t level); | 306 | uint8_t level); |
307 | extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, | 307 | extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, |
308 | uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); | 308 | uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage); |
309 | extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table); | 309 | extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table); |
310 | 310 | ||
311 | extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param); | 311 | extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param); |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c index 233eb7f36c1d..5d0f655bf160 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | |||
@@ -1302,7 +1302,7 @@ static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, | |||
1302 | table->Smio[count] |= | 1302 | table->Smio[count] |= |
1303 | data->mvdd_voltage_table.entries[count].smio_low; | 1303 | data->mvdd_voltage_table.entries[count].smio_low; |
1304 | } | 1304 | } |
1305 | table->SmioMask2 = data->vddci_voltage_table.mask_low; | 1305 | table->SmioMask2 = data->mvdd_voltage_table.mask_low; |
1306 | 1306 | ||
1307 | CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); | 1307 | CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); |
1308 | } | 1308 | } |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c index 671fdb4d615a..dccc859f638c 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c | |||
@@ -302,7 +302,7 @@ static int init_dpm_2_parameters( | |||
302 | (((unsigned long)powerplay_table) + le16_to_cpu(powerplay_table->usPPMTableOffset)); | 302 | (((unsigned long)powerplay_table) + le16_to_cpu(powerplay_table->usPPMTableOffset)); |
303 | 303 | ||
304 | if (0 != powerplay_table->usPPMTableOffset) { | 304 | if (0 != powerplay_table->usPPMTableOffset) { |
305 | if (1 == get_platform_power_management_table(hwmgr, atom_ppm_table)) { | 305 | if (get_platform_power_management_table(hwmgr, atom_ppm_table) == 0) { |
306 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | 306 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
307 | PHM_PlatformCaps_EnablePlatformPowerManagement); | 307 | PHM_PlatformCaps_EnablePlatformPowerManagement); |
308 | } | 308 | } |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c index 22706c0a54b5..49bd5da194e1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c | |||
@@ -40,7 +40,8 @@ static int | |||
40 | gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) | 40 | gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) |
41 | { | 41 | { |
42 | struct nvkm_device *device = outp->base.disp->engine.subdev.device; | 42 | struct nvkm_device *device = outp->base.disp->engine.subdev.device; |
43 | nvkm_mask(device, 0x61c110, 0x0f0f0f0f, 0x01010101 * pattern); | 43 | const u32 soff = gf119_sor_soff(outp); |
44 | nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern); | ||
44 | return 0; | 45 | return 0; |
45 | } | 46 | } |
46 | 47 | ||
diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c index 4182a21f5923..41cacecbea9a 100644 --- a/drivers/gpu/drm/sun4i/sun4i_crtc.c +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c | |||
@@ -65,6 +65,14 @@ static void sun4i_crtc_disable(struct drm_crtc *crtc) | |||
65 | DRM_DEBUG_DRIVER("Disabling the CRTC\n"); | 65 | DRM_DEBUG_DRIVER("Disabling the CRTC\n"); |
66 | 66 | ||
67 | sun4i_tcon_disable(drv->tcon); | 67 | sun4i_tcon_disable(drv->tcon); |
68 | |||
69 | if (crtc->state->event && !crtc->state->active) { | ||
70 | spin_lock_irq(&crtc->dev->event_lock); | ||
71 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | ||
72 | spin_unlock_irq(&crtc->dev->event_lock); | ||
73 | |||
74 | crtc->state->event = NULL; | ||
75 | } | ||
68 | } | 76 | } |
69 | 77 | ||
70 | static void sun4i_crtc_enable(struct drm_crtc *crtc) | 78 | static void sun4i_crtc_enable(struct drm_crtc *crtc) |
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index 257d2b4f3645..937394cbc241 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c | |||
@@ -92,7 +92,7 @@ static struct drm_driver sun4i_drv_driver = { | |||
92 | /* Frame Buffer Operations */ | 92 | /* Frame Buffer Operations */ |
93 | 93 | ||
94 | /* VBlank Operations */ | 94 | /* VBlank Operations */ |
95 | .get_vblank_counter = drm_vblank_count, | 95 | .get_vblank_counter = drm_vblank_no_hw_counter, |
96 | .enable_vblank = sun4i_drv_enable_vblank, | 96 | .enable_vblank = sun4i_drv_enable_vblank, |
97 | .disable_vblank = sun4i_drv_disable_vblank, | 97 | .disable_vblank = sun4i_drv_disable_vblank, |
98 | }; | 98 | }; |
@@ -310,6 +310,7 @@ static int sun4i_drv_probe(struct platform_device *pdev) | |||
310 | 310 | ||
311 | count += sun4i_drv_add_endpoints(&pdev->dev, &match, | 311 | count += sun4i_drv_add_endpoints(&pdev->dev, &match, |
312 | pipeline); | 312 | pipeline); |
313 | of_node_put(pipeline); | ||
313 | 314 | ||
314 | DRM_DEBUG_DRIVER("Queued %d outputs on pipeline %d\n", | 315 | DRM_DEBUG_DRIVER("Queued %d outputs on pipeline %d\n", |
315 | count, i); | 316 | count, i); |