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authorGabriel FERNANDEZ <gabriel.fernandez@st.com>2014-08-25 10:44:00 -0400
committerMaxime Coquelin <maxime.coquelin@st.com>2014-10-31 04:59:09 -0400
commit1befe7e49f8d4e706e5ef39fb57dac1da734f163 (patch)
treed8e5a72e9d81672ed9ca46f4d391eb4b0992863d
parent58a8d9be52d917136c83ef8fde3bd3743d6db14c (diff)
ARM: STi: DT: STiH407: 407 DT Entry for clockgen C0
Patch adds DT entries for clockgen C0 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/stih407-clock.dtsi83
-rw-r--r--arch/arm/boot/dts/stih407.dtsi18
-rw-r--r--include/dt-bindings/clock/stih407-clks.h11
3 files changed, 103 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 1bfa6799d7c5..f85571a956f9 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -5,6 +5,7 @@
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8#include <dt-bindings/clock/stih407-clks.h>
8/ { 9/ {
9 clocks { 10 clocks {
10 #address-cells = <1>; 11 #address-cells = <1>;
@@ -64,5 +65,87 @@
64 clock-output-names = "clk-ic-lmi0"; 65 clock-output-names = "clk-ic-lmi0";
65 }; 66 };
66 }; 67 };
68
69 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
70 #clock-cells = <1>;
71 compatible = "st,stih407-quadfs660-C", "st,quadfs";
72 reg = <0x9103000 0x1000>;
73
74 clocks = <&clk_sysin>;
75
76 clock-output-names = "clk-s-c0-fs0-ch0",
77 "clk-s-c0-fs0-ch1",
78 "clk-s-c0-fs0-ch2",
79 "clk-s-c0-fs0-ch3";
80 };
81
82 clk_s_c0: clockgen-c@09103000 {
83 compatible = "st,clkgen-c32";
84 reg = <0x9103000 0x1000>;
85
86 clk_s_c0_pll0: clk-s-c0-pll0 {
87 #clock-cells = <1>;
88 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
89
90 clocks = <&clk_sysin>;
91
92 clock-output-names = "clk-s-c0-pll0-odf-0";
93 };
94
95 clk_s_c0_pll1: clk-s-c0-pll1 {
96 #clock-cells = <1>;
97 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
98
99 clocks = <&clk_sysin>;
100
101 clock-output-names = "clk-s-c0-pll1-odf-0";
102 };
103
104 clk_s_c0_flexgen: clk-s-c0-flexgen {
105 #clock-cells = <1>;
106 compatible = "st,flexgen";
107
108 clocks = <&clk_s_c0_pll0 0>,
109 <&clk_s_c0_pll1 0>,
110 <&clk_s_c0_quadfs 0>,
111 <&clk_s_c0_quadfs 1>,
112 <&clk_s_c0_quadfs 2>,
113 <&clk_s_c0_quadfs 3>,
114 <&clk_sysin>;
115
116 clock-output-names = "clk-icn-gpu",
117 "clk-fdma",
118 "clk-nand",
119 "clk-hva",
120 "clk-proc-stfe",
121 "clk-proc-tp",
122 "clk-rx-icn-dmu",
123 "clk-rx-icn-hva",
124 "clk-icn-cpu",
125 "clk-tx-icn-dmu",
126 "clk-mmc-0",
127 "clk-mmc-1",
128 "clk-jpegdec",
129 "clk-ext2fa9",
130 "clk-ic-bdisp-0",
131 "clk-ic-bdisp-1",
132 "clk-pp-dmu",
133 "clk-vid-dmu",
134 "clk-dss-lpc",
135 "clk-st231-aud-0",
136 "clk-st231-gp-1",
137 "clk-st231-dmu",
138 "clk-icn-lmi",
139 "clk-tx-icn-disp-1",
140 "clk-icn-sbc",
141 "clk-stfe-frc2",
142 "clk-eth-phy",
143 "clk-eth-ref-phyclk",
144 "clk-flash-promip",
145 "clk-main-disp",
146 "clk-aux-disp",
147 "clk-compo-dvp";
148 };
149 };
67 }; 150 };
68}; 151};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index d2f1aaa870ea..50637f5168d4 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -120,7 +120,7 @@
120 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; 120 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
121 pinctrl-names = "default"; 121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_serial0>; 122 pinctrl-0 = <&pinctrl_serial0>;
123 clocks = <&clk_ext2f_a9>; 123 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
124 124
125 status = "disabled"; 125 status = "disabled";
126 }; 126 };
@@ -131,7 +131,7 @@
131 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; 131 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
132 pinctrl-names = "default"; 132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_serial1>; 133 pinctrl-0 = <&pinctrl_serial1>;
134 clocks = <&clk_ext2f_a9>; 134 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
135 135
136 status = "disabled"; 136 status = "disabled";
137 }; 137 };
@@ -142,7 +142,7 @@
142 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; 142 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
143 pinctrl-names = "default"; 143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_serial2>; 144 pinctrl-0 = <&pinctrl_serial2>;
145 clocks = <&clk_ext2f_a9>; 145 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
146 146
147 status = "disabled"; 147 status = "disabled";
148 }; 148 };
@@ -174,7 +174,7 @@
174 compatible = "st,comms-ssc4-i2c"; 174 compatible = "st,comms-ssc4-i2c";
175 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 175 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
176 reg = <0x9840000 0x110>; 176 reg = <0x9840000 0x110>;
177 clocks = <&clk_ext2f_a9>; 177 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
178 clock-names = "ssc"; 178 clock-names = "ssc";
179 clock-frequency = <400000>; 179 clock-frequency = <400000>;
180 pinctrl-names = "default"; 180 pinctrl-names = "default";
@@ -187,7 +187,7 @@
187 compatible = "st,comms-ssc4-i2c"; 187 compatible = "st,comms-ssc4-i2c";
188 reg = <0x9841000 0x110>; 188 reg = <0x9841000 0x110>;
189 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 189 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&clk_ext2f_a9>; 190 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
191 clock-names = "ssc"; 191 clock-names = "ssc";
192 clock-frequency = <400000>; 192 clock-frequency = <400000>;
193 pinctrl-names = "default"; 193 pinctrl-names = "default";
@@ -200,7 +200,7 @@
200 compatible = "st,comms-ssc4-i2c"; 200 compatible = "st,comms-ssc4-i2c";
201 reg = <0x9842000 0x110>; 201 reg = <0x9842000 0x110>;
202 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 202 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&clk_ext2f_a9>; 203 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
204 clock-names = "ssc"; 204 clock-names = "ssc";
205 clock-frequency = <400000>; 205 clock-frequency = <400000>;
206 pinctrl-names = "default"; 206 pinctrl-names = "default";
@@ -213,7 +213,7 @@
213 compatible = "st,comms-ssc4-i2c"; 213 compatible = "st,comms-ssc4-i2c";
214 reg = <0x9843000 0x110>; 214 reg = <0x9843000 0x110>;
215 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 215 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clk_ext2f_a9>; 216 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
217 clock-names = "ssc"; 217 clock-names = "ssc";
218 clock-frequency = <400000>; 218 clock-frequency = <400000>;
219 pinctrl-names = "default"; 219 pinctrl-names = "default";
@@ -226,7 +226,7 @@
226 compatible = "st,comms-ssc4-i2c"; 226 compatible = "st,comms-ssc4-i2c";
227 reg = <0x9844000 0x110>; 227 reg = <0x9844000 0x110>;
228 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 228 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&clk_ext2f_a9>; 229 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
230 clock-names = "ssc"; 230 clock-names = "ssc";
231 clock-frequency = <400000>; 231 clock-frequency = <400000>;
232 pinctrl-names = "default"; 232 pinctrl-names = "default";
@@ -239,7 +239,7 @@
239 compatible = "st,comms-ssc4-i2c"; 239 compatible = "st,comms-ssc4-i2c";
240 reg = <0x9845000 0x110>; 240 reg = <0x9845000 0x110>;
241 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 241 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clk_ext2f_a9>; 242 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
243 clock-names = "ssc"; 243 clock-names = "ssc";
244 clock-frequency = <400000>; 244 clock-frequency = <400000>;
245 pinctrl-names = "default"; 245 pinctrl-names = "default";
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
new file mode 100644
index 000000000000..1f9bfe0e47f8
--- /dev/null
+++ b/include/dt-bindings/clock/stih407-clks.h
@@ -0,0 +1,11 @@
1/*
2 * This header provides constants clk index STMicroelectronics
3 * STiH407 SoC.
4 */
5#ifndef _DT_BINDINGS_CLK_STIH407
6#define _DT_BINDINGS_CLK_STIH407
7
8/* CLOCKGEN C0 */
9#define CLK_EXT2F_A9 13
10
11#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 22:17:23 -0400