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authorDavid S. Miller <davem@davemloft.net>2016-04-25 15:12:06 -0400
committerDavid S. Miller <davem@davemloft.net>2016-04-25 15:12:06 -0400
commit1bc7fe64b60b40d50e42ba4bb870bbfb95d64e21 (patch)
tree06c7729d87807b412cc3ff6c48675af2e2420d6b
parente7157f28ced492accf6e665ba0f748162757779f (diff)
parentd4f90d9dca26efef7a1112a8f4258c90b73bb37f (diff)
Merge branch '10GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
Jeff Kirsher says: ==================== 10GbE Intel Wired LAN Driver Updates 2016-04-25 This series contains updates to ixgbe and ixgbevf. Emil provides several patches, starting with the consolidation of the logic behind configuring spoof checking. Fixed an issue which was causing link issues for backplane devices because x550em_a/x devices did not have a default value for mac->ops.setup_link. Refactored the ethtool stats to bring the logic closer to how ixgbe handles stats and sets up per-queue stats for ixgbevf. Mark adds a new register to wait for previous register writes to complete before issuing a register read, which is needed when slower links are in use. Fixed the flow control setup for x550em_a, the incorrect fc_setup function was being used. Don added a workaround for empty SFP+ cage crosstalk, since on some systems the crosstalk could lead to link flap on empty SFP+ cages. Jake converts ixgbe and ixgbevf to use the BIT() macro. Alex Duyck adds support for partial GSO segmentation in the case of tunnels for ixgbe and ixgbevf. Then preps for HyperV by moving the API negotiation into mac_ops. Arnd Bergmann provides a fix for the ARM compile warnings in linux-next by converting the use of a udelay() to msleep(). ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe.h75
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c6
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c16
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_common.c70
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_common.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c4
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c6
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c14
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_main.c259
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c4
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c4
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c86
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_type.h168
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c4
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c14
-rw-r--r--drivers/net/ethernet/intel/ixgbevf/defines.h24
-rw-r--r--drivers/net/ethernet/intel/ixgbevf/ethtool.c230
-rw-r--r--drivers/net/ethernet/intel/ixgbevf/ixgbevf.h18
-rw-r--r--drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c149
-rw-r--r--drivers/net/ethernet/intel/ixgbevf/vf.c5
-rw-r--r--drivers/net/ethernet/intel/ixgbevf/vf.h2
24 files changed, 661 insertions, 505 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
index d10ed62993c1..781c8787ab66 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
@@ -143,14 +143,11 @@ struct vf_data_storage {
143 unsigned char vf_mac_addresses[ETH_ALEN]; 143 unsigned char vf_mac_addresses[ETH_ALEN];
144 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 144 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
145 u16 num_vf_mc_hashes; 145 u16 num_vf_mc_hashes;
146 u16 default_vf_vlan_id;
147 u16 vlans_enabled;
148 bool clear_to_send; 146 bool clear_to_send;
149 bool pf_set_mac; 147 bool pf_set_mac;
150 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 148 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
151 u16 pf_qos; 149 u16 pf_qos;
152 u16 tx_rate; 150 u16 tx_rate;
153 u16 vlan_count;
154 u8 spoofchk_enabled; 151 u8 spoofchk_enabled;
155 bool rss_query_enabled; 152 bool rss_query_enabled;
156 u8 trusted; 153 u8 trusted;
@@ -173,7 +170,7 @@ struct vf_macvlans {
173}; 170};
174 171
175#define IXGBE_MAX_TXD_PWR 14 172#define IXGBE_MAX_TXD_PWR 14
176#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) 173#define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR)
177 174
178/* Tx Descriptors needed, worst case */ 175/* Tx Descriptors needed, worst case */
179#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 176#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
@@ -623,44 +620,44 @@ struct ixgbe_adapter {
623 * thus the additional *_CAPABLE flags. 620 * thus the additional *_CAPABLE flags.
624 */ 621 */
625 u32 flags; 622 u32 flags;
626#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) 623#define IXGBE_FLAG_MSI_ENABLED BIT(1)
627#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) 624#define IXGBE_FLAG_MSIX_ENABLED BIT(3)
628#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) 625#define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4)
629#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) 626#define IXGBE_FLAG_RX_PS_CAPABLE BIT(5)
630#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) 627#define IXGBE_FLAG_RX_PS_ENABLED BIT(6)
631#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) 628#define IXGBE_FLAG_DCA_ENABLED BIT(8)
632#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) 629#define IXGBE_FLAG_DCA_CAPABLE BIT(9)
633#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) 630#define IXGBE_FLAG_IMIR_ENABLED BIT(10)
634#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) 631#define IXGBE_FLAG_MQ_CAPABLE BIT(11)
635#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) 632#define IXGBE_FLAG_DCB_ENABLED BIT(12)
636#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) 633#define IXGBE_FLAG_VMDQ_CAPABLE BIT(13)
637#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) 634#define IXGBE_FLAG_VMDQ_ENABLED BIT(14)
638#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) 635#define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15)
639#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) 636#define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16)
640#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) 637#define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17)
641#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) 638#define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18)
642#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) 639#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19)
643#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) 640#define IXGBE_FLAG_FCOE_CAPABLE BIT(20)
644#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) 641#define IXGBE_FLAG_FCOE_ENABLED BIT(21)
645#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) 642#define IXGBE_FLAG_SRIOV_CAPABLE BIT(22)
646#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) 643#define IXGBE_FLAG_SRIOV_ENABLED BIT(23)
647#define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) 644#define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24)
648#define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 645#define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25)
649#define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 646#define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26)
650 647
651 u32 flags2; 648 u32 flags2;
652#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) 649#define IXGBE_FLAG2_RSC_CAPABLE BIT(0)
653#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 650#define IXGBE_FLAG2_RSC_ENABLED BIT(1)
654#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 651#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2)
655#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) 652#define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3)
656#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) 653#define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4)
657#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) 654#define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5)
658#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) 655#define IXGBE_FLAG2_RESET_REQUESTED BIT(6)
659#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) 656#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7)
660#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) 657#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8)
661#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) 658#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9)
662#define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) 659#define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10)
663#define IXGBE_FLAG2_PHY_INTERRUPT (u32)(1 << 11) 660#define IXGBE_FLAG2_PHY_INTERRUPT BIT(11)
664#define IXGBE_FLAG2_VXLAN_REREG_NEEDED BIT(12) 661#define IXGBE_FLAG2_VXLAN_REREG_NEEDED BIT(12)
665#define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 662#define IXGBE_FLAG2_VLAN_PROMISC BIT(13)
666 663
@@ -806,6 +803,8 @@ struct ixgbe_adapter {
806 803
807#define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 804#define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
808 u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)]; 805 u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)];
806
807 bool need_crosstalk_fix;
809}; 808};
810 809
811static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 810static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
@@ -828,7 +827,7 @@ struct ixgbe_fdir_filter {
828 struct hlist_node fdir_node; 827 struct hlist_node fdir_node;
829 union ixgbe_atr_input filter; 828 union ixgbe_atr_input filter;
830 u16 sw_idx; 829 u16 sw_idx;
831 u16 action; 830 u64 action;
832}; 831};
833 832
834enum ixgbe_state_t { 833enum ixgbe_state_t {
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
index 6ecd598c6ef5..fb51be74dd4c 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
@@ -792,7 +792,7 @@ mac_reset_top:
792 } 792 }
793 793
794 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 794 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
795 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 795 gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6));
796 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 796 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
797 797
798 /* 798 /*
@@ -914,10 +914,10 @@ static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
914 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 914 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
915 if (vlan_on) 915 if (vlan_on)
916 /* Turn on this VLAN id */ 916 /* Turn on this VLAN id */
917 bits |= (1 << bitindex); 917 bits |= BIT(bitindex);
918 else 918 else
919 /* Turn off this VLAN id */ 919 /* Turn off this VLAN id */
920 bits &= ~(1 << bitindex); 920 bits &= ~BIT(bitindex);
921 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 921 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
922 922
923 return 0; 923 return 0;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
index 01519787324a..47afed74a54d 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
@@ -1296,17 +1296,17 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1296#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1296#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1297do { \ 1297do { \
1298 u32 n = (_n); \ 1298 u32 n = (_n); \
1299 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1299 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n)) \
1300 common_hash ^= lo_hash_dword >> n; \ 1300 common_hash ^= lo_hash_dword >> n; \
1301 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1301 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \
1302 bucket_hash ^= lo_hash_dword >> n; \ 1302 bucket_hash ^= lo_hash_dword >> n; \
1303 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1303 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n)) \
1304 sig_hash ^= lo_hash_dword << (16 - n); \ 1304 sig_hash ^= lo_hash_dword << (16 - n); \
1305 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1305 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n + 16)) \
1306 common_hash ^= hi_hash_dword >> n; \ 1306 common_hash ^= hi_hash_dword >> n; \
1307 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1307 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \
1308 bucket_hash ^= hi_hash_dword >> n; \ 1308 bucket_hash ^= hi_hash_dword >> n; \
1309 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1309 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n + 16)) \
1310 sig_hash ^= hi_hash_dword << (16 - n); \ 1310 sig_hash ^= hi_hash_dword << (16 - n); \
1311} while (0) 1311} while (0)
1312 1312
@@ -1440,9 +1440,9 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1440#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1440#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1441do { \ 1441do { \
1442 u32 n = (_n); \ 1442 u32 n = (_n); \
1443 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1443 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \
1444 bucket_hash ^= lo_hash_dword >> n; \ 1444 bucket_hash ^= lo_hash_dword >> n; \
1445 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1445 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \
1446 bucket_hash ^= hi_hash_dword >> n; \ 1446 bucket_hash ^= hi_hash_dword >> n; \
1447} while (0) 1447} while (0)
1448 1448
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
index 737443a015d5..902d2061ce73 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
@@ -825,8 +825,8 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
825 */ 825 */
826 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 826 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
827 IXGBE_EEC_SIZE_SHIFT); 827 IXGBE_EEC_SIZE_SHIFT);
828 eeprom->word_size = 1 << (eeprom_size + 828 eeprom->word_size = BIT(eeprom_size +
829 IXGBE_EEPROM_WORD_SIZE_SHIFT); 829 IXGBE_EEPROM_WORD_SIZE_SHIFT);
830 } 830 }
831 831
832 if (eec & IXGBE_EEC_ADDR_SIZE) 832 if (eec & IXGBE_EEC_ADDR_SIZE)
@@ -1502,7 +1502,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1502 * Mask is used to shift "count" bits of "data" out to the EEPROM 1502 * Mask is used to shift "count" bits of "data" out to the EEPROM
1503 * one bit at a time. Determine the starting bit based on count 1503 * one bit at a time. Determine the starting bit based on count
1504 */ 1504 */
1505 mask = 0x01 << (count - 1); 1505 mask = BIT(count - 1);
1506 1506
1507 for (i = 0; i < count; i++) { 1507 for (i = 0; i < count; i++) {
1508 /* 1508 /*
@@ -1991,7 +1991,7 @@ static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1991 */ 1991 */
1992 vector_reg = (vector >> 5) & 0x7F; 1992 vector_reg = (vector >> 5) & 0x7F;
1993 vector_bit = vector & 0x1F; 1993 vector_bit = vector & 0x1F;
1994 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 1994 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit);
1995} 1995}
1996 1996
1997/** 1997/**
@@ -2921,10 +2921,10 @@ s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2921 mpsar_hi = 0; 2921 mpsar_hi = 0;
2922 } 2922 }
2923 } else if (vmdq < 32) { 2923 } else if (vmdq < 32) {
2924 mpsar_lo &= ~(1 << vmdq); 2924 mpsar_lo &= ~BIT(vmdq);
2925 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2925 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2926 } else { 2926 } else {
2927 mpsar_hi &= ~(1 << (vmdq - 32)); 2927 mpsar_hi &= ~BIT(vmdq - 32);
2928 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2928 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2929 } 2929 }
2930 2930
@@ -2953,11 +2953,11 @@ s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2953 2953
2954 if (vmdq < 32) { 2954 if (vmdq < 32) {
2955 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2955 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2956 mpsar |= 1 << vmdq; 2956 mpsar |= BIT(vmdq);
2957 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 2957 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2958 } else { 2958 } else {
2959 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2959 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2960 mpsar |= 1 << (vmdq - 32); 2960 mpsar |= BIT(vmdq - 32);
2961 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 2961 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2962 } 2962 }
2963 return 0; 2963 return 0;
@@ -2978,11 +2978,11 @@ s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2978 u32 rar = hw->mac.san_mac_rar_index; 2978 u32 rar = hw->mac.san_mac_rar_index;
2979 2979
2980 if (vmdq < 32) { 2980 if (vmdq < 32) {
2981 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 2981 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq));
2982 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2982 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2983 } else { 2983 } else {
2984 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2984 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2985 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 2985 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32));
2986 } 2986 }
2987 2987
2988 return 0; 2988 return 0;
@@ -3082,7 +3082,7 @@ s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3082 * bits[4-0]: which bit in the register 3082 * bits[4-0]: which bit in the register
3083 */ 3083 */
3084 regidx = vlan / 32; 3084 regidx = vlan / 32;
3085 vfta_delta = 1 << (vlan % 32); 3085 vfta_delta = BIT(vlan % 32);
3086 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3086 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3087 3087
3088 /* vfta_delta represents the difference between the current value 3088 /* vfta_delta represents the difference between the current value
@@ -3113,12 +3113,12 @@ s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3113 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 3113 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
3114 3114
3115 /* set the pool bit */ 3115 /* set the pool bit */
3116 bits |= 1 << (vind % 32); 3116 bits |= BIT(vind % 32);
3117 if (vlan_on) 3117 if (vlan_on)
3118 goto vlvf_update; 3118 goto vlvf_update;
3119 3119
3120 /* clear the pool bit */ 3120 /* clear the pool bit */
3121 bits ^= 1 << (vind % 32); 3121 bits ^= BIT(vind % 32);
3122 3122
3123 if (!bits && 3123 if (!bits &&
3124 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 3124 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
@@ -3310,43 +3310,25 @@ wwn_prefix_err:
3310/** 3310/**
3311 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3311 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3312 * @hw: pointer to hardware structure 3312 * @hw: pointer to hardware structure
3313 * @enable: enable or disable switch for anti-spoofing 3313 * @enable: enable or disable switch for MAC anti-spoofing
3314 * @pf: Physical Function pool - do not enable anti-spoofing for the PF 3314 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
3315 * 3315 *
3316 **/ 3316 **/
3317void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) 3317void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3318{ 3318{
3319 int j; 3319 int vf_target_reg = vf >> 3;
3320 int pf_target_reg = pf >> 3; 3320 int vf_target_shift = vf % 8;
3321 int pf_target_shift = pf % 8; 3321 u32 pfvfspoof;
3322 u32 pfvfspoof = 0;
3323 3322
3324 if (hw->mac.type == ixgbe_mac_82598EB) 3323 if (hw->mac.type == ixgbe_mac_82598EB)
3325 return; 3324 return;
3326 3325
3326 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3327 if (enable) 3327 if (enable)
3328 pfvfspoof = IXGBE_SPOOF_MACAS_MASK; 3328 pfvfspoof |= BIT(vf_target_shift);
3329 3329 else
3330 /* 3330 pfvfspoof &= ~BIT(vf_target_shift);
3331 * PFVFSPOOF register array is size 8 with 8 bits assigned to 3331 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3332 * MAC anti-spoof enables in each register array element.
3333 */
3334 for (j = 0; j < pf_target_reg; j++)
3335 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3336
3337 /*
3338 * The PF should be allowed to spoof so that it can support
3339 * emulation mode NICs. Do not set the bits assigned to the PF
3340 */
3341 pfvfspoof &= (1 << pf_target_shift) - 1;
3342 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3343
3344 /*
3345 * Remaining pools belong to the PF so they do not need to have
3346 * anti-spoofing enabled.
3347 */
3348 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3349 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
3350} 3332}
3351 3333
3352/** 3334/**
@@ -3367,9 +3349,9 @@ void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3367 3349
3368 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3350 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3369 if (enable) 3351 if (enable)
3370 pfvfspoof |= (1 << vf_target_shift); 3352 pfvfspoof |= BIT(vf_target_shift);
3371 else 3353 else
3372 pfvfspoof &= ~(1 << vf_target_shift); 3354 pfvfspoof &= ~BIT(vf_target_shift);
3373 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3355 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3374} 3356}
3375 3357
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
index 6f8e6a56e242..6d4c260d0cbd 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
@@ -106,7 +106,7 @@ s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);
106 106
107s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index); 107s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
108s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index); 108s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
109void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf); 109void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
110void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf); 110void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
111s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps); 111s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
112s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 112s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c
index f8fb2acc2632..072ef3b5fc61 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c
@@ -186,7 +186,7 @@ void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en)
186 186
187 for (*pfc_en = 0, tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) { 187 for (*pfc_en = 0, tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) {
188 if (tc_config[tc].dcb_pfc != pfc_disabled) 188 if (tc_config[tc].dcb_pfc != pfc_disabled)
189 *pfc_en |= 1 << tc; 189 *pfc_en |= BIT(tc);
190 } 190 }
191} 191}
192 192
@@ -232,7 +232,7 @@ void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *cfg, int direction,
232u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up) 232u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
233{ 233{
234 struct tc_configuration *tc_config = &cfg->tc_config[0]; 234 struct tc_configuration *tc_config = &cfg->tc_config[0];
235 u8 prio_mask = 1 << up; 235 u8 prio_mask = BIT(up);
236 u8 tc = cfg->num_tcs.pg_tcs; 236 u8 tc = cfg->num_tcs.pg_tcs;
237 237
238 /* If tc is 0 then DCB is likely not enabled or supported */ 238 /* If tc is 0 then DCB is likely not enabled or supported */
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c
index d3ba63f9ad37..b79e93a5b699 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c
@@ -210,7 +210,7 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
210 210
211 /* Configure PFC Tx thresholds per TC */ 211 /* Configure PFC Tx thresholds per TC */
212 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 212 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
213 if (!(pfc_en & (1 << i))) { 213 if (!(pfc_en & BIT(i))) {
214 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 214 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
215 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 215 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
216 continue; 216 continue;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
index b5cc989a3d23..1011d644978f 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
@@ -248,7 +248,7 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
248 int enabled = 0; 248 int enabled = 0;
249 249
250 for (j = 0; j < MAX_USER_PRIORITY; j++) { 250 for (j = 0; j < MAX_USER_PRIORITY; j++) {
251 if ((prio_tc[j] == i) && (pfc_en & (1 << j))) { 251 if ((prio_tc[j] == i) && (pfc_en & BIT(j))) {
252 enabled = 1; 252 enabled = 1;
253 break; 253 break;
254 } 254 }
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c
index 2707bda37418..b8fc3cfec831 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c
@@ -62,7 +62,7 @@ static int ixgbe_copy_dcb_cfg(struct ixgbe_adapter *adapter, int tc_max)
62 }; 62 };
63 u8 up = dcb_getapp(adapter->netdev, &app); 63 u8 up = dcb_getapp(adapter->netdev, &app);
64 64
65 if (up && !(up & (1 << adapter->fcoe.up))) 65 if (up && !(up & BIT(adapter->fcoe.up)))
66 changes |= BIT_APP_UPCHG; 66 changes |= BIT_APP_UPCHG;
67#endif 67#endif
68 68
@@ -657,7 +657,7 @@ static int ixgbe_dcbnl_ieee_setapp(struct net_device *dev,
657 app->protocol == ETH_P_FCOE) { 657 app->protocol == ETH_P_FCOE) {
658 u8 app_mask = dcb_ieee_getapp_mask(dev, app); 658 u8 app_mask = dcb_ieee_getapp_mask(dev, app);
659 659
660 if (app_mask & (1 << adapter->fcoe.up)) 660 if (app_mask & BIT(adapter->fcoe.up))
661 return 0; 661 return 0;
662 662
663 adapter->fcoe.up = app->priority; 663 adapter->fcoe.up = app->priority;
@@ -700,7 +700,7 @@ static int ixgbe_dcbnl_ieee_delapp(struct net_device *dev,
700 app->protocol == ETH_P_FCOE) { 700 app->protocol == ETH_P_FCOE) {
701 u8 app_mask = dcb_ieee_getapp_mask(dev, app); 701 u8 app_mask = dcb_ieee_getapp_mask(dev, app);
702 702
703 if (app_mask & (1 << adapter->fcoe.up)) 703 if (app_mask & BIT(adapter->fcoe.up))
704 return 0; 704 return 0;
705 705
706 adapter->fcoe.up = app_mask ? 706 adapter->fcoe.up = app_mask ?
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
index 9f76be1431b1..d3efcb4fecce 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
@@ -1586,7 +1586,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1586 /* Test each interrupt */ 1586 /* Test each interrupt */
1587 for (; i < 10; i++) { 1587 for (; i < 10; i++) {
1588 /* Interrupt to test */ 1588 /* Interrupt to test */
1589 mask = 1 << i; 1589 mask = BIT(i);
1590 1590
1591 if (!shared_int) { 1591 if (!shared_int) {
1592 /* 1592 /*
@@ -3014,14 +3014,14 @@ static int ixgbe_get_ts_info(struct net_device *dev,
3014 info->phc_index = -1; 3014 info->phc_index = -1;
3015 3015
3016 info->tx_types = 3016 info->tx_types =
3017 (1 << HWTSTAMP_TX_OFF) | 3017 BIT(HWTSTAMP_TX_OFF) |
3018 (1 << HWTSTAMP_TX_ON); 3018 BIT(HWTSTAMP_TX_ON);
3019 3019
3020 info->rx_filters = 3020 info->rx_filters =
3021 (1 << HWTSTAMP_FILTER_NONE) | 3021 BIT(HWTSTAMP_FILTER_NONE) |
3022 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 3022 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3023 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 3023 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3024 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 3024 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
3025 break; 3025 break;
3026 default: 3026 default:
3027 return ethtool_op_get_ts_info(dev, info); 3027 return ethtool_op_get_ts_info(dev, info);
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index b2f2cf40f06a..0ef4a15bb23e 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -371,6 +371,27 @@ u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
371 371
372 if (ixgbe_removed(reg_addr)) 372 if (ixgbe_removed(reg_addr))
373 return IXGBE_FAILED_READ_REG; 373 return IXGBE_FAILED_READ_REG;
374 if (unlikely(hw->phy.nw_mng_if_sel &
375 IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M)) {
376 struct ixgbe_adapter *adapter;
377 int i;
378
379 for (i = 0; i < 200; ++i) {
380 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
381 if (likely(!value))
382 goto writes_completed;
383 if (value == IXGBE_FAILED_READ_REG) {
384 ixgbe_remove_adapter(hw);
385 return IXGBE_FAILED_READ_REG;
386 }
387 udelay(5);
388 }
389
390 adapter = hw->back;
391 e_warn(hw, "register writes incomplete %08x\n", value);
392 }
393
394writes_completed:
374 value = readl(reg_addr + reg); 395 value = readl(reg_addr + reg);
375 if (unlikely(value == IXGBE_FAILED_READ_REG)) 396 if (unlikely(value == IXGBE_FAILED_READ_REG))
376 ixgbe_check_remove(hw, reg); 397 ixgbe_check_remove(hw, reg);
@@ -2224,7 +2245,7 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2224 2245
2225 /* Populate MSIX to EITR Select */ 2246 /* Populate MSIX to EITR Select */
2226 if (adapter->num_vfs > 32) { 2247 if (adapter->num_vfs > 32) {
2227 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; 2248 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
2228 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2249 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2229 } 2250 }
2230 2251
@@ -2863,7 +2884,7 @@ int ixgbe_poll(struct napi_struct *napi, int budget)
2863 if (adapter->rx_itr_setting & 1) 2884 if (adapter->rx_itr_setting & 1)
2864 ixgbe_set_itr(q_vector); 2885 ixgbe_set_itr(q_vector);
2865 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2886 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2866 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); 2887 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx));
2867 2888
2868 return 0; 2889 return 0;
2869} 2890}
@@ -3156,15 +3177,15 @@ void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3156 * currently 40. 3177 * currently 40.
3157 */ 3178 */
3158 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3179 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3159 txdctl |= (1 << 16); /* WTHRESH = 1 */ 3180 txdctl |= 1u << 16; /* WTHRESH = 1 */
3160 else 3181 else
3161 txdctl |= (8 << 16); /* WTHRESH = 8 */ 3182 txdctl |= 8u << 16; /* WTHRESH = 8 */
3162 3183
3163 /* 3184 /*
3164 * Setting PTHRESH to 32 both improves performance 3185 * Setting PTHRESH to 32 both improves performance
3165 * and avoids a TX hang with DFP enabled 3186 * and avoids a TX hang with DFP enabled
3166 */ 3187 */
3167 txdctl |= (1 << 8) | /* HTHRESH = 1 */ 3188 txdctl |= (1u << 8) | /* HTHRESH = 1 */
3168 32; /* PTHRESH = 32 */ 3189 32; /* PTHRESH = 32 */
3169 3190
3170 /* reinitialize flowdirector state */ 3191 /* reinitialize flowdirector state */
@@ -3716,9 +3737,9 @@ static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3716 return; 3737 return;
3717 3738
3718 if (rss_i > 3) 3739 if (rss_i > 3)
3719 psrtype |= 2 << 29; 3740 psrtype |= 2u << 29;
3720 else if (rss_i > 1) 3741 else if (rss_i > 1)
3721 psrtype |= 1 << 29; 3742 psrtype |= 1u << 29;
3722 3743
3723 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 3744 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3724 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 3745 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
@@ -3745,9 +3766,9 @@ static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3745 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 3766 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3746 3767
3747 /* Enable only the PF's pool for Tx/Rx */ 3768 /* Enable only the PF's pool for Tx/Rx */
3748 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); 3769 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(vf_shift, 31));
3749 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 3770 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3750 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); 3771 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(vf_shift, 31));
3751 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 3772 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3752 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 3773 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
3753 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 3774 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
@@ -3776,34 +3797,10 @@ static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3776 3797
3777 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3798 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3778 3799
3779
3780 /* Enable MAC Anti-Spoofing */
3781 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3782 adapter->num_vfs);
3783
3784 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
3785 * calling set_ethertype_anti_spoofing for each VF in loop below
3786 */
3787 if (hw->mac.ops.set_ethertype_anti_spoofing) {
3788 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3789 (IXGBE_ETQF_FILTER_EN |
3790 IXGBE_ETQF_TX_ANTISPOOF |
3791 IXGBE_ETH_P_LLDP));
3792
3793 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3794 (IXGBE_ETQF_FILTER_EN |
3795 IXGBE_ETQF_TX_ANTISPOOF |
3796 ETH_P_PAUSE));
3797 }
3798
3799 /* For VFs that have spoof checking turned off */
3800 for (i = 0; i < adapter->num_vfs; i++) { 3800 for (i = 0; i < adapter->num_vfs; i++) {
3801 if (!adapter->vfinfo[i].spoofchk_enabled) 3801 /* configure spoof checking */
3802 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); 3802 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
3803 3803 adapter->vfinfo[i].spoofchk_enabled);
3804 /* enable ethertype anti spoofing if hw supports it */
3805 if (hw->mac.ops.set_ethertype_anti_spoofing)
3806 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
3807 3804
3808 /* Enable/Disable RSS query feature */ 3805 /* Enable/Disable RSS query feature */
3809 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 3806 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
@@ -3997,7 +3994,7 @@ void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3997 * entry other than the PF. 3994 * entry other than the PF.
3998 */ 3995 */
3999 word = idx * 2 + (VMDQ_P(0) / 32); 3996 word = idx * 2 + (VMDQ_P(0) / 32);
4000 bits = ~(1 << (VMDQ_P(0)) % 32); 3997 bits = ~BIT(VMDQ_P(0) % 32);
4001 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 3998 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4002 3999
4003 /* Disable the filter so this falls into the default pool. */ 4000 /* Disable the filter so this falls into the default pool. */
@@ -4132,7 +4129,7 @@ static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4132 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4129 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4133 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4130 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4134 4131
4135 vlvfb |= 1 << (VMDQ_P(0) % 32); 4132 vlvfb |= BIT(VMDQ_P(0) % 32);
4136 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4133 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4137 } 4134 }
4138 4135
@@ -4162,7 +4159,7 @@ static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4162 4159
4163 if (vlvf) { 4160 if (vlvf) {
4164 /* record VLAN ID in VFTA */ 4161 /* record VLAN ID in VFTA */
4165 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32); 4162 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4166 4163
4167 /* if PF is part of this then continue */ 4164 /* if PF is part of this then continue */
4168 if (test_bit(vid, adapter->active_vlans)) 4165 if (test_bit(vid, adapter->active_vlans))
@@ -4171,7 +4168,7 @@ static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4171 4168
4172 /* remove PF from the pool */ 4169 /* remove PF from the pool */
4173 word = i * 2 + VMDQ_P(0) / 32; 4170 word = i * 2 + VMDQ_P(0) / 32;
4174 bits = ~(1 << (VMDQ_P(0) % 32)); 4171 bits = ~BIT(VMDQ_P(0) % 32);
4175 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4172 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4176 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4173 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4177 } 4174 }
@@ -4865,9 +4862,9 @@ static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4865 return; 4862 return;
4866 4863
4867 if (rss_i > 3) 4864 if (rss_i > 3)
4868 psrtype |= 2 << 29; 4865 psrtype |= 2u << 29;
4869 else if (rss_i > 1) 4866 else if (rss_i > 1)
4870 psrtype |= 1 << 29; 4867 psrtype |= 1u << 29;
4871 4868
4872 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4869 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4873} 4870}
@@ -4931,7 +4928,7 @@ static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4931 /* shutdown specific queue receive and wait for dma to settle */ 4928 /* shutdown specific queue receive and wait for dma to settle */
4932 ixgbe_disable_rx_queue(adapter, rx_ring); 4929 ixgbe_disable_rx_queue(adapter, rx_ring);
4933 usleep_range(10000, 20000); 4930 usleep_range(10000, 20000);
4934 ixgbe_irq_disable_queues(adapter, ((u64)1 << index)); 4931 ixgbe_irq_disable_queues(adapter, BIT_ULL(index));
4935 ixgbe_clean_rx_ring(rx_ring); 4932 ixgbe_clean_rx_ring(rx_ring);
4936 rx_ring->l2_accel_priv = NULL; 4933 rx_ring->l2_accel_priv = NULL;
4937} 4934}
@@ -5575,6 +5572,7 @@ static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5575 struct pci_dev *pdev = adapter->pdev; 5572 struct pci_dev *pdev = adapter->pdev;
5576 unsigned int rss, fdir; 5573 unsigned int rss, fdir;
5577 u32 fwsm; 5574 u32 fwsm;
5575 u16 device_caps;
5578#ifdef CONFIG_IXGBE_DCB 5576#ifdef CONFIG_IXGBE_DCB
5579 int j; 5577 int j;
5580 struct tc_configuration *tc; 5578 struct tc_configuration *tc;
@@ -5740,6 +5738,22 @@ static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5740 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 5738 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5741 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 5739 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5742 5740
5741 /* Cache bit indicating need for crosstalk fix */
5742 switch (hw->mac.type) {
5743 case ixgbe_mac_82599EB:
5744 case ixgbe_mac_X550EM_x:
5745 case ixgbe_mac_x550em_a:
5746 hw->mac.ops.get_device_caps(hw, &device_caps);
5747 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
5748 adapter->need_crosstalk_fix = false;
5749 else
5750 adapter->need_crosstalk_fix = true;
5751 break;
5752 default:
5753 adapter->need_crosstalk_fix = false;
5754 break;
5755 }
5756
5743 /* set default work limits */ 5757 /* set default work limits */
5744 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 5758 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5745 5759
@@ -6631,7 +6645,7 @@ static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6631 for (i = 0; i < adapter->num_q_vectors; i++) { 6645 for (i = 0; i < adapter->num_q_vectors; i++) {
6632 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 6646 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6633 if (qv->rx.ring || qv->tx.ring) 6647 if (qv->rx.ring || qv->tx.ring)
6634 eics |= ((u64)1 << i); 6648 eics |= BIT_ULL(i);
6635 } 6649 }
6636 } 6650 }
6637 6651
@@ -6662,6 +6676,18 @@ static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6662 link_up = true; 6676 link_up = true;
6663 } 6677 }
6664 6678
6679 /* If Crosstalk fix enabled do the sanity check of making sure
6680 * the SFP+ cage is empty.
6681 */
6682 if (adapter->need_crosstalk_fix) {
6683 u32 sfp_cage_full;
6684
6685 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
6686 IXGBE_ESDP_SDP2;
6687 if (ixgbe_is_sfp(hw) && link_up && !sfp_cage_full)
6688 link_up = false;
6689 }
6690
6665 if (adapter->ixgbe_ieee_pfc) 6691 if (adapter->ixgbe_ieee_pfc)
6666 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 6692 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6667 6693
@@ -7008,6 +7034,16 @@ static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
7008 struct ixgbe_hw *hw = &adapter->hw; 7034 struct ixgbe_hw *hw = &adapter->hw;
7009 s32 err; 7035 s32 err;
7010 7036
7037 /* If crosstalk fix enabled verify the SFP+ cage is full */
7038 if (adapter->need_crosstalk_fix) {
7039 u32 sfp_cage_full;
7040
7041 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
7042 IXGBE_ESDP_SDP2;
7043 if (!sfp_cage_full)
7044 return;
7045 }
7046
7011 /* not searching for SFP so there is nothing to do here */ 7047 /* not searching for SFP so there is nothing to do here */
7012 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7048 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7013 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7049 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
@@ -7220,9 +7256,18 @@ static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7220 struct ixgbe_tx_buffer *first, 7256 struct ixgbe_tx_buffer *first,
7221 u8 *hdr_len) 7257 u8 *hdr_len)
7222{ 7258{
7259 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7223 struct sk_buff *skb = first->skb; 7260 struct sk_buff *skb = first->skb;
7224 u32 vlan_macip_lens, type_tucmd; 7261 union {
7225 u32 mss_l4len_idx, l4len; 7262 struct iphdr *v4;
7263 struct ipv6hdr *v6;
7264 unsigned char *hdr;
7265 } ip;
7266 union {
7267 struct tcphdr *tcp;
7268 unsigned char *hdr;
7269 } l4;
7270 u32 paylen, l4_offset;
7226 int err; 7271 int err;
7227 7272
7228 if (skb->ip_summed != CHECKSUM_PARTIAL) 7273 if (skb->ip_summed != CHECKSUM_PARTIAL)
@@ -7235,46 +7280,52 @@ static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7235 if (err < 0) 7280 if (err < 0)
7236 return err; 7281 return err;
7237 7282
7283 ip.hdr = skb_network_header(skb);
7284 l4.hdr = skb_checksum_start(skb);
7285
7238 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7286 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7239 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7287 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7240 7288
7241 if (first->protocol == htons(ETH_P_IP)) { 7289 /* initialize outer IP header fields */
7242 struct iphdr *iph = ip_hdr(skb); 7290 if (ip.v4->version == 4) {
7243 iph->tot_len = 0; 7291 /* IP header will have to cancel out any data that
7244 iph->check = 0; 7292 * is not a part of the outer IP header
7245 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 7293 */
7246 iph->daddr, 0, 7294 ip.v4->check = csum_fold(csum_add(lco_csum(skb),
7247 IPPROTO_TCP, 7295 csum_unfold(l4.tcp->check)));
7248 0);
7249 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7296 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7297
7298 ip.v4->tot_len = 0;
7250 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7299 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7251 IXGBE_TX_FLAGS_CSUM | 7300 IXGBE_TX_FLAGS_CSUM |
7252 IXGBE_TX_FLAGS_IPV4; 7301 IXGBE_TX_FLAGS_IPV4;
7253 } else if (skb_is_gso_v6(skb)) { 7302 } else {
7254 ipv6_hdr(skb)->payload_len = 0; 7303 ip.v6->payload_len = 0;
7255 tcp_hdr(skb)->check =
7256 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7257 &ipv6_hdr(skb)->daddr,
7258 0, IPPROTO_TCP, 0);
7259 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7304 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7260 IXGBE_TX_FLAGS_CSUM; 7305 IXGBE_TX_FLAGS_CSUM;
7261 } 7306 }
7262 7307
7263 /* compute header lengths */ 7308 /* determine offset of inner transport header */
7264 l4len = tcp_hdrlen(skb); 7309 l4_offset = l4.hdr - skb->data;
7265 *hdr_len = skb_transport_offset(skb) + l4len; 7310
7311 /* compute length of segmentation header */
7312 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
7313
7314 /* remove payload length from inner checksum */
7315 paylen = skb->len - l4_offset;
7316 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
7266 7317
7267 /* update gso size and bytecount with header size */ 7318 /* update gso size and bytecount with header size */
7268 first->gso_segs = skb_shinfo(skb)->gso_segs; 7319 first->gso_segs = skb_shinfo(skb)->gso_segs;
7269 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7320 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7270 7321
7271 /* mss_l4len_id: use 0 as index for TSO */ 7322 /* mss_l4len_id: use 0 as index for TSO */
7272 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; 7323 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
7273 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7324 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
7274 7325
7275 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7326 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7276 vlan_macip_lens = skb_network_header_len(skb); 7327 vlan_macip_lens = l4.hdr - ip.hdr;
7277 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7328 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
7278 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7329 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7279 7330
7280 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 7331 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
@@ -8862,17 +8913,36 @@ static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8862 kfree(fwd_adapter); 8913 kfree(fwd_adapter);
8863} 8914}
8864 8915
8865#define IXGBE_MAX_TUNNEL_HDR_LEN 80 8916#define IXGBE_MAX_MAC_HDR_LEN 127
8917#define IXGBE_MAX_NETWORK_HDR_LEN 511
8918
8866static netdev_features_t 8919static netdev_features_t
8867ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 8920ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8868 netdev_features_t features) 8921 netdev_features_t features)
8869{ 8922{
8870 if (!skb->encapsulation) 8923 unsigned int network_hdr_len, mac_hdr_len;
8871 return features; 8924
8872 8925 /* Make certain the headers can be described by a context descriptor */
8873 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) > 8926 mac_hdr_len = skb_network_header(skb) - skb->data;
8874 IXGBE_MAX_TUNNEL_HDR_LEN)) 8927 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
8875 return features & ~NETIF_F_CSUM_MASK; 8928 return features & ~(NETIF_F_HW_CSUM |
8929 NETIF_F_SCTP_CRC |
8930 NETIF_F_HW_VLAN_CTAG_TX |
8931 NETIF_F_TSO |
8932 NETIF_F_TSO6);
8933
8934 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
8935 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
8936 return features & ~(NETIF_F_HW_CSUM |
8937 NETIF_F_SCTP_CRC |
8938 NETIF_F_TSO |
8939 NETIF_F_TSO6);
8940
8941 /* We can only support IPV4 TSO in tunnels if we can mangle the
8942 * inner IP ID field, so strip TSO if MANGLEID is not supported.
8943 */
8944 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
8945 features &= ~NETIF_F_TSO;
8876 8946
8877 return features; 8947 return features;
8878} 8948}
@@ -9156,7 +9226,7 @@ static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9156 goto err_ioremap; 9226 goto err_ioremap;
9157 } 9227 }
9158 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 9228 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
9159 if (!(eec & (1 << 8))) 9229 if (!(eec & BIT(8)))
9160 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 9230 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
9161 9231
9162 /* PHY */ 9232 /* PHY */
@@ -9239,31 +9309,44 @@ skip_sriov:
9239 NETIF_F_TSO6 | 9309 NETIF_F_TSO6 |
9240 NETIF_F_RXHASH | 9310 NETIF_F_RXHASH |
9241 NETIF_F_RXCSUM | 9311 NETIF_F_RXCSUM |
9242 NETIF_F_HW_CSUM | 9312 NETIF_F_HW_CSUM;
9243 NETIF_F_HW_VLAN_CTAG_TX | 9313
9244 NETIF_F_HW_VLAN_CTAG_RX | 9314#define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
9245 NETIF_F_HW_VLAN_CTAG_FILTER; 9315 NETIF_F_GSO_GRE_CSUM | \
9316 NETIF_F_GSO_IPIP | \
9317 NETIF_F_GSO_SIT | \
9318 NETIF_F_GSO_UDP_TUNNEL | \
9319 NETIF_F_GSO_UDP_TUNNEL_CSUM)
9320
9321 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
9322 netdev->features |= NETIF_F_GSO_PARTIAL |
9323 IXGBE_GSO_PARTIAL_FEATURES;
9246 9324
9247 if (hw->mac.type >= ixgbe_mac_82599EB) 9325 if (hw->mac.type >= ixgbe_mac_82599EB)
9248 netdev->features |= NETIF_F_SCTP_CRC; 9326 netdev->features |= NETIF_F_SCTP_CRC;
9249 9327
9250 /* copy netdev features into list of user selectable features */ 9328 /* copy netdev features into list of user selectable features */
9251 netdev->hw_features |= netdev->features; 9329 netdev->hw_features |= netdev->features |
9252 netdev->hw_features |= NETIF_F_RXALL | 9330 NETIF_F_HW_VLAN_CTAG_RX |
9331 NETIF_F_HW_VLAN_CTAG_TX |
9332 NETIF_F_RXALL |
9253 NETIF_F_HW_L2FW_DOFFLOAD; 9333 NETIF_F_HW_L2FW_DOFFLOAD;
9254 9334
9255 if (hw->mac.type >= ixgbe_mac_82599EB) 9335 if (hw->mac.type >= ixgbe_mac_82599EB)
9256 netdev->hw_features |= NETIF_F_NTUPLE | 9336 netdev->hw_features |= NETIF_F_NTUPLE |
9257 NETIF_F_HW_TC; 9337 NETIF_F_HW_TC;
9258 9338
9259 netdev->vlan_features |= NETIF_F_SG | 9339 if (pci_using_dac)
9260 NETIF_F_TSO | 9340 netdev->features |= NETIF_F_HIGHDMA;
9261 NETIF_F_TSO6 | 9341
9262 NETIF_F_HW_CSUM | 9342 /* set this bit last since it cannot be part of vlan_features */
9263 NETIF_F_SCTP_CRC; 9343 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
9344 NETIF_F_HW_VLAN_CTAG_RX |
9345 NETIF_F_HW_VLAN_CTAG_TX;
9264 9346
9347 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
9348 netdev->hw_enc_features |= netdev->vlan_features;
9265 netdev->mpls_features |= NETIF_F_HW_CSUM; 9349 netdev->mpls_features |= NETIF_F_HW_CSUM;
9266 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
9267 9350
9268 netdev->priv_flags |= IFF_UNICAST_FLT; 9351 netdev->priv_flags |= IFF_UNICAST_FLT;
9269 netdev->priv_flags |= IFF_SUPP_NOFCS; 9352 netdev->priv_flags |= IFF_SUPP_NOFCS;
@@ -9294,10 +9377,6 @@ skip_sriov:
9294 NETIF_F_FCOE_MTU; 9377 NETIF_F_FCOE_MTU;
9295 } 9378 }
9296#endif /* IXGBE_FCOE */ 9379#endif /* IXGBE_FCOE */
9297 if (pci_using_dac) {
9298 netdev->features |= NETIF_F_HIGHDMA;
9299 netdev->vlan_features |= NETIF_F_HIGHDMA;
9300 }
9301 9380
9302 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 9381 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9303 netdev->hw_features |= NETIF_F_LRO; 9382 netdev->hw_features |= NETIF_F_LRO;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c
index b2125e358f7b..a0cb84381cd0 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c
@@ -314,8 +314,8 @@ static s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)
314 break; 314 break;
315 } 315 }
316 316
317 if (vflre & (1 << vf_shift)) { 317 if (vflre & BIT(vf_shift)) {
318 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift)); 318 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), BIT(vf_shift));
319 hw->mbx.stats.rsts++; 319 hw->mbx.stats.rsts++;
320 return 0; 320 return 0;
321 } 321 }
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
index cdf4c3800801..cc735ec3e045 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
@@ -107,7 +107,7 @@
107#define IXGBE_PE 0xE0 /* Port expander addr */ 107#define IXGBE_PE 0xE0 /* Port expander addr */
108#define IXGBE_PE_OUTPUT 1 /* Output reg offset */ 108#define IXGBE_PE_OUTPUT 1 /* Output reg offset */
109#define IXGBE_PE_CONFIG 3 /* Config reg offset */ 109#define IXGBE_PE_CONFIG 3 /* Config reg offset */
110#define IXGBE_PE_BIT1 (1 << 1) 110#define IXGBE_PE_BIT1 BIT(1)
111 111
112/* Flow control defines */ 112/* Flow control defines */
113#define IXGBE_TAF_SYM_PAUSE 0x400 113#define IXGBE_TAF_SYM_PAUSE 0x400
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
index bdc8fdcc07a5..e5431bfe3339 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
@@ -396,7 +396,7 @@ static int ixgbe_ptp_adjfreq_82599(struct ptp_clock_info *ptp, s32 ppb)
396 if (incval > 0x00FFFFFFULL) 396 if (incval > 0x00FFFFFFULL)
397 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n"); 397 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
398 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 398 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
399 (1 << IXGBE_INCPER_SHIFT_82599) | 399 BIT(IXGBE_INCPER_SHIFT_82599) |
400 ((u32)incval & 0x00FFFFFFUL)); 400 ((u32)incval & 0x00FFFFFFUL));
401 break; 401 break;
402 default: 402 default:
@@ -1114,7 +1114,7 @@ void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
1114 incval >>= IXGBE_INCVAL_SHIFT_82599; 1114 incval >>= IXGBE_INCVAL_SHIFT_82599;
1115 cc.shift -= IXGBE_INCVAL_SHIFT_82599; 1115 cc.shift -= IXGBE_INCVAL_SHIFT_82599;
1116 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 1116 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
1117 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 1117 BIT(IXGBE_INCPER_SHIFT_82599) | incval);
1118 break; 1118 break;
1119 default: 1119 default:
1120 /* other devices aren't supported */ 1120 /* other devices aren't supported */
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
index adcf00002483..c5caacdd193d 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
@@ -406,7 +406,7 @@ static int ixgbe_set_vf_multicasts(struct ixgbe_adapter *adapter,
406 vector_reg = (vfinfo->vf_mc_hashes[i] >> 5) & 0x7F; 406 vector_reg = (vfinfo->vf_mc_hashes[i] >> 5) & 0x7F;
407 vector_bit = vfinfo->vf_mc_hashes[i] & 0x1F; 407 vector_bit = vfinfo->vf_mc_hashes[i] & 0x1F;
408 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 408 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
409 mta_reg |= (1 << vector_bit); 409 mta_reg |= BIT(vector_bit);
410 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 410 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
411 } 411 }
412 vmolr |= IXGBE_VMOLR_ROMPE; 412 vmolr |= IXGBE_VMOLR_ROMPE;
@@ -433,7 +433,7 @@ void ixgbe_restore_vf_multicasts(struct ixgbe_adapter *adapter)
433 vector_reg = (vfinfo->vf_mc_hashes[j] >> 5) & 0x7F; 433 vector_reg = (vfinfo->vf_mc_hashes[j] >> 5) & 0x7F;
434 vector_bit = vfinfo->vf_mc_hashes[j] & 0x1F; 434 vector_bit = vfinfo->vf_mc_hashes[j] & 0x1F;
435 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 435 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
436 mta_reg |= (1 << vector_bit); 436 mta_reg |= BIT(vector_bit);
437 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 437 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
438 } 438 }
439 439
@@ -536,9 +536,9 @@ static s32 ixgbe_set_vf_lpe(struct ixgbe_adapter *adapter, u32 *msgbuf, u32 vf)
536 /* enable or disable receive depending on error */ 536 /* enable or disable receive depending on error */
537 vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); 537 vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
538 if (err) 538 if (err)
539 vfre &= ~(1 << vf_shift); 539 vfre &= ~BIT(vf_shift);
540 else 540 else
541 vfre |= 1 << vf_shift; 541 vfre |= BIT(vf_shift);
542 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), vfre); 542 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), vfre);
543 543
544 if (err) { 544 if (err) {
@@ -592,8 +592,8 @@ static void ixgbe_clear_vf_vlans(struct ixgbe_adapter *adapter, u32 vf)
592 u32 vlvfb_mask, pool_mask, i; 592 u32 vlvfb_mask, pool_mask, i;
593 593
594 /* create mask for VF and other pools */ 594 /* create mask for VF and other pools */
595 pool_mask = ~(1 << (VMDQ_P(0) % 32)); 595 pool_mask = ~BIT(VMDQ_P(0) % 32);
596 vlvfb_mask = 1 << (vf % 32); 596 vlvfb_mask = BIT(vf % 32);
597 597
598 /* post increment loop, covers VLVF_ENTRIES - 1 to 0 */ 598 /* post increment loop, covers VLVF_ENTRIES - 1 to 0 */
599 for (i = IXGBE_VLVF_ENTRIES; i--;) { 599 for (i = IXGBE_VLVF_ENTRIES; i--;) {
@@ -629,7 +629,7 @@ static void ixgbe_clear_vf_vlans(struct ixgbe_adapter *adapter, u32 vf)
629 goto update_vlvfb; 629 goto update_vlvfb;
630 630
631 vid = vlvf & VLAN_VID_MASK; 631 vid = vlvf & VLAN_VID_MASK;
632 mask = 1 << (vid % 32); 632 mask = BIT(vid % 32);
633 633
634 /* clear bit from VFTA */ 634 /* clear bit from VFTA */
635 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid / 32)); 635 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid / 32));
@@ -813,7 +813,7 @@ static int ixgbe_vf_reset_msg(struct ixgbe_adapter *adapter, u32 vf)
813 813
814 /* enable transmit for vf */ 814 /* enable transmit for vf */
815 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset)); 815 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
816 reg |= 1 << vf_shift; 816 reg |= BIT(vf_shift);
817 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg); 817 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
818 818
819 /* force drop enable for all VF Rx queues */ 819 /* force drop enable for all VF Rx queues */
@@ -821,7 +821,7 @@ static int ixgbe_vf_reset_msg(struct ixgbe_adapter *adapter, u32 vf)
821 821
822 /* enable receive for vf */ 822 /* enable receive for vf */
823 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); 823 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
824 reg |= 1 << vf_shift; 824 reg |= BIT(vf_shift);
825 /* 825 /*
826 * The 82599 cannot support a mix of jumbo and non-jumbo PF/VFs. 826 * The 82599 cannot support a mix of jumbo and non-jumbo PF/VFs.
827 * For more info take a look at ixgbe_set_vf_lpe 827 * For more info take a look at ixgbe_set_vf_lpe
@@ -837,7 +837,7 @@ static int ixgbe_vf_reset_msg(struct ixgbe_adapter *adapter, u32 vf)
837 837
838#endif /* CONFIG_FCOE */ 838#endif /* CONFIG_FCOE */
839 if (pf_max_frame > ETH_FRAME_LEN) 839 if (pf_max_frame > ETH_FRAME_LEN)
840 reg &= ~(1 << vf_shift); 840 reg &= ~BIT(vf_shift);
841 } 841 }
842 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg); 842 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
843 843
@@ -846,7 +846,7 @@ static int ixgbe_vf_reset_msg(struct ixgbe_adapter *adapter, u32 vf)
846 846
847 /* Enable counting of spoofed packets in the SSVPC register */ 847 /* Enable counting of spoofed packets in the SSVPC register */
848 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset)); 848 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
849 reg |= (1 << vf_shift); 849 reg |= BIT(vf_shift);
850 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg); 850 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
851 851
852 /* 852 /*
@@ -908,8 +908,6 @@ static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter,
908 u32 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >> IXGBE_VT_MSGINFO_SHIFT; 908 u32 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >> IXGBE_VT_MSGINFO_SHIFT;
909 u32 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK); 909 u32 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
910 u8 tcs = netdev_get_num_tc(adapter->netdev); 910 u8 tcs = netdev_get_num_tc(adapter->netdev);
911 struct ixgbe_hw *hw = &adapter->hw;
912 int err;
913 911
914 if (adapter->vfinfo[vf].pf_vlan || tcs) { 912 if (adapter->vfinfo[vf].pf_vlan || tcs) {
915 e_warn(drv, 913 e_warn(drv,
@@ -923,19 +921,7 @@ static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter,
923 if (!vid && !add) 921 if (!vid && !add)
924 return 0; 922 return 0;
925 923
926 err = ixgbe_set_vf_vlan(adapter, add, vid, vf); 924 return ixgbe_set_vf_vlan(adapter, add, vid, vf);
927 if (err)
928 return err;
929
930 if (adapter->vfinfo[vf].spoofchk_enabled)
931 hw->mac.ops.set_vlan_anti_spoofing(hw, true, vf);
932
933 if (add)
934 adapter->vfinfo[vf].vlan_count++;
935 else if (adapter->vfinfo[vf].vlan_count)
936 adapter->vfinfo[vf].vlan_count--;
937
938 return 0;
939} 925}
940 926
941static int ixgbe_set_vf_macvlan_msg(struct ixgbe_adapter *adapter, 927static int ixgbe_set_vf_macvlan_msg(struct ixgbe_adapter *adapter,
@@ -964,8 +950,11 @@ static int ixgbe_set_vf_macvlan_msg(struct ixgbe_adapter *adapter,
964 * If the VF is allowed to set MAC filters then turn off 950 * If the VF is allowed to set MAC filters then turn off
965 * anti-spoofing to avoid false positives. 951 * anti-spoofing to avoid false positives.
966 */ 952 */
967 if (adapter->vfinfo[vf].spoofchk_enabled) 953 if (adapter->vfinfo[vf].spoofchk_enabled) {
968 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, vf, false); 954 struct ixgbe_hw *hw = &adapter->hw;
955
956 hw->mac.ops.set_mac_anti_spoofing(hw, false, vf);
957 }
969 } 958 }
970 959
971 err = ixgbe_set_vf_macvlan(adapter, vf, index, new_mac); 960 err = ixgbe_set_vf_macvlan(adapter, vf, index, new_mac);
@@ -1321,9 +1310,6 @@ static int ixgbe_enable_port_vlan(struct ixgbe_adapter *adapter, int vf,
1321 1310
1322 ixgbe_set_vmvir(adapter, vlan, qos, vf); 1311 ixgbe_set_vmvir(adapter, vlan, qos, vf);
1323 ixgbe_set_vmolr(hw, vf, false); 1312 ixgbe_set_vmolr(hw, vf, false);
1324 if (adapter->vfinfo[vf].spoofchk_enabled)
1325 hw->mac.ops.set_vlan_anti_spoofing(hw, true, vf);
1326 adapter->vfinfo[vf].vlan_count++;
1327 1313
1328 /* enable hide vlan on X550 */ 1314 /* enable hide vlan on X550 */
1329 if (hw->mac.type >= ixgbe_mac_X550) 1315 if (hw->mac.type >= ixgbe_mac_X550)
@@ -1356,9 +1342,6 @@ static int ixgbe_disable_port_vlan(struct ixgbe_adapter *adapter, int vf)
1356 ixgbe_set_vf_vlan(adapter, true, 0, vf); 1342 ixgbe_set_vf_vlan(adapter, true, 0, vf);
1357 ixgbe_clear_vmvir(adapter, vf); 1343 ixgbe_clear_vmvir(adapter, vf);
1358 ixgbe_set_vmolr(hw, vf, true); 1344 ixgbe_set_vmolr(hw, vf, true);
1359 hw->mac.ops.set_vlan_anti_spoofing(hw, false, vf);
1360 if (adapter->vfinfo[vf].vlan_count)
1361 adapter->vfinfo[vf].vlan_count--;
1362 1345
1363 /* disable hide VLAN on X550 */ 1346 /* disable hide VLAN on X550 */
1364 if (hw->mac.type >= ixgbe_mac_X550) 1347 if (hw->mac.type >= ixgbe_mac_X550)
@@ -1525,27 +1508,34 @@ int ixgbe_ndo_set_vf_bw(struct net_device *netdev, int vf, int min_tx_rate,
1525int ixgbe_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, bool setting) 1508int ixgbe_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, bool setting)
1526{ 1509{
1527 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1510 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1528 int vf_target_reg = vf >> 3;
1529 int vf_target_shift = vf % 8;
1530 struct ixgbe_hw *hw = &adapter->hw; 1511 struct ixgbe_hw *hw = &adapter->hw;
1531 u32 regval;
1532 1512
1533 if (vf >= adapter->num_vfs) 1513 if (vf >= adapter->num_vfs)
1534 return -EINVAL; 1514 return -EINVAL;
1535 1515
1536 adapter->vfinfo[vf].spoofchk_enabled = setting; 1516 adapter->vfinfo[vf].spoofchk_enabled = setting;
1537 1517
1538 regval = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 1518 /* configure MAC spoofing */
1539 regval &= ~(1 << vf_target_shift); 1519 hw->mac.ops.set_mac_anti_spoofing(hw, setting, vf);
1540 regval |= (setting << vf_target_shift); 1520
1541 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), regval); 1521 /* configure VLAN spoofing */
1542 1522 hw->mac.ops.set_vlan_anti_spoofing(hw, setting, vf);
1543 if (adapter->vfinfo[vf].vlan_count) { 1523
1544 vf_target_shift += IXGBE_SPOOF_VLANAS_SHIFT; 1524 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
1545 regval = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 1525 * calling set_ethertype_anti_spoofing for each VF in loop below
1546 regval &= ~(1 << vf_target_shift); 1526 */
1547 regval |= (setting << vf_target_shift); 1527 if (hw->mac.ops.set_ethertype_anti_spoofing) {
1548 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), regval); 1528 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
1529 (IXGBE_ETQF_FILTER_EN |
1530 IXGBE_ETQF_TX_ANTISPOOF |
1531 IXGBE_ETH_P_LLDP));
1532
1533 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
1534 (IXGBE_ETQF_FILTER_EN |
1535 IXGBE_ETQF_TX_ANTISPOOF |
1536 ETH_P_PAUSE));
1537
1538 hw->mac.ops.set_ethertype_anti_spoofing(hw, setting, vf);
1549 } 1539 }
1550 1540
1551 return 0; 1541 return 0;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
index ba3b837c7e9d..7af451460374 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
@@ -697,16 +697,16 @@ struct ixgbe_thermal_sensor_data {
697#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 697#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
698#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */ 698#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
699#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) 699#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
700#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 700#define IXGBE_FCBUFF_VALID BIT(0) /* DMA Context Valid */
701#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 701#define IXGBE_FCBUFF_BUFFSIZE (3u << 3) /* User Buffer Size */
702#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 702#define IXGBE_FCBUFF_WRCONTX BIT(7) /* 0: Initiator, 1: Target */
703#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 703#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
704#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 704#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
705#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 705#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
706#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 706#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
707#define IXGBE_FCBUFF_OFFSET_SHIFT 16 707#define IXGBE_FCBUFF_OFFSET_SHIFT 16
708#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 708#define IXGBE_FCDMARW_WE BIT(14) /* Write enable */
709#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 709#define IXGBE_FCDMARW_RE BIT(15) /* Read enable */
710#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 710#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
711#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 711#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
712#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 712#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
@@ -723,23 +723,23 @@ struct ixgbe_thermal_sensor_data {
723#define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 723#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
724#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 724#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
725#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 725#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
726#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 726#define IXGBE_FCFLT_VALID BIT(0) /* Filter Context Valid */
727#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 727#define IXGBE_FCFLT_FIRST BIT(1) /* Filter First */
728#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 728#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
729#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 729#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
730#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 730#define IXGBE_FCFLTRW_RVALDT BIT(13) /* Fast Re-Validation */
731#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 731#define IXGBE_FCFLTRW_WE BIT(14) /* Write Enable */
732#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 732#define IXGBE_FCFLTRW_RE BIT(15) /* Read Enable */
733/* FCoE Receive Control */ 733/* FCoE Receive Control */
734#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 734#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
735#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 735#define IXGBE_FCRXCTRL_FCOELLI BIT(0) /* Low latency interrupt */
736#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 736#define IXGBE_FCRXCTRL_SAVBAD BIT(1) /* Save Bad Frames */
737#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 737#define IXGBE_FCRXCTRL_FRSTRDH BIT(2) /* EN 1st Read Header */
738#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 738#define IXGBE_FCRXCTRL_LASTSEQH BIT(3) /* EN Last Header in Seq */
739#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 739#define IXGBE_FCRXCTRL_ALLH BIT(4) /* EN All Headers */
740#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 740#define IXGBE_FCRXCTRL_FRSTSEQH BIT(5) /* EN 1st Seq. Header */
741#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 741#define IXGBE_FCRXCTRL_ICRC BIT(6) /* Ignore Bad FC CRC */
742#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 742#define IXGBE_FCRXCTRL_FCCRCBO BIT(7) /* FC CRC Byte Ordering */
743#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 743#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
744#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 744#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
745/* FCoE Redirection */ 745/* FCoE Redirection */
@@ -1131,6 +1131,7 @@ struct ixgbe_thermal_sensor_data {
1131#define IXGBE_XPCSS 0x04290 1131#define IXGBE_XPCSS 0x04290
1132#define IXGBE_MFLCN 0x04294 1132#define IXGBE_MFLCN 0x04294
1133#define IXGBE_SERDESC 0x04298 1133#define IXGBE_SERDESC 0x04298
1134#define IXGBE_MAC_SGMII_BUSY 0x04298
1134#define IXGBE_MACS 0x0429C 1135#define IXGBE_MACS 0x0429C
1135#define IXGBE_AUTOC 0x042A0 1136#define IXGBE_AUTOC 0x042A0
1136#define IXGBE_LINKS 0x042A4 1137#define IXGBE_LINKS 0x042A4
@@ -1255,20 +1256,20 @@ struct ixgbe_thermal_sensor_data {
1255#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 1256#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1256#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 1257#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
1257#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 1258#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1258#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 1259#define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
1259#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 1260#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
1260#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 1261#define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
1261#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */ 1262#define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
1262#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 1263#define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */
1263#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 1264#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */
1264 1265
1265#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 1266#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1266#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 1267#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
1267#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 1268#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1268#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 1269#define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
1269#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 1270#define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
1270#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 1271#define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */
1271#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 1272#define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
1272#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 1273#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
1273 1274
1274/* MSCA Bit Masks */ 1275/* MSCA Bit Masks */
@@ -1747,7 +1748,7 @@ enum {
1747#define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */ 1748#define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */
1748#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 1749#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1749#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 1750#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1750#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 1751#define IXGBE_ETQF_POOL_ENABLE BIT(26) /* bit 26 */
1751#define IXGBE_ETQF_POOL_SHIFT 20 1752#define IXGBE_ETQF_POOL_SHIFT 20
1752 1753
1753#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 1754#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
@@ -1873,20 +1874,20 @@ enum {
1873#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 1874#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1874#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 1875#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1875#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 1876#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
1876#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1877#define IXGBE_AUTOC_10G_XAUI (0u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1877#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1878#define IXGBE_AUTOC_10G_KX4 (1u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1878#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1879#define IXGBE_AUTOC_10G_CX4 (2u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1879#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1880#define IXGBE_AUTOC_1G_BX (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1880#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1881#define IXGBE_AUTOC_1G_KX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1881#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1882#define IXGBE_AUTOC_1G_SFI (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1882#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1883#define IXGBE_AUTOC_1G_KX_BX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1883 1884
1884#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 1885#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1885#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 1886#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1886#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 1887#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1887#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1888#define IXGBE_AUTOC2_10G_KR (0u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1888#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1889#define IXGBE_AUTOC2_10G_XFI (1u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1889#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1890#define IXGBE_AUTOC2_10G_SFI (2u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1890#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000 1891#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000
1891#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 1892#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
1892 1893
@@ -2123,6 +2124,7 @@ enum {
2123#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 2124#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
2124#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 2125#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
2125#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 2126#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
2127#define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR BIT(7)
2126#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 2128#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
2127#define IXGBE_FW_LESM_STATE_1 0x1 2129#define IXGBE_FW_LESM_STATE_1 0x1
2128#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 2130#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
@@ -2838,15 +2840,15 @@ struct ixgbe_adv_tx_context_desc {
2838#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 2840#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2839#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 2841#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2840#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 2842#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
2841#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 2843#define IXGBE_ADVTXD_FCOEF_SOF (BIT(2) << 10) /* FC SOF index */
2842#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 2844#define IXGBE_ADVTXD_FCOEF_PARINC (BIT(3) << 10) /* Rel_Off in F_CTL */
2843#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 2845#define IXGBE_ADVTXD_FCOEF_ORIE (BIT(4) << 10) /* Orientation: End */
2844#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */ 2846#define IXGBE_ADVTXD_FCOEF_ORIS (BIT(5) << 10) /* Orientation: Start */
2845#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */ 2847#define IXGBE_ADVTXD_FCOEF_EOF_N (0u << 10) /* 00: EOFn */
2846#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 2848#define IXGBE_ADVTXD_FCOEF_EOF_T (1u << 10) /* 01: EOFt */
2847#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 2849#define IXGBE_ADVTXD_FCOEF_EOF_NI (2u << 10) /* 10: EOFni */
2848#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 2850#define IXGBE_ADVTXD_FCOEF_EOF_A (3u << 10) /* 11: EOFa */
2849#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 2851#define IXGBE_ADVTXD_FCOEF_EOF_MASK (3u << 10) /* FC EOF index */
2850#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 2852#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
2851#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 2853#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
2852 2854
@@ -3581,7 +3583,7 @@ struct ixgbe_info {
3581 3583
3582#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) 3584#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
3583#define IXGBE_FUSES0_300MHZ BIT(5) 3585#define IXGBE_FUSES0_300MHZ BIT(5)
3584#define IXGBE_FUSES0_REV_MASK (3 << 6) 3586#define IXGBE_FUSES0_REV_MASK (3u << 6)
3585 3587
3586#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) 3588#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
3587#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) 3589#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
@@ -3595,25 +3597,25 @@ struct ixgbe_info {
3595#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520) 3597#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
3596#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00) 3598#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
3597 3599
3598#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9) 3600#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B BIT(9)
3599#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11) 3601#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS BIT(11)
3600 3602
3601#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8) 3603#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (7u << 8)
3602#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8) 3604#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2u << 8)
3603#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8) 3605#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4u << 8)
3604#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN BIT(12) 3606#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN BIT(12)
3605#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN BIT(13) 3607#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN BIT(13)
3606#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14) 3608#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ BIT(14)
3607#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15) 3609#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC BIT(15)
3608#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16) 3610#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX BIT(16)
3609#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18) 3611#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR BIT(18)
3610#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24) 3612#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX BIT(24)
3611#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26) 3613#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR BIT(26)
3612#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29) 3614#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE BIT(29)
3613#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31) 3615#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART BIT(31)
3614 3616
3615#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28) 3617#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE BIT(28)
3616#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29) 3618#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE BIT(29)
3617 3619
3618#define IXGBE_KRM_AN_CNTL_8_LINEAR BIT(0) 3620#define IXGBE_KRM_AN_CNTL_8_LINEAR BIT(0)
3619#define IXGBE_KRM_AN_CNTL_8_LIMITING BIT(1) 3621#define IXGBE_KRM_AN_CNTL_8_LIMITING BIT(1)
@@ -3621,28 +3623,28 @@ struct ixgbe_info {
3621#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D BIT(12) 3623#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D BIT(12)
3622#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D BIT(19) 3624#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D BIT(19)
3623 3625
3624#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6) 3626#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN BIT(6)
3625#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15) 3627#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN BIT(15)
3626#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16) 3628#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN BIT(16)
3627 3629
3628#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4) 3630#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL BIT(4)
3629#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2) 3631#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS BIT(2)
3630 3632
3631#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16) 3633#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (3u << 16)
3632 3634
3633#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1) 3635#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN BIT(1)
3634#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2) 3636#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN BIT(2)
3635#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3) 3637#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN BIT(3)
3636#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31) 3638#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN BIT(31)
3637 3639
3638#define IXGBE_KX4_LINK_CNTL_1 0x4C 3640#define IXGBE_KX4_LINK_CNTL_1 0x4C
3639#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX (1 << 16) 3641#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX BIT(16)
3640#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 (1 << 17) 3642#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 BIT(17)
3641#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX (1 << 24) 3643#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX BIT(24)
3642#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 (1 << 25) 3644#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 BIT(25)
3643#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE (1 << 29) 3645#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE BIT(29)
3644#define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP (1 << 30) 3646#define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP BIT(30)
3645#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART (1 << 31) 3647#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART BIT(31)
3646 3648
3647#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144 3649#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
3648#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148 3650#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
@@ -3658,7 +3660,7 @@ struct ixgbe_info {
3658#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28 3660#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
3659#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7 3661#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
3660#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31 3662#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
3661#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) 3663#define IXGBE_SB_IOSF_CTRL_BUSY BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
3662#define IXGBE_SB_IOSF_TARGET_KR_PHY 0 3664#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
3663#define IXGBE_SB_IOSF_TARGET_KX4_UNIPHY 1 3665#define IXGBE_SB_IOSF_TARGET_KX4_UNIPHY 1
3664#define IXGBE_SB_IOSF_TARGET_KX4_PCS0 2 3666#define IXGBE_SB_IOSF_TARGET_KX4_PCS0 2
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
index 40824d85d807..f2b1d48a16c3 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
@@ -214,8 +214,8 @@ s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
214 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 214 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
215 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 215 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
216 IXGBE_EEC_SIZE_SHIFT); 216 IXGBE_EEC_SIZE_SHIFT);
217 eeprom->word_size = 1 << (eeprom_size + 217 eeprom->word_size = BIT(eeprom_size +
218 IXGBE_EEPROM_WORD_SIZE_SHIFT); 218 IXGBE_EEPROM_WORD_SIZE_SHIFT);
219 219
220 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 220 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
221 eeprom->type, eeprom->word_size); 221 eeprom->type, eeprom->word_size);
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
index c71e93ed4451..19b75cd98682 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
@@ -335,8 +335,8 @@ static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
335 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 335 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
336 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 336 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
337 IXGBE_EEC_SIZE_SHIFT); 337 IXGBE_EEC_SIZE_SHIFT);
338 eeprom->word_size = 1 << (eeprom_size + 338 eeprom->word_size = BIT(eeprom_size +
339 IXGBE_EEPROM_WORD_SIZE_SHIFT); 339 IXGBE_EEPROM_WORD_SIZE_SHIFT);
340 340
341 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 341 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
342 eeprom->type, eeprom->word_size); 342 eeprom->type, eeprom->word_size);
@@ -2646,9 +2646,9 @@ static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2646 2646
2647 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 2647 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2648 if (enable) 2648 if (enable)
2649 pfvfspoof |= (1 << vf_target_shift); 2649 pfvfspoof |= BIT(vf_target_shift);
2650 else 2650 else
2651 pfvfspoof &= ~(1 << vf_target_shift); 2651 pfvfspoof &= ~BIT(vf_target_shift);
2652 2652
2653 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 2653 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2654} 2654}
@@ -2765,7 +2765,7 @@ static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
2765 ixgbe_release_swfw_sync_X540(hw, hmask); 2765 ixgbe_release_swfw_sync_X540(hw, hmask);
2766 if (status != IXGBE_ERR_TOKEN_RETRY) 2766 if (status != IXGBE_ERR_TOKEN_RETRY)
2767 return status; 2767 return status;
2768 udelay(FW_PHY_TOKEN_DELAY * 1000); 2768 msleep(FW_PHY_TOKEN_DELAY);
2769 } 2769 }
2770 2770
2771 return status; 2771 return status;
@@ -2908,7 +2908,7 @@ static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
2908 .get_media_type = &ixgbe_get_media_type_X550em, 2908 .get_media_type = &ixgbe_get_media_type_X550em,
2909 .get_san_mac_addr = NULL, 2909 .get_san_mac_addr = NULL,
2910 .get_wwn_prefix = NULL, 2910 .get_wwn_prefix = NULL,
2911 .setup_link = NULL, /* defined later */ 2911 .setup_link = &ixgbe_setup_mac_link_X540,
2912 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 2912 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
2913 .get_bus_info = &ixgbe_get_bus_info_X550em, 2913 .get_bus_info = &ixgbe_get_bus_info_X550em,
2914 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 2914 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
@@ -2932,7 +2932,7 @@ static struct ixgbe_mac_operations mac_ops_x550em_a = {
2932 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 2932 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
2933 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 2933 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
2934 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 2934 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
2935 .setup_fc = ixgbe_setup_fc_generic, 2935 .setup_fc = ixgbe_setup_fc_x550em,
2936 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 2936 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
2937 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 2937 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
2938}; 2938};
diff --git a/drivers/net/ethernet/intel/ixgbevf/defines.h b/drivers/net/ethernet/intel/ixgbevf/defines.h
index 58434584b16d..74901f7ef391 100644
--- a/drivers/net/ethernet/intel/ixgbevf/defines.h
+++ b/drivers/net/ethernet/intel/ixgbevf/defines.h
@@ -74,7 +74,7 @@ typedef u32 ixgbe_link_speed;
74#define IXGBE_RXDCTL_RLPML_EN 0x00008000 74#define IXGBE_RXDCTL_RLPML_EN 0x00008000
75 75
76/* DCA Control */ 76/* DCA Control */
77#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 77#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
78 78
79/* PSRTYPE bit definitions */ 79/* PSRTYPE bit definitions */
80#define IXGBE_PSRTYPE_TCPHDR 0x00000010 80#define IXGBE_PSRTYPE_TCPHDR 0x00000010
@@ -296,16 +296,16 @@ struct ixgbe_adv_tx_context_desc {
296#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 296#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */
297#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 297#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
298 298
299#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */ 299#define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* Rx Desc enable */
300#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */ 300#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* Rx Desc header ena */
301#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */ 301#define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* Rx Desc payload ena */
302#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */ 302#define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* Rx rd Desc Relax Order */
303#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 303#define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */
304#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 304#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */
305 305
306#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 306#define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
307#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 307#define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
308#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 308#define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */
309#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 309#define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
310 310
311#endif /* _IXGBEVF_DEFINES_H_ */ 311#endif /* _IXGBEVF_DEFINES_H_ */
diff --git a/drivers/net/ethernet/intel/ixgbevf/ethtool.c b/drivers/net/ethernet/intel/ixgbevf/ethtool.c
index d7aa4b203f40..508e72c5f1c2 100644
--- a/drivers/net/ethernet/intel/ixgbevf/ethtool.c
+++ b/drivers/net/ethernet/intel/ixgbevf/ethtool.c
@@ -42,65 +42,54 @@
42 42
43#define IXGBE_ALL_RAR_ENTRIES 16 43#define IXGBE_ALL_RAR_ENTRIES 16
44 44
45enum {NETDEV_STATS, IXGBEVF_STATS};
46
45struct ixgbe_stats { 47struct ixgbe_stats {
46 char stat_string[ETH_GSTRING_LEN]; 48 char stat_string[ETH_GSTRING_LEN];
47 struct { 49 int type;
48 int sizeof_stat; 50 int sizeof_stat;
49 int stat_offset; 51 int stat_offset;
50 int base_stat_offset;
51 int saved_reset_offset;
52 };
53}; 52};
54 53
55#define IXGBEVF_STAT(m, b, r) { \ 54#define IXGBEVF_STAT(_name, _stat) { \
56 .sizeof_stat = FIELD_SIZEOF(struct ixgbevf_adapter, m), \ 55 .stat_string = _name, \
57 .stat_offset = offsetof(struct ixgbevf_adapter, m), \ 56 .type = IXGBEVF_STATS, \
58 .base_stat_offset = offsetof(struct ixgbevf_adapter, b), \ 57 .sizeof_stat = FIELD_SIZEOF(struct ixgbevf_adapter, _stat), \
59 .saved_reset_offset = offsetof(struct ixgbevf_adapter, r) \ 58 .stat_offset = offsetof(struct ixgbevf_adapter, _stat) \
60} 59}
61 60
62#define IXGBEVF_ZSTAT(m) { \ 61#define IXGBEVF_NETDEV_STAT(_net_stat) { \
63 .sizeof_stat = FIELD_SIZEOF(struct ixgbevf_adapter, m), \ 62 .stat_string = #_net_stat, \
64 .stat_offset = offsetof(struct ixgbevf_adapter, m), \ 63 .type = NETDEV_STATS, \
65 .base_stat_offset = -1, \ 64 .sizeof_stat = FIELD_SIZEOF(struct net_device_stats, _net_stat), \
66 .saved_reset_offset = -1 \ 65 .stat_offset = offsetof(struct net_device_stats, _net_stat) \
67} 66}
68 67
69static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 68static struct ixgbe_stats ixgbevf_gstrings_stats[] = {
70 {"rx_packets", IXGBEVF_STAT(stats.vfgprc, stats.base_vfgprc, 69 IXGBEVF_NETDEV_STAT(rx_packets),
71 stats.saved_reset_vfgprc)}, 70 IXGBEVF_NETDEV_STAT(tx_packets),
72 {"tx_packets", IXGBEVF_STAT(stats.vfgptc, stats.base_vfgptc, 71 IXGBEVF_NETDEV_STAT(rx_bytes),
73 stats.saved_reset_vfgptc)}, 72 IXGBEVF_NETDEV_STAT(tx_bytes),
74 {"rx_bytes", IXGBEVF_STAT(stats.vfgorc, stats.base_vfgorc, 73 IXGBEVF_STAT("tx_busy", tx_busy),
75 stats.saved_reset_vfgorc)}, 74 IXGBEVF_STAT("tx_restart_queue", restart_queue),
76 {"tx_bytes", IXGBEVF_STAT(stats.vfgotc, stats.base_vfgotc, 75 IXGBEVF_STAT("tx_timeout_count", tx_timeout_count),
77 stats.saved_reset_vfgotc)}, 76 IXGBEVF_NETDEV_STAT(multicast),
78 {"tx_busy", IXGBEVF_ZSTAT(tx_busy)}, 77 IXGBEVF_STAT("rx_csum_offload_errors", hw_csum_rx_error),
79 {"tx_restart_queue", IXGBEVF_ZSTAT(restart_queue)},
80 {"tx_timeout_count", IXGBEVF_ZSTAT(tx_timeout_count)},
81 {"multicast", IXGBEVF_STAT(stats.vfmprc, stats.base_vfmprc,
82 stats.saved_reset_vfmprc)},
83 {"rx_csum_offload_errors", IXGBEVF_ZSTAT(hw_csum_rx_error)},
84#ifdef BP_EXTENDED_STATS
85 {"rx_bp_poll_yield", IXGBEVF_ZSTAT(bp_rx_yields)},
86 {"rx_bp_cleaned", IXGBEVF_ZSTAT(bp_rx_cleaned)},
87 {"rx_bp_misses", IXGBEVF_ZSTAT(bp_rx_missed)},
88 {"tx_bp_napi_yield", IXGBEVF_ZSTAT(bp_tx_yields)},
89 {"tx_bp_cleaned", IXGBEVF_ZSTAT(bp_tx_cleaned)},
90 {"tx_bp_misses", IXGBEVF_ZSTAT(bp_tx_missed)},
91#endif
92}; 78};
93 79
94#define IXGBE_QUEUE_STATS_LEN 0 80#define IXGBEVF_QUEUE_STATS_LEN ( \
95#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 81 (((struct ixgbevf_adapter *)netdev_priv(netdev))->num_tx_queues + \
82 ((struct ixgbevf_adapter *)netdev_priv(netdev))->num_rx_queues) * \
83 (sizeof(struct ixgbe_stats) / sizeof(u64)))
84#define IXGBEVF_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbevf_gstrings_stats)
96 85
97#define IXGBEVF_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + IXGBE_QUEUE_STATS_LEN) 86#define IXGBEVF_STATS_LEN (IXGBEVF_GLOBAL_STATS_LEN + IXGBEVF_QUEUE_STATS_LEN)
98static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 87static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
99 "Register test (offline)", 88 "Register test (offline)",
100 "Link test (on/offline)" 89 "Link test (on/offline)"
101}; 90};
102 91
103#define IXGBE_TEST_LEN (sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN) 92#define IXGBEVF_TEST_LEN (sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN)
104 93
105static int ixgbevf_get_settings(struct net_device *netdev, 94static int ixgbevf_get_settings(struct net_device *netdev,
106 struct ethtool_cmd *ecmd) 95 struct ethtool_cmd *ecmd)
@@ -177,7 +166,8 @@ static void ixgbevf_get_regs(struct net_device *netdev,
177 166
178 memset(p, 0, regs_len); 167 memset(p, 0, regs_len);
179 168
180 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id; 169 /* generate a number suitable for ethtool's register version */
170 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id;
181 171
182 /* General Registers */ 172 /* General Registers */
183 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_VFCTRL); 173 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_VFCTRL);
@@ -392,13 +382,13 @@ clear_reset:
392 return err; 382 return err;
393} 383}
394 384
395static int ixgbevf_get_sset_count(struct net_device *dev, int stringset) 385static int ixgbevf_get_sset_count(struct net_device *netdev, int stringset)
396{ 386{
397 switch (stringset) { 387 switch (stringset) {
398 case ETH_SS_TEST: 388 case ETH_SS_TEST:
399 return IXGBE_TEST_LEN; 389 return IXGBEVF_TEST_LEN;
400 case ETH_SS_STATS: 390 case ETH_SS_STATS:
401 return IXGBE_GLOBAL_STATS_LEN; 391 return IXGBEVF_STATS_LEN;
402 default: 392 default:
403 return -EINVAL; 393 return -EINVAL;
404 } 394 }
@@ -408,70 +398,138 @@ static void ixgbevf_get_ethtool_stats(struct net_device *netdev,
408 struct ethtool_stats *stats, u64 *data) 398 struct ethtool_stats *stats, u64 *data)
409{ 399{
410 struct ixgbevf_adapter *adapter = netdev_priv(netdev); 400 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
411 char *base = (char *)adapter; 401 struct rtnl_link_stats64 temp;
412 int i; 402 const struct rtnl_link_stats64 *net_stats;
413#ifdef BP_EXTENDED_STATS 403 unsigned int start;
414 u64 rx_yields = 0, rx_cleaned = 0, rx_missed = 0, 404 struct ixgbevf_ring *ring;
415 tx_yields = 0, tx_cleaned = 0, tx_missed = 0; 405 int i, j;
406 char *p;
416 407
417 for (i = 0; i < adapter->num_rx_queues; i++) { 408 ixgbevf_update_stats(adapter);
418 rx_yields += adapter->rx_ring[i]->stats.yields; 409 net_stats = dev_get_stats(netdev, &temp);
419 rx_cleaned += adapter->rx_ring[i]->stats.cleaned; 410 for (i = 0; i < IXGBEVF_GLOBAL_STATS_LEN; i++) {
420 rx_yields += adapter->rx_ring[i]->stats.yields; 411 switch (ixgbevf_gstrings_stats[i].type) {
421 } 412 case NETDEV_STATS:
413 p = (char *)net_stats +
414 ixgbevf_gstrings_stats[i].stat_offset;
415 break;
416 case IXGBEVF_STATS:
417 p = (char *)adapter +
418 ixgbevf_gstrings_stats[i].stat_offset;
419 break;
420 default:
421 data[i] = 0;
422 continue;
423 }
422 424
423 for (i = 0; i < adapter->num_tx_queues; i++) { 425 data[i] = (ixgbevf_gstrings_stats[i].sizeof_stat ==
424 tx_yields += adapter->tx_ring[i]->stats.yields; 426 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
425 tx_cleaned += adapter->tx_ring[i]->stats.cleaned;
426 tx_yields += adapter->tx_ring[i]->stats.yields;
427 } 427 }
428 428
429 adapter->bp_rx_yields = rx_yields; 429 /* populate Tx queue data */
430 adapter->bp_rx_cleaned = rx_cleaned; 430 for (j = 0; j < adapter->num_tx_queues; j++) {
431 adapter->bp_rx_missed = rx_missed; 431 ring = adapter->tx_ring[j];
432 if (!ring) {
433 data[i++] = 0;
434 data[i++] = 0;
435#ifdef BP_EXTENDED_STATS
436 data[i++] = 0;
437 data[i++] = 0;
438 data[i++] = 0;
439#endif
440 continue;
441 }
432 442
433 adapter->bp_tx_yields = tx_yields; 443 do {
434 adapter->bp_tx_cleaned = tx_cleaned; 444 start = u64_stats_fetch_begin_irq(&ring->syncp);
435 adapter->bp_tx_missed = tx_missed; 445 data[i] = ring->stats.packets;
446 data[i + 1] = ring->stats.bytes;
447 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
448 i += 2;
449#ifdef BP_EXTENDED_STATS
450 data[i] = ring->stats.yields;
451 data[i + 1] = ring->stats.misses;
452 data[i + 2] = ring->stats.cleaned;
453 i += 3;
436#endif 454#endif
455 }
437 456
438 ixgbevf_update_stats(adapter); 457 /* populate Rx queue data */
439 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 458 for (j = 0; j < adapter->num_rx_queues; j++) {
440 char *p = base + ixgbe_gstrings_stats[i].stat_offset; 459 ring = adapter->rx_ring[j];
441 char *b = base + ixgbe_gstrings_stats[i].base_stat_offset; 460 if (!ring) {
442 char *r = base + ixgbe_gstrings_stats[i].saved_reset_offset; 461 data[i++] = 0;
443 462 data[i++] = 0;
444 if (ixgbe_gstrings_stats[i].sizeof_stat == sizeof(u64)) { 463#ifdef BP_EXTENDED_STATS
445 if (ixgbe_gstrings_stats[i].base_stat_offset >= 0) 464 data[i++] = 0;
446 data[i] = *(u64 *)p - *(u64 *)b + *(u64 *)r; 465 data[i++] = 0;
447 else 466 data[i++] = 0;
448 data[i] = *(u64 *)p; 467#endif
449 } else { 468 continue;
450 if (ixgbe_gstrings_stats[i].base_stat_offset >= 0)
451 data[i] = *(u32 *)p - *(u32 *)b + *(u32 *)r;
452 else
453 data[i] = *(u32 *)p;
454 } 469 }
470
471 do {
472 start = u64_stats_fetch_begin_irq(&ring->syncp);
473 data[i] = ring->stats.packets;
474 data[i + 1] = ring->stats.bytes;
475 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
476 i += 2;
477#ifdef BP_EXTENDED_STATS
478 data[i] = ring->stats.yields;
479 data[i + 1] = ring->stats.misses;
480 data[i + 2] = ring->stats.cleaned;
481 i += 3;
482#endif
455 } 483 }
456} 484}
457 485
458static void ixgbevf_get_strings(struct net_device *netdev, u32 stringset, 486static void ixgbevf_get_strings(struct net_device *netdev, u32 stringset,
459 u8 *data) 487 u8 *data)
460{ 488{
489 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
461 char *p = (char *)data; 490 char *p = (char *)data;
462 int i; 491 int i;
463 492
464 switch (stringset) { 493 switch (stringset) {
465 case ETH_SS_TEST: 494 case ETH_SS_TEST:
466 memcpy(data, *ixgbe_gstrings_test, 495 memcpy(data, *ixgbe_gstrings_test,
467 IXGBE_TEST_LEN * ETH_GSTRING_LEN); 496 IXGBEVF_TEST_LEN * ETH_GSTRING_LEN);
468 break; 497 break;
469 case ETH_SS_STATS: 498 case ETH_SS_STATS:
470 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 499 for (i = 0; i < IXGBEVF_GLOBAL_STATS_LEN; i++) {
471 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 500 memcpy(p, ixgbevf_gstrings_stats[i].stat_string,
472 ETH_GSTRING_LEN); 501 ETH_GSTRING_LEN);
473 p += ETH_GSTRING_LEN; 502 p += ETH_GSTRING_LEN;
474 } 503 }
504
505 for (i = 0; i < adapter->num_tx_queues; i++) {
506 sprintf(p, "tx_queue_%u_packets", i);
507 p += ETH_GSTRING_LEN;
508 sprintf(p, "tx_queue_%u_bytes", i);
509 p += ETH_GSTRING_LEN;
510#ifdef BP_EXTENDED_STATS
511 sprintf(p, "tx_queue_%u_bp_napi_yield", i);
512 p += ETH_GSTRING_LEN;
513 sprintf(p, "tx_queue_%u_bp_misses", i);
514 p += ETH_GSTRING_LEN;
515 sprintf(p, "tx_queue_%u_bp_cleaned", i);
516 p += ETH_GSTRING_LEN;
517#endif /* BP_EXTENDED_STATS */
518 }
519 for (i = 0; i < adapter->num_rx_queues; i++) {
520 sprintf(p, "rx_queue_%u_packets", i);
521 p += ETH_GSTRING_LEN;
522 sprintf(p, "rx_queue_%u_bytes", i);
523 p += ETH_GSTRING_LEN;
524#ifdef BP_EXTENDED_STATS
525 sprintf(p, "rx_queue_%u_bp_poll_yield", i);
526 p += ETH_GSTRING_LEN;
527 sprintf(p, "rx_queue_%u_bp_misses", i);
528 p += ETH_GSTRING_LEN;
529 sprintf(p, "rx_queue_%u_bp_cleaned", i);
530 p += ETH_GSTRING_LEN;
531#endif /* BP_EXTENDED_STATS */
532 }
475 break; 533 break;
476 } 534 }
477} 535}
diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h b/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h
index 5ac60eefb0cd..aa28c4fb1a43 100644
--- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h
+++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h
@@ -166,10 +166,10 @@ struct ixgbevf_ring {
166 166
167#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 167#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
168 168
169#define IXGBE_TX_FLAGS_CSUM (u32)(1) 169#define IXGBE_TX_FLAGS_CSUM BIT(0)
170#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1) 170#define IXGBE_TX_FLAGS_VLAN BIT(1)
171#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2) 171#define IXGBE_TX_FLAGS_TSO BIT(2)
172#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3) 172#define IXGBE_TX_FLAGS_IPV4 BIT(3)
173#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 173#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
174#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 174#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
175#define IXGBE_TX_FLAGS_VLAN_SHIFT 16 175#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
@@ -422,16 +422,6 @@ struct ixgbevf_adapter {
422 unsigned int tx_ring_count; 422 unsigned int tx_ring_count;
423 unsigned int rx_ring_count; 423 unsigned int rx_ring_count;
424 424
425#ifdef BP_EXTENDED_STATS
426 u64 bp_rx_yields;
427 u64 bp_rx_cleaned;
428 u64 bp_rx_missed;
429
430 u64 bp_tx_yields;
431 u64 bp_tx_cleaned;
432 u64 bp_tx_missed;
433#endif
434
435 u8 __iomem *io_addr; /* Mainly for iounmap use */ 425 u8 __iomem *io_addr; /* Mainly for iounmap use */
436 u32 link_speed; 426 u32 link_speed;
437 bool link_up; 427 bool link_up;
diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
index 007cbe094990..319e25f29883 100644
--- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
+++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
@@ -1056,7 +1056,7 @@ static int ixgbevf_poll(struct napi_struct *napi, int budget)
1056 if (!test_bit(__IXGBEVF_DOWN, &adapter->state) && 1056 if (!test_bit(__IXGBEVF_DOWN, &adapter->state) &&
1057 !test_bit(__IXGBEVF_REMOVING, &adapter->state)) 1057 !test_bit(__IXGBEVF_REMOVING, &adapter->state))
1058 ixgbevf_irq_enable_queues(adapter, 1058 ixgbevf_irq_enable_queues(adapter,
1059 1 << q_vector->v_idx); 1059 BIT(q_vector->v_idx));
1060 1060
1061 return 0; 1061 return 0;
1062} 1062}
@@ -1158,14 +1158,14 @@ static void ixgbevf_configure_msix(struct ixgbevf_adapter *adapter)
1158 } 1158 }
1159 1159
1160 /* add q_vector eims value to global eims_enable_mask */ 1160 /* add q_vector eims value to global eims_enable_mask */
1161 adapter->eims_enable_mask |= 1 << v_idx; 1161 adapter->eims_enable_mask |= BIT(v_idx);
1162 1162
1163 ixgbevf_write_eitr(q_vector); 1163 ixgbevf_write_eitr(q_vector);
1164 } 1164 }
1165 1165
1166 ixgbevf_set_ivar(adapter, -1, 1, v_idx); 1166 ixgbevf_set_ivar(adapter, -1, 1, v_idx);
1167 /* setup eims_other and add value to global eims_enable_mask */ 1167 /* setup eims_other and add value to global eims_enable_mask */
1168 adapter->eims_other = 1 << v_idx; 1168 adapter->eims_other = BIT(v_idx);
1169 adapter->eims_enable_mask |= adapter->eims_other; 1169 adapter->eims_enable_mask |= adapter->eims_other;
1170} 1170}
1171 1171
@@ -1589,8 +1589,8 @@ static void ixgbevf_configure_tx_ring(struct ixgbevf_adapter *adapter,
1589 txdctl |= (8 << 16); /* WTHRESH = 8 */ 1589 txdctl |= (8 << 16); /* WTHRESH = 8 */
1590 1590
1591 /* Setting PTHRESH to 32 both improves performance */ 1591 /* Setting PTHRESH to 32 both improves performance */
1592 txdctl |= (1 << 8) | /* HTHRESH = 1 */ 1592 txdctl |= (1u << 8) | /* HTHRESH = 1 */
1593 32; /* PTHRESH = 32 */ 1593 32; /* PTHRESH = 32 */
1594 1594
1595 clear_bit(__IXGBEVF_HANG_CHECK_ARMED, &ring->state); 1595 clear_bit(__IXGBEVF_HANG_CHECK_ARMED, &ring->state);
1596 1596
@@ -1646,7 +1646,7 @@ static void ixgbevf_setup_psrtype(struct ixgbevf_adapter *adapter)
1646 IXGBE_PSRTYPE_L2HDR; 1646 IXGBE_PSRTYPE_L2HDR;
1647 1647
1648 if (adapter->num_rx_queues > 1) 1648 if (adapter->num_rx_queues > 1)
1649 psrtype |= 1 << 29; 1649 psrtype |= BIT(29);
1650 1650
1651 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype); 1651 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
1652} 1652}
@@ -2056,7 +2056,7 @@ static void ixgbevf_negotiate_api(struct ixgbevf_adapter *adapter)
2056 spin_lock_bh(&adapter->mbx_lock); 2056 spin_lock_bh(&adapter->mbx_lock);
2057 2057
2058 while (api[idx] != ixgbe_mbox_api_unknown) { 2058 while (api[idx] != ixgbe_mbox_api_unknown) {
2059 err = ixgbevf_negotiate_api_version(hw, api[idx]); 2059 err = hw->mac.ops.negotiate_api_version(hw, api[idx]);
2060 if (!err) 2060 if (!err)
2061 break; 2061 break;
2062 idx++; 2062 idx++;
@@ -2797,7 +2797,7 @@ static void ixgbevf_check_hang_subtask(struct ixgbevf_adapter *adapter)
2797 struct ixgbevf_q_vector *qv = adapter->q_vector[i]; 2797 struct ixgbevf_q_vector *qv = adapter->q_vector[i];
2798 2798
2799 if (qv->rx.ring || qv->tx.ring) 2799 if (qv->rx.ring || qv->tx.ring)
2800 eics |= 1 << i; 2800 eics |= BIT(i);
2801 } 2801 }
2802 2802
2803 /* Cause software interrupt to ensure rings are cleaned */ 2803 /* Cause software interrupt to ensure rings are cleaned */
@@ -3272,9 +3272,18 @@ static int ixgbevf_tso(struct ixgbevf_ring *tx_ring,
3272 struct ixgbevf_tx_buffer *first, 3272 struct ixgbevf_tx_buffer *first,
3273 u8 *hdr_len) 3273 u8 *hdr_len)
3274{ 3274{
3275 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
3275 struct sk_buff *skb = first->skb; 3276 struct sk_buff *skb = first->skb;
3276 u32 vlan_macip_lens, type_tucmd; 3277 union {
3277 u32 mss_l4len_idx, l4len; 3278 struct iphdr *v4;
3279 struct ipv6hdr *v6;
3280 unsigned char *hdr;
3281 } ip;
3282 union {
3283 struct tcphdr *tcp;
3284 unsigned char *hdr;
3285 } l4;
3286 u32 paylen, l4_offset;
3278 int err; 3287 int err;
3279 3288
3280 if (skb->ip_summed != CHECKSUM_PARTIAL) 3289 if (skb->ip_summed != CHECKSUM_PARTIAL)
@@ -3287,49 +3296,53 @@ static int ixgbevf_tso(struct ixgbevf_ring *tx_ring,
3287 if (err < 0) 3296 if (err < 0)
3288 return err; 3297 return err;
3289 3298
3299 ip.hdr = skb_network_header(skb);
3300 l4.hdr = skb_checksum_start(skb);
3301
3290 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 3302 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3291 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 3303 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
3292 3304
3293 if (first->protocol == htons(ETH_P_IP)) { 3305 /* initialize outer IP header fields */
3294 struct iphdr *iph = ip_hdr(skb); 3306 if (ip.v4->version == 4) {
3295 3307 /* IP header will have to cancel out any data that
3296 iph->tot_len = 0; 3308 * is not a part of the outer IP header
3297 iph->check = 0; 3309 */
3298 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 3310 ip.v4->check = csum_fold(csum_add(lco_csum(skb),
3299 iph->daddr, 0, 3311 csum_unfold(l4.tcp->check)));
3300 IPPROTO_TCP,
3301 0);
3302 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 3312 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
3313
3314 ip.v4->tot_len = 0;
3303 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 3315 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
3304 IXGBE_TX_FLAGS_CSUM | 3316 IXGBE_TX_FLAGS_CSUM |
3305 IXGBE_TX_FLAGS_IPV4; 3317 IXGBE_TX_FLAGS_IPV4;
3306 } else if (skb_is_gso_v6(skb)) { 3318 } else {
3307 ipv6_hdr(skb)->payload_len = 0; 3319 ip.v6->payload_len = 0;
3308 tcp_hdr(skb)->check =
3309 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3310 &ipv6_hdr(skb)->daddr,
3311 0, IPPROTO_TCP, 0);
3312 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 3320 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
3313 IXGBE_TX_FLAGS_CSUM; 3321 IXGBE_TX_FLAGS_CSUM;
3314 } 3322 }
3315 3323
3316 /* compute header lengths */ 3324 /* determine offset of inner transport header */
3317 l4len = tcp_hdrlen(skb); 3325 l4_offset = l4.hdr - skb->data;
3318 *hdr_len += l4len; 3326
3319 *hdr_len = skb_transport_offset(skb) + l4len; 3327 /* compute length of segmentation header */
3328 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
3320 3329
3321 /* update GSO size and bytecount with header size */ 3330 /* remove payload length from inner checksum */
3331 paylen = skb->len - l4_offset;
3332 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
3333
3334 /* update gso size and bytecount with header size */
3322 first->gso_segs = skb_shinfo(skb)->gso_segs; 3335 first->gso_segs = skb_shinfo(skb)->gso_segs;
3323 first->bytecount += (first->gso_segs - 1) * *hdr_len; 3336 first->bytecount += (first->gso_segs - 1) * *hdr_len;
3324 3337
3325 /* mss_l4len_id: use 1 as index for TSO */ 3338 /* mss_l4len_id: use 1 as index for TSO */
3326 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; 3339 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
3327 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 3340 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
3328 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; 3341 mss_l4len_idx |= (1u << IXGBE_ADVTXD_IDX_SHIFT);
3329 3342
3330 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 3343 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
3331 vlan_macip_lens = skb_network_header_len(skb); 3344 vlan_macip_lens = l4.hdr - ip.hdr;
3332 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 3345 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
3333 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 3346 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
3334 3347
3335 ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens, 3348 ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens,
@@ -3422,7 +3435,7 @@ static void ixgbevf_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
3422 3435
3423 /* use index 1 context for TSO/FSO/FCOE */ 3436 /* use index 1 context for TSO/FSO/FCOE */
3424 if (tx_flags & IXGBE_TX_FLAGS_TSO) 3437 if (tx_flags & IXGBE_TX_FLAGS_TSO)
3425 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); 3438 olinfo_status |= cpu_to_le32(1u << IXGBE_ADVTXD_IDX_SHIFT);
3426 3439
3427 /* Check Context must be set if Tx switch is enabled, which it 3440 /* Check Context must be set if Tx switch is enabled, which it
3428 * always is for case where virtual functions are running 3441 * always is for case where virtual functions are running
@@ -3870,6 +3883,40 @@ static struct rtnl_link_stats64 *ixgbevf_get_stats(struct net_device *netdev,
3870 return stats; 3883 return stats;
3871} 3884}
3872 3885
3886#define IXGBEVF_MAX_MAC_HDR_LEN 127
3887#define IXGBEVF_MAX_NETWORK_HDR_LEN 511
3888
3889static netdev_features_t
3890ixgbevf_features_check(struct sk_buff *skb, struct net_device *dev,
3891 netdev_features_t features)
3892{
3893 unsigned int network_hdr_len, mac_hdr_len;
3894
3895 /* Make certain the headers can be described by a context descriptor */
3896 mac_hdr_len = skb_network_header(skb) - skb->data;
3897 if (unlikely(mac_hdr_len > IXGBEVF_MAX_MAC_HDR_LEN))
3898 return features & ~(NETIF_F_HW_CSUM |
3899 NETIF_F_SCTP_CRC |
3900 NETIF_F_HW_VLAN_CTAG_TX |
3901 NETIF_F_TSO |
3902 NETIF_F_TSO6);
3903
3904 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
3905 if (unlikely(network_hdr_len > IXGBEVF_MAX_NETWORK_HDR_LEN))
3906 return features & ~(NETIF_F_HW_CSUM |
3907 NETIF_F_SCTP_CRC |
3908 NETIF_F_TSO |
3909 NETIF_F_TSO6);
3910
3911 /* We can only support IPV4 TSO in tunnels if we can mangle the
3912 * inner IP ID field, so strip TSO if MANGLEID is not supported.
3913 */
3914 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
3915 features &= ~NETIF_F_TSO;
3916
3917 return features;
3918}
3919
3873static const struct net_device_ops ixgbevf_netdev_ops = { 3920static const struct net_device_ops ixgbevf_netdev_ops = {
3874 .ndo_open = ixgbevf_open, 3921 .ndo_open = ixgbevf_open,
3875 .ndo_stop = ixgbevf_close, 3922 .ndo_stop = ixgbevf_close,
@@ -3888,7 +3935,7 @@ static const struct net_device_ops ixgbevf_netdev_ops = {
3888#ifdef CONFIG_NET_POLL_CONTROLLER 3935#ifdef CONFIG_NET_POLL_CONTROLLER
3889 .ndo_poll_controller = ixgbevf_netpoll, 3936 .ndo_poll_controller = ixgbevf_netpoll,
3890#endif 3937#endif
3891 .ndo_features_check = passthru_features_check, 3938 .ndo_features_check = ixgbevf_features_check,
3892}; 3939};
3893 3940
3894static void ixgbevf_assign_netdev_ops(struct net_device *dev) 3941static void ixgbevf_assign_netdev_ops(struct net_device *dev)
@@ -3999,23 +4046,31 @@ static int ixgbevf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3999 NETIF_F_HW_CSUM | 4046 NETIF_F_HW_CSUM |
4000 NETIF_F_SCTP_CRC; 4047 NETIF_F_SCTP_CRC;
4001 4048
4002 netdev->features = netdev->hw_features | 4049#define IXGBEVF_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
4003 NETIF_F_HW_VLAN_CTAG_TX | 4050 NETIF_F_GSO_GRE_CSUM | \
4004 NETIF_F_HW_VLAN_CTAG_RX | 4051 NETIF_F_GSO_IPIP | \
4005 NETIF_F_HW_VLAN_CTAG_FILTER; 4052 NETIF_F_GSO_SIT | \
4053 NETIF_F_GSO_UDP_TUNNEL | \
4054 NETIF_F_GSO_UDP_TUNNEL_CSUM)
4006 4055
4007 netdev->vlan_features |= NETIF_F_SG | 4056 netdev->gso_partial_features = IXGBEVF_GSO_PARTIAL_FEATURES;
4008 NETIF_F_TSO | 4057 netdev->hw_features |= NETIF_F_GSO_PARTIAL |
4009 NETIF_F_TSO6 | 4058 IXGBEVF_GSO_PARTIAL_FEATURES;
4010 NETIF_F_HW_CSUM |
4011 NETIF_F_SCTP_CRC;
4012 4059
4013 netdev->mpls_features |= NETIF_F_HW_CSUM; 4060 netdev->features = netdev->hw_features;
4014 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4015 4061
4016 if (pci_using_dac) 4062 if (pci_using_dac)
4017 netdev->features |= NETIF_F_HIGHDMA; 4063 netdev->features |= NETIF_F_HIGHDMA;
4018 4064
4065 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
4066 netdev->mpls_features |= NETIF_F_HW_CSUM;
4067 netdev->hw_enc_features |= netdev->vlan_features;
4068
4069 /* set this bit last since it cannot be part of vlan_features */
4070 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
4071 NETIF_F_HW_VLAN_CTAG_RX |
4072 NETIF_F_HW_VLAN_CTAG_TX;
4073
4019 netdev->priv_flags |= IFF_UNICAST_FLT; 4074 netdev->priv_flags |= IFF_UNICAST_FLT;
4020 4075
4021 if (IXGBE_REMOVED(hw->hw_addr)) { 4076 if (IXGBE_REMOVED(hw->hw_addr)) {
diff --git a/drivers/net/ethernet/intel/ixgbevf/vf.c b/drivers/net/ethernet/intel/ixgbevf/vf.c
index 4d613a4f2a7f..987ad69d4918 100644
--- a/drivers/net/ethernet/intel/ixgbevf/vf.c
+++ b/drivers/net/ethernet/intel/ixgbevf/vf.c
@@ -670,11 +670,11 @@ void ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size)
670} 670}
671 671
672/** 672/**
673 * ixgbevf_negotiate_api_version - Negotiate supported API version 673 * ixgbevf_negotiate_api_version_vf - Negotiate supported API version
674 * @hw: pointer to the HW structure 674 * @hw: pointer to the HW structure
675 * @api: integer containing requested API version 675 * @api: integer containing requested API version
676 **/ 676 **/
677int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api) 677static int ixgbevf_negotiate_api_version_vf(struct ixgbe_hw *hw, int api)
678{ 678{
679 int err; 679 int err;
680 u32 msg[3]; 680 u32 msg[3];
@@ -769,6 +769,7 @@ static const struct ixgbe_mac_operations ixgbevf_mac_ops = {
769 .stop_adapter = ixgbevf_stop_hw_vf, 769 .stop_adapter = ixgbevf_stop_hw_vf,
770 .setup_link = ixgbevf_setup_mac_link_vf, 770 .setup_link = ixgbevf_setup_mac_link_vf,
771 .check_link = ixgbevf_check_mac_link_vf, 771 .check_link = ixgbevf_check_mac_link_vf,
772 .negotiate_api_version = ixgbevf_negotiate_api_version_vf,
772 .set_rar = ixgbevf_set_rar_vf, 773 .set_rar = ixgbevf_set_rar_vf,
773 .update_mc_addr_list = ixgbevf_update_mc_addr_list_vf, 774 .update_mc_addr_list = ixgbevf_update_mc_addr_list_vf,
774 .update_xcast_mode = ixgbevf_update_xcast_mode, 775 .update_xcast_mode = ixgbevf_update_xcast_mode,
diff --git a/drivers/net/ethernet/intel/ixgbevf/vf.h b/drivers/net/ethernet/intel/ixgbevf/vf.h
index ef9f7736b4dc..8e623f9327ae 100644
--- a/drivers/net/ethernet/intel/ixgbevf/vf.h
+++ b/drivers/net/ethernet/intel/ixgbevf/vf.h
@@ -51,6 +51,7 @@ struct ixgbe_mac_operations {
51 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 51 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
52 s32 (*stop_adapter)(struct ixgbe_hw *); 52 s32 (*stop_adapter)(struct ixgbe_hw *);
53 s32 (*get_bus_info)(struct ixgbe_hw *); 53 s32 (*get_bus_info)(struct ixgbe_hw *);
54 s32 (*negotiate_api_version)(struct ixgbe_hw *hw, int api);
54 55
55 /* Link */ 56 /* Link */
56 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool); 57 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
@@ -208,7 +209,6 @@ static inline u32 ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg,
208#define IXGBE_READ_REG_ARRAY(h, r, o) ixgbe_read_reg_array(h, r, o) 209#define IXGBE_READ_REG_ARRAY(h, r, o) ixgbe_read_reg_array(h, r, o)
209 210
210void ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size); 211void ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size);
211int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api);
212int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs, 212int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,
213 unsigned int *default_tc); 213 unsigned int *default_tc);
214int ixgbevf_get_reta_locked(struct ixgbe_hw *hw, u32 *reta, int num_rx_queues); 214int ixgbevf_get_reta_locked(struct ixgbe_hw *hw, u32 *reta, int num_rx_queues);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 19:01:10 -0400