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authorZhao Qiang <qiang.zhao@nxp.com>2016-05-16 22:39:03 -0400
committerScott Wood <oss@buserror.net>2016-07-09 02:12:04 -0400
commit1afbf61750364864adf6a17818c5bbbea4dea531 (patch)
tree5b94a5cb2deb2576d293e631ef9f4fa6faf8ca72
parentdf02087d271ca3568ce0b8abd334305ecdda9060 (diff)
T104xQDS: Add qe node to t104xqds
add qe node to t104xqds.dtsi Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
-rw-r--r--arch/powerpc/boot/dts/fsl/t104xqds.dtsi38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t104xqds.dtsi b/arch/powerpc/boot/dts/fsl/t104xqds.dtsi
index 977af355b388..2fd4cbe7098f 100644
--- a/arch/powerpc/boot/dts/fsl/t104xqds.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t104xqds.dtsi
@@ -366,4 +366,42 @@
366 0 0x00010000>; 366 0 0x00010000>;
367 }; 367 };
368 }; 368 };
369
370 qe: qe@ffe140000 {
371 ranges = <0x0 0xf 0xfe140000 0x40000>;
372 reg = <0xf 0xfe140000 0 0x480>;
373 brg-frequency = <0>;
374 bus-frequency = <0>;
375
376 si1: si@700 {
377 compatible = "fsl,t1040-qe-si";
378 reg = <0x700 0x80>;
379 };
380
381 siram1: siram@1000 {
382 compatible = "fsl,t1040-qe-siram";
383 reg = <0x1000 0x800>;
384 };
385
386 ucc_hdlc: ucc@2000 {
387 compatible = "fsl,ucc-hdlc";
388 rx-clock-name = "clk8";
389 tx-clock-name = "clk9";
390 fsl,rx-sync-clock = "rsync_pin";
391 fsl,tx-sync-clock = "tsync_pin";
392 fsl,tx-timeslot-mask = <0xfffffffe>;
393 fsl,rx-timeslot-mask = <0xfffffffe>;
394 fsl,tdm-framer-type = "e1";
395 fsl,tdm-id = <0>;
396 fsl,siram-entry-id = <0>;
397 fsl,tdm-interface;
398 };
399
400 ucc_serial: ucc@2200 {
401 compatible = "fsl,t1040-ucc-uart";
402 port-number = <0>;
403 rx-clock-name = "brg2";
404 tx-clock-name = "brg2";
405 };
406 };
369}; 407};