ASoC: rt5677: Reconfigure PLL1 after resume

Sometimes PLL1 stops working if the codec loses power
during suspend (when pow-ldo2 or reset gpio is used).
MX-7Bh(RT5677_PLL1_CTRL2) is cleared and won't be restored
by regcache since it's volatile. MX-7Bh has one status bit
and M code for PLL1. rt5677_set_dai_pll doesn't reconfigure
PLL1 after resume because it thinks the PLL params are not
changed.

This patch clears the cached PLL params at resume so that
rt5677_set_dai_pll can reconfigure the PLL after resume.

Signed-off-by: Ben Zhang <benzh@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>

1 files changed, 3 insertions, 0 deletions

diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
index f73fd125e49c..c404f515376e 100644
--- a/sound/soc/codecs/rt5677.c
+++ b/sound/soc/codecs/rt5677.c
@@ -4792,6 +4792,9 @@ static int rt5677_resume(struct snd_soc_codec *codec)
         struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 
         if (!rt5677->dsp_vad_en) {
+                rt5677->pll_src = 0;
+                rt5677->pll_in = 0;
+                rt5677->pll_out = 0;
                 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
                 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
                 if (rt5677->pow_ldo2 || rt5677->reset_pin)