aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorRob Clark <robdclark@gmail.com>2017-01-30 10:46:35 -0500
committerRob Clark <robdclark@gmail.com>2017-02-06 11:28:42 -0500
commit1a4a66ddc7b290ea2fd492c9c922ee7205d44724 (patch)
tree8eda878f36ba53d13f195c3f9544901e7f2df150
parent99743ae4c5f52f8f8ceb17783056fcc9b4f8b64c (diff)
drm/msm: remove qcom,gpu-pwrlevels bindings
The plan is to use the OPP bindings. For now, remove the documentation for qcom,gpu-pwrlevels, and make the driver fall back to a safe low clock if the node is not present. Note that no upstream dtb use this node. For now we keep compatibility with this node to avoid breaking compatibility with downstream android dt files. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/display/msm/gpu.txt15
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_device.c6
2 files changed, 4 insertions, 17 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 67d0a58dbb77..747b984c7210 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -12,12 +12,6 @@ Required properties:
12 * "mem_iface_clk" 12 * "mem_iface_clk"
13- qcom,chipid: gpu chip-id. Note this may become optional for future 13- qcom,chipid: gpu chip-id. Note this may become optional for future
14 devices if we can reliably read the chipid from hw 14 devices if we can reliably read the chipid from hw
15- qcom,gpu-pwrlevels: list of operating points
16 - compatible: "qcom,gpu-pwrlevels"
17 - for each qcom,gpu-pwrlevel:
18 - qcom,gpu-freq: requested gpu clock speed
19 - NOTE: downstream android driver defines additional parameters to
20 configure memory bandwidth scaling per OPP.
21 15
22Example: 16Example:
23 17
@@ -39,14 +33,5 @@ Example:
39 <&mmcc GFX3D_AHB_CLK>, 33 <&mmcc GFX3D_AHB_CLK>,
40 <&mmcc MMSS_IMEM_AHB_CLK>; 34 <&mmcc MMSS_IMEM_AHB_CLK>;
41 qcom,chipid = <0x03020100>; 35 qcom,chipid = <0x03020100>;
42 qcom,gpu-pwrlevels {
43 compatible = "qcom,gpu-pwrlevels";
44 qcom,gpu-pwrlevel@0 {
45 qcom,gpu-freq = <450000000>;
46 };
47 qcom,gpu-pwrlevel@1 {
48 qcom,gpu-freq = <27000000>;
49 };
50 };
51 }; 36 };
52}; 37};
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 893eb2b2531b..8d54cb764f77 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -224,8 +224,10 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
224 } 224 }
225 225
226 if (!config.fast_rate) { 226 if (!config.fast_rate) {
227 dev_err(dev, "could not find clk rates\n"); 227 dev_warn(dev, "could not find clk rates\n");
228 return -ENXIO; 228 /* This is a safe low speed for all devices: */
229 config.fast_rate = 200000000;
230 config.slow_rate = 27000000;
229 } 231 }
230 232
231 for (i = 0; i < ARRAY_SIZE(quirks); i++) 233 for (i = 0; i < ARRAY_SIZE(quirks); i++)