diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-06-23 19:23:30 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-06-23 19:23:30 -0400 |
commit | 1a13e36a79f25f4cf506258637e96a07ac1451f2 (patch) | |
tree | 35b55b9b2d45426584e1816bcad4e0fb4acc9e71 | |
parent | 36a1624d8844b6c165daf61649e6b68c02d0835f (diff) | |
parent | f778dad38a54ca5207d024b5ebe0e6d71b8bad83 (diff) |
Merge tag 'fbdev-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux
Pull fbdev updates from Tomi Valkeinen:
- ssd1307fb: various fixes and improvements, SSD1305 support
- use architecture agnostic functions instead of MTRR functions in
various fbdev drivers
- TI DRA7xx SoC display support (arch/arm/ side)
- OMAPDSS componentization to fix probing order issues
- OMAPDSS scaling fixes
- msm_fb: remove obsoleted driver
* tag 'fbdev-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: (77 commits)
msm: msm_fb: Remove dead code
OMAPDSS: HDMI: wait for framedone when stopping video
OMAPDSS: HDMI4: fix error handling
OMAPDSS: DISPC: scaler debug print
OMAPDSS: DISPC: do only y decimation on OMAP3
OMAPDSS: DISPC: check if scaling setup failed
OMAPDSS: DISPC: fix 64 bit issue in 5-tap
OMAPDSS: DISPC: fix row_inc for OMAP3
OMAPDSS: DISPC: add check for scaling limits
OMAPDSS: DISPC: fix check_horiz_timing_omap3 args
OMAPDSS: DISPC: fix predecimation for YUV modes
OMAPDSS: DISPC: work-around for errata i631
OMAPDSS: simplify submodule reg/unreg code
OMAPDSS: componentize omapdss
OMAPDSS: reorder uninit calls
OMAPDSS: remove uses of __init/__exit
OMAPDSS: fix dss_init_ports error handling
OMAPDSS: refactor dss probe function
OMAPDSS: move 'dss_initialized' to dss driver
fbdev: propagate result of fb_videomode_from_videomode()
...
85 files changed, 1311 insertions, 6680 deletions
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 7b8c1295fd90..53d87bad0adc 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt | |||
@@ -182,6 +182,7 @@ skyworks Skyworks Solutions, Inc. | |||
182 | smsc Standard Microsystems Corporation | 182 | smsc Standard Microsystems Corporation |
183 | snps Synopsys, Inc. | 183 | snps Synopsys, Inc. |
184 | solidrun SolidRun | 184 | solidrun SolidRun |
185 | solomon Solomon Systech Limited | ||
185 | sony Sony Corporation | 186 | sony Sony Corporation |
186 | spansion Spansion Inc. | 187 | spansion Spansion Inc. |
187 | sprd Spreadtrum Communications Inc. | 188 | sprd Spreadtrum Communications Inc. |
diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt b/Documentation/devicetree/bindings/video/ssd1307fb.txt index 7a125427ff4b..d1be78db63f5 100644 --- a/Documentation/devicetree/bindings/video/ssd1307fb.txt +++ b/Documentation/devicetree/bindings/video/ssd1307fb.txt | |||
@@ -2,7 +2,7 @@ | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for | 4 | - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for |
5 | now is i2c, and the supported chips are ssd1306 and ssd1307. | 5 | now is i2c, and the supported chips are ssd1305, ssd1306 and ssd1307. |
6 | - reg: Should contain address of the controller on the I2C bus. Most likely | 6 | - reg: Should contain address of the controller on the I2C bus. Most likely |
7 | 0x3c or 0x3d | 7 | 0x3c or 0x3d |
8 | - pwm: Should contain the pwm to use according to the OF device tree PWM | 8 | - pwm: Should contain the pwm to use according to the OF device tree PWM |
@@ -15,6 +15,16 @@ Required properties: | |||
15 | 15 | ||
16 | Optional properties: | 16 | Optional properties: |
17 | - reset-active-low: Is the reset gpio is active on physical low? | 17 | - reset-active-low: Is the reset gpio is active on physical low? |
18 | - solomon,segment-no-remap: Display needs normal (non-inverted) data column | ||
19 | to segment mapping | ||
20 | - solomon,com-seq: Display uses sequential COM pin configuration | ||
21 | - solomon,com-lrremap: Display uses left-right COM pin remap | ||
22 | - solomon,com-invdir: Display uses inverted COM pin scan direction | ||
23 | - solomon,com-offset: Number of the COM pin wired to the first display line | ||
24 | - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles. | ||
25 | - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles. | ||
26 | This needs to be the higher, the higher the capacitance | ||
27 | of the OLED's pixels is | ||
18 | 28 | ||
19 | [0]: Documentation/devicetree/bindings/pwm/pwm.txt | 29 | [0]: Documentation/devicetree/bindings/pwm/pwm.txt |
20 | 30 | ||
@@ -26,3 +36,14 @@ ssd1307: oled@3c { | |||
26 | reset-gpios = <&gpio2 7>; | 36 | reset-gpios = <&gpio2 7>; |
27 | reset-active-low; | 37 | reset-active-low; |
28 | }; | 38 | }; |
39 | |||
40 | ssd1306: oled@3c { | ||
41 | compatible = "solomon,ssd1306fb-i2c"; | ||
42 | reg = <0x3c>; | ||
43 | pwms = <&pwm 4 3000>; | ||
44 | reset-gpios = <&gpio2 7>; | ||
45 | reset-active-low; | ||
46 | solomon,com-lrremap; | ||
47 | solomon,com-invdir; | ||
48 | solomon,com-offset = <32>; | ||
49 | }; | ||
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index 7128fad991ac..a42cc377a862 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts | |||
@@ -19,6 +19,7 @@ | |||
19 | rtc0 = &mcp_rtc; | 19 | rtc0 = &mcp_rtc; |
20 | rtc1 = &tps659038_rtc; | 20 | rtc1 = &tps659038_rtc; |
21 | rtc2 = &rtc; | 21 | rtc2 = &rtc; |
22 | display0 = &hdmi0; | ||
22 | }; | 23 | }; |
23 | 24 | ||
24 | memory { | 25 | memory { |
@@ -103,6 +104,51 @@ | |||
103 | pinctrl-names = "default"; | 104 | pinctrl-names = "default"; |
104 | pinctrl-0 = <&extcon_usb2_pins>; | 105 | pinctrl-0 = <&extcon_usb2_pins>; |
105 | }; | 106 | }; |
107 | |||
108 | hdmi0: connector { | ||
109 | compatible = "hdmi-connector"; | ||
110 | label = "hdmi"; | ||
111 | |||
112 | type = "a"; | ||
113 | |||
114 | port { | ||
115 | hdmi_connector_in: endpoint { | ||
116 | remote-endpoint = <&tpd12s015_out>; | ||
117 | }; | ||
118 | }; | ||
119 | }; | ||
120 | |||
121 | tpd12s015: encoder { | ||
122 | compatible = "ti,tpd12s015"; | ||
123 | |||
124 | pinctrl-names = "default"; | ||
125 | pinctrl-0 = <&tpd12s015_pins>; | ||
126 | |||
127 | gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ | ||
128 | <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ | ||
129 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ | ||
130 | |||
131 | ports { | ||
132 | #address-cells = <1>; | ||
133 | #size-cells = <0>; | ||
134 | |||
135 | port@0 { | ||
136 | reg = <0>; | ||
137 | |||
138 | tpd12s015_in: endpoint { | ||
139 | remote-endpoint = <&hdmi_out>; | ||
140 | }; | ||
141 | }; | ||
142 | |||
143 | port@1 { | ||
144 | reg = <1>; | ||
145 | |||
146 | tpd12s015_out: endpoint { | ||
147 | remote-endpoint = <&hdmi_connector_in>; | ||
148 | }; | ||
149 | }; | ||
150 | }; | ||
151 | }; | ||
106 | }; | 152 | }; |
107 | 153 | ||
108 | &dra7_pmx_core { | 154 | &dra7_pmx_core { |
@@ -122,6 +168,13 @@ | |||
122 | >; | 168 | >; |
123 | }; | 169 | }; |
124 | 170 | ||
171 | hdmi_pins: pinmux_hdmi_pins { | ||
172 | pinctrl-single,pins = < | ||
173 | 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ | ||
174 | 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ | ||
175 | >; | ||
176 | }; | ||
177 | |||
125 | i2c3_pins_default: i2c3_pins_default { | 178 | i2c3_pins_default: i2c3_pins_default { |
126 | pinctrl-single,pins = < | 179 | pinctrl-single,pins = < |
127 | 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ | 180 | 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ |
@@ -278,6 +331,14 @@ | |||
278 | 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */ | 331 | 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */ |
279 | >; | 332 | >; |
280 | }; | 333 | }; |
334 | |||
335 | tpd12s015_pins: pinmux_tpd12s015_pins { | ||
336 | pinctrl-single,pins = < | ||
337 | 0x3b0 (PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */ | ||
338 | 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ | ||
339 | 0x370 (PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */ | ||
340 | >; | ||
341 | }; | ||
281 | }; | 342 | }; |
282 | 343 | ||
283 | &i2c1 { | 344 | &i2c1 { |
@@ -608,3 +669,23 @@ | |||
608 | }; | 669 | }; |
609 | }; | 670 | }; |
610 | }; | 671 | }; |
672 | |||
673 | &dss { | ||
674 | status = "ok"; | ||
675 | |||
676 | vdda_video-supply = <&ldoln_reg>; | ||
677 | }; | ||
678 | |||
679 | &hdmi { | ||
680 | status = "ok"; | ||
681 | vdda-supply = <&ldo3_reg>; | ||
682 | |||
683 | pinctrl-names = "default"; | ||
684 | pinctrl-0 = <&hdmi_pins>; | ||
685 | |||
686 | port { | ||
687 | hdmi_out: endpoint { | ||
688 | remote-endpoint = <&tpd12s015_in>; | ||
689 | }; | ||
690 | }; | ||
691 | }; | ||
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index f03a091cd076..8f1e25bcecbd 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi | |||
@@ -131,6 +131,11 @@ | |||
131 | regulator-max-microvolt = <3000000>; | 131 | regulator-max-microvolt = <3000000>; |
132 | }; | 132 | }; |
133 | }; | 133 | }; |
134 | |||
135 | scm_conf_clocks: clocks { | ||
136 | #address-cells = <1>; | ||
137 | #size-cells = <0>; | ||
138 | }; | ||
134 | }; | 139 | }; |
135 | 140 | ||
136 | dra7_pmx_core: pinmux@1400 { | 141 | dra7_pmx_core: pinmux@1400 { |
@@ -1469,6 +1474,44 @@ | |||
1469 | clocks = <&sys_clkin1>; | 1474 | clocks = <&sys_clkin1>; |
1470 | status = "disabled"; | 1475 | status = "disabled"; |
1471 | }; | 1476 | }; |
1477 | |||
1478 | dss: dss@58000000 { | ||
1479 | compatible = "ti,dra7-dss"; | ||
1480 | /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ | ||
1481 | /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ | ||
1482 | status = "disabled"; | ||
1483 | ti,hwmods = "dss_core"; | ||
1484 | /* CTRL_CORE_DSS_PLL_CONTROL */ | ||
1485 | syscon-pll-ctrl = <&scm_conf 0x538>; | ||
1486 | #address-cells = <1>; | ||
1487 | #size-cells = <1>; | ||
1488 | ranges; | ||
1489 | |||
1490 | dispc@58001000 { | ||
1491 | compatible = "ti,dra7-dispc"; | ||
1492 | reg = <0x58001000 0x1000>; | ||
1493 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | ||
1494 | ti,hwmods = "dss_dispc"; | ||
1495 | clocks = <&dss_dss_clk>; | ||
1496 | clock-names = "fck"; | ||
1497 | /* CTRL_CORE_SMA_SW_1 */ | ||
1498 | syscon-pol = <&scm_conf 0x534>; | ||
1499 | }; | ||
1500 | |||
1501 | hdmi: encoder@58060000 { | ||
1502 | compatible = "ti,dra7-hdmi"; | ||
1503 | reg = <0x58040000 0x200>, | ||
1504 | <0x58040200 0x80>, | ||
1505 | <0x58040300 0x80>, | ||
1506 | <0x58060000 0x19000>; | ||
1507 | reg-names = "wp", "pll", "phy", "core"; | ||
1508 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | ||
1509 | status = "disabled"; | ||
1510 | ti,hwmods = "dss_hdmi"; | ||
1511 | clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; | ||
1512 | clock-names = "fck", "sys_clk"; | ||
1513 | }; | ||
1514 | }; | ||
1472 | }; | 1515 | }; |
1473 | 1516 | ||
1474 | thermal_zones: thermal-zones { | 1517 | thermal_zones: thermal-zones { |
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index ce0390f081d9..4e1b60581782 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts | |||
@@ -19,6 +19,10 @@ | |||
19 | reg = <0x80000000 0x40000000>; /* 1024 MB */ | 19 | reg = <0x80000000 0x40000000>; /* 1024 MB */ |
20 | }; | 20 | }; |
21 | 21 | ||
22 | aliases { | ||
23 | display0 = &hdmi0; | ||
24 | }; | ||
25 | |||
22 | evm_3v3: fixedregulator-evm_3v3 { | 26 | evm_3v3: fixedregulator-evm_3v3 { |
23 | compatible = "regulator-fixed"; | 27 | compatible = "regulator-fixed"; |
24 | regulator-name = "evm_3v3"; | 28 | regulator-name = "evm_3v3"; |
@@ -35,6 +39,51 @@ | |||
35 | compatible = "linux,extcon-usb-gpio"; | 39 | compatible = "linux,extcon-usb-gpio"; |
36 | id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; | 40 | id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; |
37 | }; | 41 | }; |
42 | |||
43 | hdmi0: connector { | ||
44 | compatible = "hdmi-connector"; | ||
45 | label = "hdmi"; | ||
46 | |||
47 | type = "a"; | ||
48 | |||
49 | port { | ||
50 | hdmi_connector_in: endpoint { | ||
51 | remote-endpoint = <&tpd12s015_out>; | ||
52 | }; | ||
53 | }; | ||
54 | }; | ||
55 | |||
56 | tpd12s015: encoder { | ||
57 | compatible = "ti,tpd12s015"; | ||
58 | |||
59 | pinctrl-names = "default"; | ||
60 | pinctrl-0 = <&tpd12s015_pins>; | ||
61 | |||
62 | gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ | ||
63 | <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ | ||
64 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ | ||
65 | |||
66 | ports { | ||
67 | #address-cells = <1>; | ||
68 | #size-cells = <0>; | ||
69 | |||
70 | port@0 { | ||
71 | reg = <0>; | ||
72 | |||
73 | tpd12s015_in: endpoint { | ||
74 | remote-endpoint = <&hdmi_out>; | ||
75 | }; | ||
76 | }; | ||
77 | |||
78 | port@1 { | ||
79 | reg = <1>; | ||
80 | |||
81 | tpd12s015_out: endpoint { | ||
82 | remote-endpoint = <&hdmi_connector_in>; | ||
83 | }; | ||
84 | }; | ||
85 | }; | ||
86 | }; | ||
38 | }; | 87 | }; |
39 | 88 | ||
40 | &dra7_pmx_core { | 89 | &dra7_pmx_core { |
@@ -45,6 +94,13 @@ | |||
45 | >; | 94 | >; |
46 | }; | 95 | }; |
47 | 96 | ||
97 | i2c5_pins: pinmux_i2c5_pins { | ||
98 | pinctrl-single,pins = < | ||
99 | 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ | ||
100 | 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ | ||
101 | >; | ||
102 | }; | ||
103 | |||
48 | nand_default: nand_default { | 104 | nand_default: nand_default { |
49 | pinctrl-single,pins = < | 105 | pinctrl-single,pins = < |
50 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ | 106 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ |
@@ -142,6 +198,19 @@ | |||
142 | 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ | 198 | 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ |
143 | >; | 199 | >; |
144 | }; | 200 | }; |
201 | |||
202 | hdmi_pins: pinmux_hdmi_pins { | ||
203 | pinctrl-single,pins = < | ||
204 | 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ | ||
205 | 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ | ||
206 | >; | ||
207 | }; | ||
208 | |||
209 | tpd12s015_pins: pinmux_tpd12s015_pins { | ||
210 | pinctrl-single,pins = < | ||
211 | 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ | ||
212 | >; | ||
213 | }; | ||
145 | }; | 214 | }; |
146 | 215 | ||
147 | &i2c1 { | 216 | &i2c1 { |
@@ -277,6 +346,27 @@ | |||
277 | }; | 346 | }; |
278 | }; | 347 | }; |
279 | 348 | ||
349 | &i2c5 { | ||
350 | status = "okay"; | ||
351 | pinctrl-names = "default"; | ||
352 | pinctrl-0 = <&i2c5_pins>; | ||
353 | clock-frequency = <400000>; | ||
354 | |||
355 | pcf_hdmi: pcf8575@26 { | ||
356 | compatible = "nxp,pcf8575"; | ||
357 | reg = <0x26>; | ||
358 | gpio-controller; | ||
359 | #gpio-cells = <2>; | ||
360 | /* | ||
361 | * initial state is used here to keep the mdio interface | ||
362 | * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and | ||
363 | * VIN2_S0 driven high otherwise Ethernet stops working | ||
364 | * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 | ||
365 | */ | ||
366 | lines-initial-states = <0x0f2b>; | ||
367 | }; | ||
368 | }; | ||
369 | |||
280 | &uart1 { | 370 | &uart1 { |
281 | status = "okay"; | 371 | status = "okay"; |
282 | }; | 372 | }; |
@@ -566,3 +656,23 @@ | |||
566 | }; | 656 | }; |
567 | }; | 657 | }; |
568 | }; | 658 | }; |
659 | |||
660 | &dss { | ||
661 | status = "ok"; | ||
662 | |||
663 | vdda_video-supply = <&ldo5_reg>; | ||
664 | }; | ||
665 | |||
666 | &hdmi { | ||
667 | status = "ok"; | ||
668 | vdda-supply = <&ldo3_reg>; | ||
669 | |||
670 | pinctrl-names = "default"; | ||
671 | pinctrl-0 = <&hdmi_pins>; | ||
672 | |||
673 | port { | ||
674 | hdmi_out: endpoint { | ||
675 | remote-endpoint = <&tpd12s015_in>; | ||
676 | }; | ||
677 | }; | ||
678 | }; | ||
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index 03d742f8d572..eaca143faa77 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi | |||
@@ -34,3 +34,14 @@ | |||
34 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; | 34 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
35 | }; | 35 | }; |
36 | }; | 36 | }; |
37 | |||
38 | &dss { | ||
39 | reg = <0x58000000 0x80>, | ||
40 | <0x58004054 0x4>, | ||
41 | <0x58004300 0x20>; | ||
42 | reg-names = "dss", "pll1_clkctrl", "pll1"; | ||
43 | |||
44 | clocks = <&dss_dss_clk>, | ||
45 | <&dss_video1_clk>; | ||
46 | clock-names = "fck", "video1_clk"; | ||
47 | }; | ||
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index cc560a70926f..fa995d0ca1f2 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi | |||
@@ -73,3 +73,18 @@ | |||
73 | }; | 73 | }; |
74 | }; | 74 | }; |
75 | }; | 75 | }; |
76 | |||
77 | &dss { | ||
78 | reg = <0x58000000 0x80>, | ||
79 | <0x58004054 0x4>, | ||
80 | <0x58004300 0x20>, | ||
81 | <0x58005054 0x4>, | ||
82 | <0x58005300 0x20>; | ||
83 | reg-names = "dss", "pll1_clkctrl", "pll1", | ||
84 | "pll2_clkctrl", "pll2"; | ||
85 | |||
86 | clocks = <&dss_dss_clk>, | ||
87 | <&dss_video1_clk>, | ||
88 | <&dss_video2_clk>; | ||
89 | clock-names = "fck", "video1_clk", "video2_clk"; | ||
90 | }; | ||
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3b933f74d000..357bedeebfac 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi | |||
@@ -1531,6 +1531,7 @@ | |||
1531 | clocks = <&dpll_per_h12x2_ck>; | 1531 | clocks = <&dpll_per_h12x2_ck>; |
1532 | ti,bit-shift = <8>; | 1532 | ti,bit-shift = <8>; |
1533 | reg = <0x1120>; | 1533 | reg = <0x1120>; |
1534 | ti,set-rate-parent; | ||
1534 | }; | 1535 | }; |
1535 | 1536 | ||
1536 | dss_hdmi_clk: dss_hdmi_clk { | 1537 | dss_hdmi_clk: dss_hdmi_clk { |
@@ -2136,3 +2137,13 @@ | |||
2136 | clocks = <&dpll_usb_ck>; | 2137 | clocks = <&dpll_usb_ck>; |
2137 | }; | 2138 | }; |
2138 | }; | 2139 | }; |
2140 | |||
2141 | &scm_conf_clocks { | ||
2142 | dss_deshdcp_clk: dss_deshdcp_clk { | ||
2143 | #clock-cells = <0>; | ||
2144 | compatible = "ti,gate-clock"; | ||
2145 | clocks = <&l3_iclk_div>; | ||
2146 | ti,bit-shift = <0>; | ||
2147 | reg = <0x558>; | ||
2148 | }; | ||
2149 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index b04b6b8850a7..570aa339a05e 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts | |||
@@ -99,6 +99,9 @@ | |||
99 | solomon,height = <32>; | 99 | solomon,height = <32>; |
100 | solomon,width = <128>; | 100 | solomon,width = <128>; |
101 | solomon,page-offset = <0>; | 101 | solomon,page-offset = <0>; |
102 | solomon,com-lrremap; | ||
103 | solomon,com-invdir; | ||
104 | solomon,com-offset = <32>; | ||
102 | }; | 105 | }; |
103 | }; | 106 | }; |
104 | 107 | ||
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index f492ae147c6a..6ab13d18c636 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c | |||
@@ -287,6 +287,8 @@ static enum omapdss_version __init omap_display_get_version(void) | |||
287 | return OMAPDSS_VER_OMAP5; | 287 | return OMAPDSS_VER_OMAP5; |
288 | else if (soc_is_am43xx()) | 288 | else if (soc_is_am43xx()) |
289 | return OMAPDSS_VER_AM43xx; | 289 | return OMAPDSS_VER_AM43xx; |
290 | else if (soc_is_dra7xx()) | ||
291 | return OMAPDSS_VER_DRA7xx; | ||
290 | else | 292 | else |
291 | return OMAPDSS_VER_UNKNOWN; | 293 | return OMAPDSS_VER_UNKNOWN; |
292 | } | 294 | } |
@@ -568,25 +570,25 @@ void __init omapdss_early_init_of(void) | |||
568 | 570 | ||
569 | } | 571 | } |
570 | 572 | ||
573 | static const char * const omapdss_compat_names[] __initconst = { | ||
574 | "ti,omap2-dss", | ||
575 | "ti,omap3-dss", | ||
576 | "ti,omap4-dss", | ||
577 | "ti,omap5-dss", | ||
578 | "ti,dra7-dss", | ||
579 | }; | ||
580 | |||
571 | struct device_node * __init omapdss_find_dss_of_node(void) | 581 | struct device_node * __init omapdss_find_dss_of_node(void) |
572 | { | 582 | { |
573 | struct device_node *node; | 583 | struct device_node *node; |
584 | int i; | ||
574 | 585 | ||
575 | node = of_find_compatible_node(NULL, NULL, "ti,omap2-dss"); | 586 | for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) { |
576 | if (node) | 587 | node = of_find_compatible_node(NULL, NULL, |
577 | return node; | 588 | omapdss_compat_names[i]); |
578 | 589 | if (node) | |
579 | node = of_find_compatible_node(NULL, NULL, "ti,omap3-dss"); | 590 | return node; |
580 | if (node) | 591 | } |
581 | return node; | ||
582 | |||
583 | node = of_find_compatible_node(NULL, NULL, "ti,omap4-dss"); | ||
584 | if (node) | ||
585 | return node; | ||
586 | |||
587 | node = of_find_compatible_node(NULL, NULL, "ti,omap5-dss"); | ||
588 | if (node) | ||
589 | return node; | ||
590 | 592 | ||
591 | return NULL; | 593 | return NULL; |
592 | } | 594 | } |
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 0e64c2fac0b5..9961f95f52ae 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c | |||
@@ -49,6 +49,27 @@ | |||
49 | */ | 49 | */ |
50 | 50 | ||
51 | /* | 51 | /* |
52 | * 'dmm' class | ||
53 | * instance(s): dmm | ||
54 | */ | ||
55 | static struct omap_hwmod_class dra7xx_dmm_hwmod_class = { | ||
56 | .name = "dmm", | ||
57 | }; | ||
58 | |||
59 | /* dmm */ | ||
60 | static struct omap_hwmod dra7xx_dmm_hwmod = { | ||
61 | .name = "dmm", | ||
62 | .class = &dra7xx_dmm_hwmod_class, | ||
63 | .clkdm_name = "emif_clkdm", | ||
64 | .prcm = { | ||
65 | .omap4 = { | ||
66 | .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET, | ||
67 | .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET, | ||
68 | }, | ||
69 | }, | ||
70 | }; | ||
71 | |||
72 | /* | ||
52 | * 'l3' class | 73 | * 'l3' class |
53 | * instance(s): l3_instr, l3_main_1, l3_main_2 | 74 | * instance(s): l3_instr, l3_main_1, l3_main_2 |
54 | */ | 75 | */ |
@@ -438,6 +459,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |||
438 | { .role = "video2_clk", .clk = "dss_video2_clk" }, | 459 | { .role = "video2_clk", .clk = "dss_video2_clk" }, |
439 | { .role = "video1_clk", .clk = "dss_video1_clk" }, | 460 | { .role = "video1_clk", .clk = "dss_video1_clk" }, |
440 | { .role = "hdmi_clk", .clk = "dss_hdmi_clk" }, | 461 | { .role = "hdmi_clk", .clk = "dss_hdmi_clk" }, |
462 | { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" }, | ||
441 | }; | 463 | }; |
442 | 464 | ||
443 | static struct omap_hwmod dra7xx_dss_hwmod = { | 465 | static struct omap_hwmod dra7xx_dss_hwmod = { |
@@ -500,6 +522,7 @@ static struct omap_hwmod dra7xx_dss_dispc_hwmod = { | |||
500 | }, | 522 | }, |
501 | }, | 523 | }, |
502 | .dev_attr = &dss_dispc_dev_attr, | 524 | .dev_attr = &dss_dispc_dev_attr, |
525 | .parent_hwmod = &dra7xx_dss_hwmod, | ||
503 | }; | 526 | }; |
504 | 527 | ||
505 | /* | 528 | /* |
@@ -541,6 +564,7 @@ static struct omap_hwmod dra7xx_dss_hdmi_hwmod = { | |||
541 | }, | 564 | }, |
542 | .opt_clks = dss_hdmi_opt_clks, | 565 | .opt_clks = dss_hdmi_opt_clks, |
543 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | 566 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), |
567 | .parent_hwmod = &dra7xx_dss_hwmod, | ||
544 | }; | 568 | }; |
545 | 569 | ||
546 | /* | 570 | /* |
@@ -2321,6 +2345,14 @@ static struct omap_hwmod dra7xx_wd_timer2_hwmod = { | |||
2321 | * Interfaces | 2345 | * Interfaces |
2322 | */ | 2346 | */ |
2323 | 2347 | ||
2348 | /* l3_main_1 -> dmm */ | ||
2349 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = { | ||
2350 | .master = &dra7xx_l3_main_1_hwmod, | ||
2351 | .slave = &dra7xx_dmm_hwmod, | ||
2352 | .clk = "l3_iclk_div", | ||
2353 | .user = OCP_USER_SDMA, | ||
2354 | }; | ||
2355 | |||
2324 | /* l3_main_2 -> l3_instr */ | 2356 | /* l3_main_2 -> l3_instr */ |
2325 | static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = { | 2357 | static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = { |
2326 | .master = &dra7xx_l3_main_2_hwmod, | 2358 | .master = &dra7xx_l3_main_2_hwmod, |
@@ -3289,6 +3321,7 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { | |||
3289 | }; | 3321 | }; |
3290 | 3322 | ||
3291 | static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { | 3323 | static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { |
3324 | &dra7xx_l3_main_1__dmm, | ||
3292 | &dra7xx_l3_main_2__l3_instr, | 3325 | &dra7xx_l3_main_2__l3_instr, |
3293 | &dra7xx_l4_cfg__l3_main_1, | 3326 | &dra7xx_l4_cfg__l3_main_1, |
3294 | &dra7xx_mpu__l3_main_1, | 3327 | &dra7xx_mpu__l3_main_1, |
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 5d2217ae4478..63b8323df918 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c | |||
@@ -305,13 +305,14 @@ static struct ti_dt_clk dra7xx_clks[] = { | |||
305 | DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"), | 305 | DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"), |
306 | DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"), | 306 | DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"), |
307 | DT_CLK(NULL, "sys_clkin", "sys_clkin1"), | 307 | DT_CLK(NULL, "sys_clkin", "sys_clkin1"), |
308 | DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"), | ||
308 | { .node_name = NULL }, | 309 | { .node_name = NULL }, |
309 | }; | 310 | }; |
310 | 311 | ||
311 | int __init dra7xx_dt_clk_init(void) | 312 | int __init dra7xx_dt_clk_init(void) |
312 | { | 313 | { |
313 | int rc; | 314 | int rc; |
314 | struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; | 315 | struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *hdcp_ck; |
315 | 316 | ||
316 | ti_dt_clocks_register(dra7xx_clks); | 317 | ti_dt_clocks_register(dra7xx_clks); |
317 | 318 | ||
@@ -347,5 +348,10 @@ int __init dra7xx_dt_clk_init(void) | |||
347 | if (rc) | 348 | if (rc) |
348 | pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); | 349 | pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); |
349 | 350 | ||
351 | hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); | ||
352 | rc = clk_prepare_enable(hdcp_ck); | ||
353 | if (rc) | ||
354 | pr_err("%s: failed to set dss_deshdcp_clk\n", __func__); | ||
355 | |||
350 | return rc; | 356 | return rc; |
351 | } | 357 | } |
diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c index a6ab9299813c..bb4e96255974 100644 --- a/drivers/video/console/newport_con.c +++ b/drivers/video/console/newport_con.c | |||
@@ -687,7 +687,7 @@ static int newport_scroll(struct vc_data *vc, int t, int b, int dir, | |||
687 | static void newport_bmove(struct vc_data *vc, int sy, int sx, int dy, | 687 | static void newport_bmove(struct vc_data *vc, int sy, int sx, int dy, |
688 | int dx, int h, int w) | 688 | int dx, int h, int w) |
689 | { | 689 | { |
690 | short xs, ys, xe, ye, xoffs, yoffs, tmp; | 690 | short xs, ys, xe, ye, xoffs, yoffs; |
691 | 691 | ||
692 | xs = sx << 3; | 692 | xs = sx << 3; |
693 | xe = ((sx + w) << 3) - 1; | 693 | xe = ((sx + w) << 3) - 1; |
@@ -701,9 +701,7 @@ static void newport_bmove(struct vc_data *vc, int sy, int sx, int dy, | |||
701 | yoffs = (dy - sy) << 4; | 701 | yoffs = (dy - sy) << 4; |
702 | if (xoffs > 0) { | 702 | if (xoffs > 0) { |
703 | /* move to the right, exchange starting points */ | 703 | /* move to the right, exchange starting points */ |
704 | tmp = xe; | 704 | swap(xe, xs); |
705 | xe = xs; | ||
706 | xs = tmp; | ||
707 | } | 705 | } |
708 | newport_wait(npregs); | 706 | newport_wait(npregs); |
709 | npregs->set.drawmode0 = (NPORT_DMODE0_S2S | NPORT_DMODE0_BLOCK | | 707 | npregs->set.drawmode0 = (NPORT_DMODE0_S2S | NPORT_DMODE0_BLOCK | |
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index 109462303087..2d98de535e0f 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig | |||
@@ -2326,13 +2326,6 @@ config FB_PRE_INIT_FB | |||
2326 | Select this option if display contents should be inherited as set by | 2326 | Select this option if display contents should be inherited as set by |
2327 | the bootloader. | 2327 | the bootloader. |
2328 | 2328 | ||
2329 | config FB_MSM | ||
2330 | tristate "MSM Framebuffer support" | ||
2331 | depends on FB && ARCH_MSM | ||
2332 | select FB_CFB_FILLRECT | ||
2333 | select FB_CFB_COPYAREA | ||
2334 | select FB_CFB_IMAGEBLIT | ||
2335 | |||
2336 | config FB_MX3 | 2329 | config FB_MX3 |
2337 | tristate "MX3 Framebuffer support" | 2330 | tristate "MX3 Framebuffer support" |
2338 | depends on FB && MX3_IPU | 2331 | depends on FB && MX3_IPU |
@@ -2478,6 +2471,7 @@ config FB_SSD1307 | |||
2478 | select FB_SYS_IMAGEBLIT | 2471 | select FB_SYS_IMAGEBLIT |
2479 | select FB_DEFERRED_IO | 2472 | select FB_DEFERRED_IO |
2480 | select PWM | 2473 | select PWM |
2474 | select FB_BACKLIGHT | ||
2481 | help | 2475 | help |
2482 | This driver implements support for the Solomon SSD1307 | 2476 | This driver implements support for the Solomon SSD1307 |
2483 | OLED controller over I2C. | 2477 | OLED controller over I2C. |
diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile index 1979afffccfe..cecea5063a80 100644 --- a/drivers/video/fbdev/Makefile +++ b/drivers/video/fbdev/Makefile | |||
@@ -126,7 +126,6 @@ obj-y += omap2/ | |||
126 | obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o | 126 | obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o |
127 | obj-$(CONFIG_FB_CARMINE) += carminefb.o | 127 | obj-$(CONFIG_FB_CARMINE) += carminefb.o |
128 | obj-$(CONFIG_FB_MB862XX) += mb862xx/ | 128 | obj-$(CONFIG_FB_MB862XX) += mb862xx/ |
129 | obj-$(CONFIG_FB_MSM) += msm/ | ||
130 | obj-$(CONFIG_FB_NUC900) += nuc900fb.o | 129 | obj-$(CONFIG_FB_NUC900) += nuc900fb.o |
131 | obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o | 130 | obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o |
132 | obj-$(CONFIG_FB_PUV3_UNIGFX) += fb-puv3.o | 131 | obj-$(CONFIG_FB_PUV3_UNIGFX) += fb-puv3.o |
diff --git a/drivers/video/fbdev/amifb.c b/drivers/video/fbdev/amifb.c index ee3a703acf23..1d702e13aaff 100644 --- a/drivers/video/fbdev/amifb.c +++ b/drivers/video/fbdev/amifb.c | |||
@@ -2052,7 +2052,7 @@ static void ami_set_sprite(const struct amifb_par *par) | |||
2052 | { | 2052 | { |
2053 | copins *copl, *cops; | 2053 | copins *copl, *cops; |
2054 | u_short hs, vs, ve; | 2054 | u_short hs, vs, ve; |
2055 | u_long pl, ps, pt; | 2055 | u_long pl, ps; |
2056 | short mx, my; | 2056 | short mx, my; |
2057 | 2057 | ||
2058 | cops = copdisplay.list[currentcop][0]; | 2058 | cops = copdisplay.list[currentcop][0]; |
@@ -2078,7 +2078,7 @@ static void ami_set_sprite(const struct amifb_par *par) | |||
2078 | if (mod2(vs)) { | 2078 | if (mod2(vs)) { |
2079 | lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve); | 2079 | lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve); |
2080 | shfsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs + 1, hs, ve + 1); | 2080 | shfsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs + 1, hs, ve + 1); |
2081 | pt = pl; pl = ps; ps = pt; | 2081 | swap(pl, ps); |
2082 | } else { | 2082 | } else { |
2083 | lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve + 1); | 2083 | lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve + 1); |
2084 | shfsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs + 1, hs, ve); | 2084 | shfsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs + 1, hs, ve); |
diff --git a/drivers/video/fbdev/atmel_lcdfb.c b/drivers/video/fbdev/atmel_lcdfb.c index 94a8d04e60f9..abadc490fa1f 100644 --- a/drivers/video/fbdev/atmel_lcdfb.c +++ b/drivers/video/fbdev/atmel_lcdfb.c | |||
@@ -1266,7 +1266,8 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev) | |||
1266 | goto stop_clk; | 1266 | goto stop_clk; |
1267 | } | 1267 | } |
1268 | 1268 | ||
1269 | info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); | 1269 | info->screen_base = ioremap_wc(info->fix.smem_start, |
1270 | info->fix.smem_len); | ||
1270 | if (!info->screen_base) { | 1271 | if (!info->screen_base) { |
1271 | ret = -ENOMEM; | 1272 | ret = -ENOMEM; |
1272 | goto release_intmem; | 1273 | goto release_intmem; |
diff --git a/drivers/video/fbdev/aty/aty128fb.c b/drivers/video/fbdev/aty/aty128fb.c index 0156954bf340..c42ce2fdfd44 100644 --- a/drivers/video/fbdev/aty/aty128fb.c +++ b/drivers/video/fbdev/aty/aty128fb.c | |||
@@ -80,10 +80,6 @@ | |||
80 | #include <asm/btext.h> | 80 | #include <asm/btext.h> |
81 | #endif /* CONFIG_BOOTX_TEXT */ | 81 | #endif /* CONFIG_BOOTX_TEXT */ |
82 | 82 | ||
83 | #ifdef CONFIG_MTRR | ||
84 | #include <asm/mtrr.h> | ||
85 | #endif | ||
86 | |||
87 | #include <video/aty128.h> | 83 | #include <video/aty128.h> |
88 | 84 | ||
89 | /* Debug flag */ | 85 | /* Debug flag */ |
@@ -399,10 +395,7 @@ static int default_cmode = CMODE_8; | |||
399 | 395 | ||
400 | static int default_crt_on = 0; | 396 | static int default_crt_on = 0; |
401 | static int default_lcd_on = 1; | 397 | static int default_lcd_on = 1; |
402 | |||
403 | #ifdef CONFIG_MTRR | ||
404 | static bool mtrr = true; | 398 | static bool mtrr = true; |
405 | #endif | ||
406 | 399 | ||
407 | #ifdef CONFIG_FB_ATY128_BACKLIGHT | 400 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
408 | #ifdef CONFIG_PMAC_BACKLIGHT | 401 | #ifdef CONFIG_PMAC_BACKLIGHT |
@@ -456,9 +449,7 @@ struct aty128fb_par { | |||
456 | u32 vram_size; /* onboard video ram */ | 449 | u32 vram_size; /* onboard video ram */ |
457 | int chip_gen; | 450 | int chip_gen; |
458 | const struct aty128_meminfo *mem; /* onboard mem info */ | 451 | const struct aty128_meminfo *mem; /* onboard mem info */ |
459 | #ifdef CONFIG_MTRR | 452 | int wc_cookie; |
460 | struct { int vram; int vram_valid; } mtrr; | ||
461 | #endif | ||
462 | int blitter_may_be_busy; | 453 | int blitter_may_be_busy; |
463 | int fifo_slots; /* free slots in FIFO (64 max) */ | 454 | int fifo_slots; /* free slots in FIFO (64 max) */ |
464 | 455 | ||
@@ -1725,12 +1716,10 @@ static int aty128fb_setup(char *options) | |||
1725 | #endif | 1716 | #endif |
1726 | continue; | 1717 | continue; |
1727 | } | 1718 | } |
1728 | #ifdef CONFIG_MTRR | ||
1729 | if(!strncmp(this_opt, "nomtrr", 6)) { | 1719 | if(!strncmp(this_opt, "nomtrr", 6)) { |
1730 | mtrr = 0; | 1720 | mtrr = 0; |
1731 | continue; | 1721 | continue; |
1732 | } | 1722 | } |
1733 | #endif | ||
1734 | #ifdef CONFIG_PPC_PMAC | 1723 | #ifdef CONFIG_PPC_PMAC |
1735 | /* vmode and cmode deprecated */ | 1724 | /* vmode and cmode deprecated */ |
1736 | if (!strncmp(this_opt, "vmode:", 6)) { | 1725 | if (!strncmp(this_opt, "vmode:", 6)) { |
@@ -2133,7 +2122,7 @@ static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2133 | par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; | 2122 | par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; |
2134 | 2123 | ||
2135 | /* Virtualize the framebuffer */ | 2124 | /* Virtualize the framebuffer */ |
2136 | info->screen_base = ioremap(fb_addr, par->vram_size); | 2125 | info->screen_base = ioremap_wc(fb_addr, par->vram_size); |
2137 | if (!info->screen_base) | 2126 | if (!info->screen_base) |
2138 | goto err_unmap_out; | 2127 | goto err_unmap_out; |
2139 | 2128 | ||
@@ -2170,15 +2159,9 @@ static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2170 | if (!aty128_init(pdev, ent)) | 2159 | if (!aty128_init(pdev, ent)) |
2171 | goto err_out; | 2160 | goto err_out; |
2172 | 2161 | ||
2173 | #ifdef CONFIG_MTRR | 2162 | if (mtrr) |
2174 | if (mtrr) { | 2163 | par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, |
2175 | par->mtrr.vram = mtrr_add(info->fix.smem_start, | 2164 | par->vram_size); |
2176 | par->vram_size, MTRR_TYPE_WRCOMB, 1); | ||
2177 | par->mtrr.vram_valid = 1; | ||
2178 | /* let there be speed */ | ||
2179 | printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n"); | ||
2180 | } | ||
2181 | #endif /* CONFIG_MTRR */ | ||
2182 | return 0; | 2165 | return 0; |
2183 | 2166 | ||
2184 | err_out: | 2167 | err_out: |
@@ -2212,11 +2195,7 @@ static void aty128_remove(struct pci_dev *pdev) | |||
2212 | aty128_bl_exit(info->bl_dev); | 2195 | aty128_bl_exit(info->bl_dev); |
2213 | #endif | 2196 | #endif |
2214 | 2197 | ||
2215 | #ifdef CONFIG_MTRR | 2198 | arch_phys_wc_del(par->wc_cookie); |
2216 | if (par->mtrr.vram_valid) | ||
2217 | mtrr_del(par->mtrr.vram, info->fix.smem_start, | ||
2218 | par->vram_size); | ||
2219 | #endif /* CONFIG_MTRR */ | ||
2220 | iounmap(par->regbase); | 2199 | iounmap(par->regbase); |
2221 | iounmap(info->screen_base); | 2200 | iounmap(info->screen_base); |
2222 | 2201 | ||
@@ -2625,8 +2604,5 @@ MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); | |||
2625 | MODULE_LICENSE("GPL"); | 2604 | MODULE_LICENSE("GPL"); |
2626 | module_param(mode_option, charp, 0); | 2605 | module_param(mode_option, charp, 0); |
2627 | MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); | 2606 | MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); |
2628 | #ifdef CONFIG_MTRR | ||
2629 | module_param_named(nomtrr, mtrr, invbool, 0); | 2607 | module_param_named(nomtrr, mtrr, invbool, 0); |
2630 | MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); | 2608 | MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); |
2631 | #endif | ||
2632 | |||
diff --git a/drivers/video/fbdev/aty/radeon_base.c b/drivers/video/fbdev/aty/radeon_base.c index 01237c8fcdc6..2bdb070707e4 100644 --- a/drivers/video/fbdev/aty/radeon_base.c +++ b/drivers/video/fbdev/aty/radeon_base.c | |||
@@ -85,10 +85,6 @@ | |||
85 | 85 | ||
86 | #endif /* CONFIG_PPC */ | 86 | #endif /* CONFIG_PPC */ |
87 | 87 | ||
88 | #ifdef CONFIG_MTRR | ||
89 | #include <asm/mtrr.h> | ||
90 | #endif | ||
91 | |||
92 | #include <video/radeon.h> | 88 | #include <video/radeon.h> |
93 | #include <linux/radeonfb.h> | 89 | #include <linux/radeonfb.h> |
94 | 90 | ||
@@ -271,9 +267,7 @@ static bool mirror = 0; | |||
271 | static int panel_yres = 0; | 267 | static int panel_yres = 0; |
272 | static bool force_dfp = 0; | 268 | static bool force_dfp = 0; |
273 | static bool force_measure_pll = 0; | 269 | static bool force_measure_pll = 0; |
274 | #ifdef CONFIG_MTRR | ||
275 | static bool nomtrr = 0; | 270 | static bool nomtrr = 0; |
276 | #endif | ||
277 | static bool force_sleep; | 271 | static bool force_sleep; |
278 | static bool ignore_devlist; | 272 | static bool ignore_devlist; |
279 | #ifdef CONFIG_PMAC_BACKLIGHT | 273 | #ifdef CONFIG_PMAC_BACKLIGHT |
@@ -2260,8 +2254,8 @@ static int radeonfb_pci_register(struct pci_dev *pdev, | |||
2260 | rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); | 2254 | rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); |
2261 | 2255 | ||
2262 | do { | 2256 | do { |
2263 | rinfo->fb_base = ioremap (rinfo->fb_base_phys, | 2257 | rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys, |
2264 | rinfo->mapped_vram); | 2258 | rinfo->mapped_vram); |
2265 | } while (rinfo->fb_base == NULL && | 2259 | } while (rinfo->fb_base == NULL && |
2266 | ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM)); | 2260 | ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM)); |
2267 | 2261 | ||
@@ -2359,11 +2353,9 @@ static int radeonfb_pci_register(struct pci_dev *pdev, | |||
2359 | goto err_unmap_fb; | 2353 | goto err_unmap_fb; |
2360 | } | 2354 | } |
2361 | 2355 | ||
2362 | #ifdef CONFIG_MTRR | 2356 | if (!nomtrr) |
2363 | rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys, | 2357 | rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys, |
2364 | rinfo->video_ram, | 2358 | rinfo->video_ram); |
2365 | MTRR_TYPE_WRCOMB, 1); | ||
2366 | #endif | ||
2367 | 2359 | ||
2368 | if (backlight) | 2360 | if (backlight) |
2369 | radeonfb_bl_init(rinfo); | 2361 | radeonfb_bl_init(rinfo); |
@@ -2428,12 +2420,7 @@ static void radeonfb_pci_unregister(struct pci_dev *pdev) | |||
2428 | #endif | 2420 | #endif |
2429 | 2421 | ||
2430 | del_timer_sync(&rinfo->lvds_timer); | 2422 | del_timer_sync(&rinfo->lvds_timer); |
2431 | 2423 | arch_phys_wc_del(rinfo->wc_cookie); | |
2432 | #ifdef CONFIG_MTRR | ||
2433 | if (rinfo->mtrr_hdl >= 0) | ||
2434 | mtrr_del(rinfo->mtrr_hdl, 0, 0); | ||
2435 | #endif | ||
2436 | |||
2437 | unregister_framebuffer(info); | 2424 | unregister_framebuffer(info); |
2438 | 2425 | ||
2439 | radeonfb_bl_exit(rinfo); | 2426 | radeonfb_bl_exit(rinfo); |
@@ -2489,10 +2476,8 @@ static int __init radeonfb_setup (char *options) | |||
2489 | panel_yres = simple_strtoul((this_opt+11), NULL, 0); | 2476 | panel_yres = simple_strtoul((this_opt+11), NULL, 0); |
2490 | } else if (!strncmp(this_opt, "backlight:", 10)) { | 2477 | } else if (!strncmp(this_opt, "backlight:", 10)) { |
2491 | backlight = simple_strtoul(this_opt+10, NULL, 0); | 2478 | backlight = simple_strtoul(this_opt+10, NULL, 0); |
2492 | #ifdef CONFIG_MTRR | ||
2493 | } else if (!strncmp(this_opt, "nomtrr", 6)) { | 2479 | } else if (!strncmp(this_opt, "nomtrr", 6)) { |
2494 | nomtrr = 1; | 2480 | nomtrr = 1; |
2495 | #endif | ||
2496 | } else if (!strncmp(this_opt, "nomodeset", 9)) { | 2481 | } else if (!strncmp(this_opt, "nomodeset", 9)) { |
2497 | nomodeset = 1; | 2482 | nomodeset = 1; |
2498 | } else if (!strncmp(this_opt, "force_measure_pll", 17)) { | 2483 | } else if (!strncmp(this_opt, "force_measure_pll", 17)) { |
@@ -2552,10 +2537,8 @@ module_param(monitor_layout, charp, 0); | |||
2552 | MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); | 2537 | MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); |
2553 | module_param(force_measure_pll, bool, 0); | 2538 | module_param(force_measure_pll, bool, 0); |
2554 | MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); | 2539 | MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); |
2555 | #ifdef CONFIG_MTRR | ||
2556 | module_param(nomtrr, bool, 0); | 2540 | module_param(nomtrr, bool, 0); |
2557 | MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); | 2541 | MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); |
2558 | #endif | ||
2559 | module_param(panel_yres, int, 0); | 2542 | module_param(panel_yres, int, 0); |
2560 | MODULE_PARM_DESC(panel_yres, "int: set panel yres"); | 2543 | MODULE_PARM_DESC(panel_yres, "int: set panel yres"); |
2561 | module_param(mode_option, charp, 0); | 2544 | module_param(mode_option, charp, 0); |
diff --git a/drivers/video/fbdev/aty/radeonfb.h b/drivers/video/fbdev/aty/radeonfb.h index 039def41c920..5bc1944ea1a9 100644 --- a/drivers/video/fbdev/aty/radeonfb.h +++ b/drivers/video/fbdev/aty/radeonfb.h | |||
@@ -340,7 +340,7 @@ struct radeonfb_info { | |||
340 | 340 | ||
341 | struct pll_info pll; | 341 | struct pll_info pll; |
342 | 342 | ||
343 | int mtrr_hdl; | 343 | int wc_cookie; |
344 | 344 | ||
345 | u32 save_regs[100]; | 345 | u32 save_regs[100]; |
346 | int asleep; | 346 | int asleep; |
diff --git a/drivers/video/fbdev/core/Makefile b/drivers/video/fbdev/core/Makefile index 67f28e20a892..23d86a8b7d7b 100644 --- a/drivers/video/fbdev/core/Makefile +++ b/drivers/video/fbdev/core/Makefile | |||
@@ -3,6 +3,7 @@ obj-$(CONFIG_FB_CMDLINE) += fb_cmdline.o | |||
3 | obj-$(CONFIG_FB) += fb.o | 3 | obj-$(CONFIG_FB) += fb.o |
4 | fb-y := fbmem.o fbmon.o fbcmap.o fbsysfs.o \ | 4 | fb-y := fbmem.o fbmon.o fbcmap.o fbsysfs.o \ |
5 | modedb.o fbcvt.o | 5 | modedb.o fbcvt.o |
6 | fb-$(CONFIG_FB_DEFERRED_IO) += fb_defio.o | ||
6 | fb-objs := $(fb-y) | 7 | fb-objs := $(fb-y) |
7 | 8 | ||
8 | obj-$(CONFIG_FB_CFB_FILLRECT) += cfbfillrect.o | 9 | obj-$(CONFIG_FB_CFB_FILLRECT) += cfbfillrect.o |
@@ -14,4 +15,3 @@ obj-$(CONFIG_FB_SYS_IMAGEBLIT) += sysimgblt.o | |||
14 | obj-$(CONFIG_FB_SYS_FOPS) += fb_sys_fops.o | 15 | obj-$(CONFIG_FB_SYS_FOPS) += fb_sys_fops.o |
15 | obj-$(CONFIG_FB_SVGALIB) += svgalib.o | 16 | obj-$(CONFIG_FB_SVGALIB) += svgalib.o |
16 | obj-$(CONFIG_FB_DDC) += fb_ddc.o | 17 | obj-$(CONFIG_FB_DDC) += fb_ddc.o |
17 | obj-$(CONFIG_FB_DEFERRED_IO) += fb_defio.o | ||
diff --git a/drivers/video/fbdev/core/fb_defio.c b/drivers/video/fbdev/core/fb_defio.c index d6cab1fd9a47..3fc63c208d08 100644 --- a/drivers/video/fbdev/core/fb_defio.c +++ b/drivers/video/fbdev/core/fb_defio.c | |||
@@ -242,5 +242,3 @@ void fb_deferred_io_cleanup(struct fb_info *info) | |||
242 | mutex_destroy(&fbdefio->lock); | 242 | mutex_destroy(&fbdefio->lock); |
243 | } | 243 | } |
244 | EXPORT_SYMBOL_GPL(fb_deferred_io_cleanup); | 244 | EXPORT_SYMBOL_GPL(fb_deferred_io_cleanup); |
245 | |||
246 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/fbdev/core/fbmon.c b/drivers/video/fbdev/core/fbmon.c index 01ef1b953390..d787533d9c8b 100644 --- a/drivers/video/fbdev/core/fbmon.c +++ b/drivers/video/fbdev/core/fbmon.c | |||
@@ -1475,7 +1475,9 @@ int of_get_fb_videomode(struct device_node *np, struct fb_videomode *fb, | |||
1475 | if (ret) | 1475 | if (ret) |
1476 | return ret; | 1476 | return ret; |
1477 | 1477 | ||
1478 | fb_videomode_from_videomode(&vm, fb); | 1478 | ret = fb_videomode_from_videomode(&vm, fb); |
1479 | if (ret) | ||
1480 | return ret; | ||
1479 | 1481 | ||
1480 | pr_debug("%s: got %dx%d display mode from %s\n", | 1482 | pr_debug("%s: got %dx%d display mode from %s\n", |
1481 | of_node_full_name(np), vm.hactive, vm.vactive, np->name); | 1483 | of_node_full_name(np), vm.hactive, vm.vactive, np->name); |
diff --git a/drivers/video/fbdev/gbefb.c b/drivers/video/fbdev/gbefb.c index 6d9ef39810c8..b63d55f481fa 100644 --- a/drivers/video/fbdev/gbefb.c +++ b/drivers/video/fbdev/gbefb.c | |||
@@ -22,9 +22,6 @@ | |||
22 | #include <linux/module.h> | 22 | #include <linux/module.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | 24 | ||
25 | #ifdef CONFIG_X86 | ||
26 | #include <asm/mtrr.h> | ||
27 | #endif | ||
28 | #ifdef CONFIG_MIPS | 25 | #ifdef CONFIG_MIPS |
29 | #include <asm/addrspace.h> | 26 | #include <asm/addrspace.h> |
30 | #endif | 27 | #endif |
@@ -38,6 +35,7 @@ static struct sgi_gbe *gbe; | |||
38 | struct gbefb_par { | 35 | struct gbefb_par { |
39 | struct fb_var_screeninfo var; | 36 | struct fb_var_screeninfo var; |
40 | struct gbe_timing_info timing; | 37 | struct gbe_timing_info timing; |
38 | int wc_cookie; | ||
41 | int valid; | 39 | int valid; |
42 | }; | 40 | }; |
43 | 41 | ||
@@ -1175,8 +1173,8 @@ static int gbefb_probe(struct platform_device *p_dev) | |||
1175 | 1173 | ||
1176 | if (gbe_mem_phys) { | 1174 | if (gbe_mem_phys) { |
1177 | /* memory was allocated at boot time */ | 1175 | /* memory was allocated at boot time */ |
1178 | gbe_mem = devm_ioremap_nocache(&p_dev->dev, gbe_mem_phys, | 1176 | gbe_mem = devm_ioremap_wc(&p_dev->dev, gbe_mem_phys, |
1179 | gbe_mem_size); | 1177 | gbe_mem_size); |
1180 | if (!gbe_mem) { | 1178 | if (!gbe_mem) { |
1181 | printk(KERN_ERR "gbefb: couldn't map framebuffer\n"); | 1179 | printk(KERN_ERR "gbefb: couldn't map framebuffer\n"); |
1182 | ret = -ENOMEM; | 1180 | ret = -ENOMEM; |
@@ -1187,8 +1185,8 @@ static int gbefb_probe(struct platform_device *p_dev) | |||
1187 | } else { | 1185 | } else { |
1188 | /* try to allocate memory with the classical allocator | 1186 | /* try to allocate memory with the classical allocator |
1189 | * this has high chance to fail on low memory machines */ | 1187 | * this has high chance to fail on low memory machines */ |
1190 | gbe_mem = dma_alloc_coherent(NULL, gbe_mem_size, &gbe_dma_addr, | 1188 | gbe_mem = dma_alloc_writecombine(NULL, gbe_mem_size, |
1191 | GFP_KERNEL); | 1189 | &gbe_dma_addr, GFP_KERNEL); |
1192 | if (!gbe_mem) { | 1190 | if (!gbe_mem) { |
1193 | printk(KERN_ERR "gbefb: couldn't allocate framebuffer memory\n"); | 1191 | printk(KERN_ERR "gbefb: couldn't allocate framebuffer memory\n"); |
1194 | ret = -ENOMEM; | 1192 | ret = -ENOMEM; |
@@ -1198,9 +1196,8 @@ static int gbefb_probe(struct platform_device *p_dev) | |||
1198 | gbe_mem_phys = (unsigned long) gbe_dma_addr; | 1196 | gbe_mem_phys = (unsigned long) gbe_dma_addr; |
1199 | } | 1197 | } |
1200 | 1198 | ||
1201 | #ifdef CONFIG_X86 | 1199 | par = info->par; |
1202 | mtrr_add(gbe_mem_phys, gbe_mem_size, MTRR_TYPE_WRCOMB, 1); | 1200 | par->wc_cookie = arch_phys_wc_add(gbe_mem_phys, gbe_mem_size); |
1203 | #endif | ||
1204 | 1201 | ||
1205 | /* map framebuffer memory into tiles table */ | 1202 | /* map framebuffer memory into tiles table */ |
1206 | for (i = 0; i < (gbe_mem_size >> TILE_SHIFT); i++) | 1203 | for (i = 0; i < (gbe_mem_size >> TILE_SHIFT); i++) |
@@ -1215,7 +1212,6 @@ static int gbefb_probe(struct platform_device *p_dev) | |||
1215 | /* reset GBE */ | 1212 | /* reset GBE */ |
1216 | gbe_reset(); | 1213 | gbe_reset(); |
1217 | 1214 | ||
1218 | par = info->par; | ||
1219 | /* turn on default video mode */ | 1215 | /* turn on default video mode */ |
1220 | if (fb_find_mode(&par->var, info, mode_option, NULL, 0, | 1216 | if (fb_find_mode(&par->var, info, mode_option, NULL, 0, |
1221 | default_mode, 8) == 0) | 1217 | default_mode, 8) == 0) |
@@ -1240,8 +1236,9 @@ static int gbefb_probe(struct platform_device *p_dev) | |||
1240 | return 0; | 1236 | return 0; |
1241 | 1237 | ||
1242 | out_gbe_unmap: | 1238 | out_gbe_unmap: |
1239 | arch_phys_wc_del(par->wc_cookie); | ||
1243 | if (gbe_dma_addr) | 1240 | if (gbe_dma_addr) |
1244 | dma_free_coherent(NULL, gbe_mem_size, gbe_mem, gbe_mem_phys); | 1241 | dma_free_writecombine(NULL, gbe_mem_size, gbe_mem, gbe_mem_phys); |
1245 | out_tiles_free: | 1242 | out_tiles_free: |
1246 | dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t), | 1243 | dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t), |
1247 | (void *)gbe_tiles.cpu, gbe_tiles.dma); | 1244 | (void *)gbe_tiles.cpu, gbe_tiles.dma); |
@@ -1256,11 +1253,13 @@ out_release_framebuffer: | |||
1256 | static int gbefb_remove(struct platform_device* p_dev) | 1253 | static int gbefb_remove(struct platform_device* p_dev) |
1257 | { | 1254 | { |
1258 | struct fb_info *info = platform_get_drvdata(p_dev); | 1255 | struct fb_info *info = platform_get_drvdata(p_dev); |
1256 | struct gbefb_par *par = info->par; | ||
1259 | 1257 | ||
1260 | unregister_framebuffer(info); | 1258 | unregister_framebuffer(info); |
1261 | gbe_turn_off(); | 1259 | gbe_turn_off(); |
1260 | arch_phys_wc_del(par->wc_cookie); | ||
1262 | if (gbe_dma_addr) | 1261 | if (gbe_dma_addr) |
1263 | dma_free_coherent(NULL, gbe_mem_size, gbe_mem, gbe_mem_phys); | 1262 | dma_free_writecombine(NULL, gbe_mem_size, gbe_mem, gbe_mem_phys); |
1264 | dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t), | 1263 | dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t), |
1265 | (void *)gbe_tiles.cpu, gbe_tiles.dma); | 1264 | (void *)gbe_tiles.cpu, gbe_tiles.dma); |
1266 | release_mem_region(GBE_BASE, sizeof(struct sgi_gbe)); | 1265 | release_mem_region(GBE_BASE, sizeof(struct sgi_gbe)); |
diff --git a/drivers/video/fbdev/geode/gxfb_core.c b/drivers/video/fbdev/geode/gxfb_core.c index 124d7c7e2d14..ec9fc9ac23de 100644 --- a/drivers/video/fbdev/geode/gxfb_core.c +++ b/drivers/video/fbdev/geode/gxfb_core.c | |||
@@ -263,7 +263,8 @@ static int gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev) | |||
263 | 263 | ||
264 | info->fix.smem_start = pci_resource_start(dev, 0); | 264 | info->fix.smem_start = pci_resource_start(dev, 0); |
265 | info->fix.smem_len = vram ? vram : gx_frame_buffer_size(); | 265 | info->fix.smem_len = vram ? vram : gx_frame_buffer_size(); |
266 | info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); | 266 | info->screen_base = ioremap_wc(info->fix.smem_start, |
267 | info->fix.smem_len); | ||
267 | if (!info->screen_base) | 268 | if (!info->screen_base) |
268 | return -ENOMEM; | 269 | return -ENOMEM; |
269 | 270 | ||
diff --git a/drivers/video/fbdev/i810/i810.h b/drivers/video/fbdev/i810/i810.h index 1414b73ac55b..7b1c002bfb08 100644 --- a/drivers/video/fbdev/i810/i810.h +++ b/drivers/video/fbdev/i810/i810.h | |||
@@ -199,7 +199,6 @@ | |||
199 | #define HAS_FONTCACHE 8 | 199 | #define HAS_FONTCACHE 8 |
200 | 200 | ||
201 | /* driver flags */ | 201 | /* driver flags */ |
202 | #define HAS_MTRR 1 | ||
203 | #define HAS_ACCELERATION 2 | 202 | #define HAS_ACCELERATION 2 |
204 | #define ALWAYS_SYNC 4 | 203 | #define ALWAYS_SYNC 4 |
205 | #define LOCKUP 8 | 204 | #define LOCKUP 8 |
@@ -281,7 +280,7 @@ struct i810fb_par { | |||
281 | u32 ovract; | 280 | u32 ovract; |
282 | u32 cur_state; | 281 | u32 cur_state; |
283 | u32 ddc_num; | 282 | u32 ddc_num; |
284 | int mtrr_reg; | 283 | int wc_cookie; |
285 | u16 bltcntl; | 284 | u16 bltcntl; |
286 | u8 interlace; | 285 | u8 interlace; |
287 | }; | 286 | }; |
diff --git a/drivers/video/fbdev/i810/i810_main.c b/drivers/video/fbdev/i810/i810_main.c index bb674e431741..025b882a4826 100644 --- a/drivers/video/fbdev/i810/i810_main.c +++ b/drivers/video/fbdev/i810/i810_main.c | |||
@@ -41,6 +41,7 @@ | |||
41 | #include <linux/resource.h> | 41 | #include <linux/resource.h> |
42 | #include <linux/unistd.h> | 42 | #include <linux/unistd.h> |
43 | #include <linux/console.h> | 43 | #include <linux/console.h> |
44 | #include <linux/io.h> | ||
44 | 45 | ||
45 | #include <asm/io.h> | 46 | #include <asm/io.h> |
46 | #include <asm/div64.h> | 47 | #include <asm/div64.h> |
@@ -1816,7 +1817,9 @@ static void i810_init_device(struct i810fb_par *par) | |||
1816 | u8 reg; | 1817 | u8 reg; |
1817 | u8 __iomem *mmio = par->mmio_start_virtual; | 1818 | u8 __iomem *mmio = par->mmio_start_virtual; |
1818 | 1819 | ||
1819 | if (mtrr) set_mtrr(par); | 1820 | if (mtrr) |
1821 | par->wc_cookie= arch_phys_wc_add((u32) par->aperture.physical, | ||
1822 | par->aperture.size); | ||
1820 | 1823 | ||
1821 | i810_init_cursor(par); | 1824 | i810_init_cursor(par); |
1822 | 1825 | ||
@@ -1865,8 +1868,8 @@ static int i810_allocate_pci_resource(struct i810fb_par *par, | |||
1865 | } | 1868 | } |
1866 | par->res_flags |= FRAMEBUFFER_REQ; | 1869 | par->res_flags |= FRAMEBUFFER_REQ; |
1867 | 1870 | ||
1868 | par->aperture.virtual = ioremap_nocache(par->aperture.physical, | 1871 | par->aperture.virtual = ioremap_wc(par->aperture.physical, |
1869 | par->aperture.size); | 1872 | par->aperture.size); |
1870 | if (!par->aperture.virtual) { | 1873 | if (!par->aperture.virtual) { |
1871 | printk("i810fb_init: cannot remap framebuffer region\n"); | 1874 | printk("i810fb_init: cannot remap framebuffer region\n"); |
1872 | return -ENODEV; | 1875 | return -ENODEV; |
@@ -2096,7 +2099,7 @@ static void i810fb_release_resource(struct fb_info *info, | |||
2096 | struct i810fb_par *par) | 2099 | struct i810fb_par *par) |
2097 | { | 2100 | { |
2098 | struct gtt_data *gtt = &par->i810_gtt; | 2101 | struct gtt_data *gtt = &par->i810_gtt; |
2099 | unset_mtrr(par); | 2102 | arch_phys_wc_del(par->wc_cookie); |
2100 | 2103 | ||
2101 | i810_delete_i2c_busses(par); | 2104 | i810_delete_i2c_busses(par); |
2102 | 2105 | ||
diff --git a/drivers/video/fbdev/i810/i810_main.h b/drivers/video/fbdev/i810/i810_main.h index a25afaa534ba..7bfaaad1d0fa 100644 --- a/drivers/video/fbdev/i810/i810_main.h +++ b/drivers/video/fbdev/i810/i810_main.h | |||
@@ -60,32 +60,6 @@ static inline void flush_cache(void) | |||
60 | #define flush_cache() do { } while(0) | 60 | #define flush_cache() do { } while(0) |
61 | #endif | 61 | #endif |
62 | 62 | ||
63 | #ifdef CONFIG_MTRR | ||
64 | |||
65 | #include <asm/mtrr.h> | ||
66 | |||
67 | static inline void set_mtrr(struct i810fb_par *par) | ||
68 | { | ||
69 | par->mtrr_reg = mtrr_add((u32) par->aperture.physical, | ||
70 | par->aperture.size, MTRR_TYPE_WRCOMB, 1); | ||
71 | if (par->mtrr_reg < 0) { | ||
72 | printk(KERN_ERR "set_mtrr: unable to set MTRR\n"); | ||
73 | return; | ||
74 | } | ||
75 | par->dev_flags |= HAS_MTRR; | ||
76 | } | ||
77 | static inline void unset_mtrr(struct i810fb_par *par) | ||
78 | { | ||
79 | if (par->dev_flags & HAS_MTRR) | ||
80 | mtrr_del(par->mtrr_reg, (u32) par->aperture.physical, | ||
81 | par->aperture.size); | ||
82 | } | ||
83 | #else | ||
84 | #define set_mtrr(x) printk("set_mtrr: MTRR is disabled in the kernel\n") | ||
85 | |||
86 | #define unset_mtrr(x) do { } while (0) | ||
87 | #endif /* CONFIG_MTRR */ | ||
88 | |||
89 | #ifdef CONFIG_FB_I810_GTF | 63 | #ifdef CONFIG_FB_I810_GTF |
90 | #define IS_DVT (0) | 64 | #define IS_DVT (0) |
91 | #else | 65 | #else |
diff --git a/drivers/video/fbdev/imxfb.c b/drivers/video/fbdev/imxfb.c index 84d1d29e532c..cee88603efc9 100644 --- a/drivers/video/fbdev/imxfb.c +++ b/drivers/video/fbdev/imxfb.c | |||
@@ -170,7 +170,7 @@ struct imxfb_info { | |||
170 | struct regulator *lcd_pwr; | 170 | struct regulator *lcd_pwr; |
171 | }; | 171 | }; |
172 | 172 | ||
173 | static struct platform_device_id imxfb_devtype[] = { | 173 | static const struct platform_device_id imxfb_devtype[] = { |
174 | { | 174 | { |
175 | .name = "imx1-fb", | 175 | .name = "imx1-fb", |
176 | .driver_data = IMX1_FB, | 176 | .driver_data = IMX1_FB, |
diff --git a/drivers/video/fbdev/intelfb/intelfb.h b/drivers/video/fbdev/intelfb/intelfb.h index 6b51175629c7..37f8339ea88c 100644 --- a/drivers/video/fbdev/intelfb/intelfb.h +++ b/drivers/video/fbdev/intelfb/intelfb.h | |||
@@ -285,9 +285,7 @@ struct intelfb_info { | |||
285 | /* use a gart reserved fb mem */ | 285 | /* use a gart reserved fb mem */ |
286 | u8 fbmem_gart; | 286 | u8 fbmem_gart; |
287 | 287 | ||
288 | /* mtrr support */ | 288 | int wc_cookie; |
289 | int mtrr_reg; | ||
290 | u32 has_mtrr; | ||
291 | 289 | ||
292 | /* heap data */ | 290 | /* heap data */ |
293 | struct intelfb_heap_data aperture; | 291 | struct intelfb_heap_data aperture; |
diff --git a/drivers/video/fbdev/intelfb/intelfbdrv.c b/drivers/video/fbdev/intelfb/intelfbdrv.c index b847d530471a..bbec737eef30 100644 --- a/drivers/video/fbdev/intelfb/intelfbdrv.c +++ b/drivers/video/fbdev/intelfb/intelfbdrv.c | |||
@@ -124,10 +124,6 @@ | |||
124 | 124 | ||
125 | #include <asm/io.h> | 125 | #include <asm/io.h> |
126 | 126 | ||
127 | #ifdef CONFIG_MTRR | ||
128 | #include <asm/mtrr.h> | ||
129 | #endif | ||
130 | |||
131 | #include "intelfb.h" | 127 | #include "intelfb.h" |
132 | #include "intelfbhw.h" | 128 | #include "intelfbhw.h" |
133 | #include "../edid.h" | 129 | #include "../edid.h" |
@@ -411,33 +407,6 @@ module_init(intelfb_init); | |||
411 | module_exit(intelfb_exit); | 407 | module_exit(intelfb_exit); |
412 | 408 | ||
413 | /*************************************************************** | 409 | /*************************************************************** |
414 | * mtrr support functions * | ||
415 | ***************************************************************/ | ||
416 | |||
417 | #ifdef CONFIG_MTRR | ||
418 | static inline void set_mtrr(struct intelfb_info *dinfo) | ||
419 | { | ||
420 | dinfo->mtrr_reg = mtrr_add(dinfo->aperture.physical, | ||
421 | dinfo->aperture.size, MTRR_TYPE_WRCOMB, 1); | ||
422 | if (dinfo->mtrr_reg < 0) { | ||
423 | ERR_MSG("unable to set MTRR\n"); | ||
424 | return; | ||
425 | } | ||
426 | dinfo->has_mtrr = 1; | ||
427 | } | ||
428 | static inline void unset_mtrr(struct intelfb_info *dinfo) | ||
429 | { | ||
430 | if (dinfo->has_mtrr) | ||
431 | mtrr_del(dinfo->mtrr_reg, dinfo->aperture.physical, | ||
432 | dinfo->aperture.size); | ||
433 | } | ||
434 | #else | ||
435 | #define set_mtrr(x) WRN_MSG("MTRR is disabled in the kernel\n") | ||
436 | |||
437 | #define unset_mtrr(x) do { } while (0) | ||
438 | #endif /* CONFIG_MTRR */ | ||
439 | |||
440 | /*************************************************************** | ||
441 | * driver init / cleanup * | 410 | * driver init / cleanup * |
442 | ***************************************************************/ | 411 | ***************************************************************/ |
443 | 412 | ||
@@ -456,7 +425,7 @@ static void cleanup(struct intelfb_info *dinfo) | |||
456 | if (dinfo->registered) | 425 | if (dinfo->registered) |
457 | unregister_framebuffer(dinfo->info); | 426 | unregister_framebuffer(dinfo->info); |
458 | 427 | ||
459 | unset_mtrr(dinfo); | 428 | arch_phys_wc_del(dinfo->wc_cookie); |
460 | 429 | ||
461 | if (dinfo->fbmem_gart && dinfo->gtt_fb_mem) { | 430 | if (dinfo->fbmem_gart && dinfo->gtt_fb_mem) { |
462 | agp_unbind_memory(dinfo->gtt_fb_mem); | 431 | agp_unbind_memory(dinfo->gtt_fb_mem); |
@@ -675,7 +644,7 @@ static int intelfb_pci_register(struct pci_dev *pdev, | |||
675 | /* Allocate memories (which aren't stolen) */ | 644 | /* Allocate memories (which aren't stolen) */ |
676 | /* Map the fb and MMIO regions */ | 645 | /* Map the fb and MMIO regions */ |
677 | /* ioremap only up to the end of used aperture */ | 646 | /* ioremap only up to the end of used aperture */ |
678 | dinfo->aperture.virtual = (u8 __iomem *)ioremap_nocache | 647 | dinfo->aperture.virtual = (u8 __iomem *)ioremap_wc |
679 | (dinfo->aperture.physical, ((offset + dinfo->fb.offset) << 12) | 648 | (dinfo->aperture.physical, ((offset + dinfo->fb.offset) << 12) |
680 | + dinfo->fb.size); | 649 | + dinfo->fb.size); |
681 | if (!dinfo->aperture.virtual) { | 650 | if (!dinfo->aperture.virtual) { |
@@ -772,7 +741,8 @@ static int intelfb_pci_register(struct pci_dev *pdev, | |||
772 | agp_backend_release(bridge); | 741 | agp_backend_release(bridge); |
773 | 742 | ||
774 | if (mtrr) | 743 | if (mtrr) |
775 | set_mtrr(dinfo); | 744 | dinfo->wc_cookie = arch_phys_wc_add(dinfo->aperture.physical, |
745 | dinfo->aperture.size); | ||
776 | 746 | ||
777 | DBG_MSG("fb: 0x%x(+ 0x%x)/0x%x (0x%p)\n", | 747 | DBG_MSG("fb: 0x%x(+ 0x%x)/0x%x (0x%p)\n", |
778 | dinfo->fb.physical, dinfo->fb.offset, dinfo->fb.size, | 748 | dinfo->fb.physical, dinfo->fb.offset, dinfo->fb.size, |
diff --git a/drivers/video/fbdev/matrox/matroxfb_base.c b/drivers/video/fbdev/matrox/matroxfb_base.c index 62539ca1cfa9..11eb094396ae 100644 --- a/drivers/video/fbdev/matrox/matroxfb_base.c +++ b/drivers/video/fbdev/matrox/matroxfb_base.c | |||
@@ -370,12 +370,9 @@ static void matroxfb_remove(struct matrox_fb_info *minfo, int dummy) | |||
370 | matroxfb_unregister_device(minfo); | 370 | matroxfb_unregister_device(minfo); |
371 | unregister_framebuffer(&minfo->fbcon); | 371 | unregister_framebuffer(&minfo->fbcon); |
372 | matroxfb_g450_shutdown(minfo); | 372 | matroxfb_g450_shutdown(minfo); |
373 | #ifdef CONFIG_MTRR | 373 | arch_phys_wc_del(minfo->wc_cookie); |
374 | if (minfo->mtrr.vram_valid) | 374 | iounmap(minfo->mmio.vbase.vaddr); |
375 | mtrr_del(minfo->mtrr.vram, minfo->video.base, minfo->video.len); | 375 | iounmap(minfo->video.vbase.vaddr); |
376 | #endif | ||
377 | mga_iounmap(minfo->mmio.vbase); | ||
378 | mga_iounmap(minfo->video.vbase); | ||
379 | release_mem_region(minfo->video.base, minfo->video.len_maximum); | 376 | release_mem_region(minfo->video.base, minfo->video.len_maximum); |
380 | release_mem_region(minfo->mmio.base, 16384); | 377 | release_mem_region(minfo->mmio.base, 16384); |
381 | kfree(minfo); | 378 | kfree(minfo); |
@@ -591,12 +588,8 @@ static int matroxfb_decode_var(const struct matrox_fb_info *minfo, | |||
591 | unsigned int max_yres; | 588 | unsigned int max_yres; |
592 | 589 | ||
593 | while (m1) { | 590 | while (m1) { |
594 | int t; | ||
595 | |||
596 | while (m2 >= m1) m2 -= m1; | 591 | while (m2 >= m1) m2 -= m1; |
597 | t = m1; | 592 | swap(m1, m2); |
598 | m1 = m2; | ||
599 | m2 = t; | ||
600 | } | 593 | } |
601 | m2 = linelen * PAGE_SIZE / m2; | 594 | m2 = linelen * PAGE_SIZE / m2; |
602 | *ydstorg = m2 = 0x400000 % m2; | 595 | *ydstorg = m2 = 0x400000 % m2; |
@@ -1256,9 +1249,7 @@ static int nobios; /* "matroxfb:nobios" */ | |||
1256 | static int noinit = 1; /* "matroxfb:init" */ | 1249 | static int noinit = 1; /* "matroxfb:init" */ |
1257 | static int inverse; /* "matroxfb:inverse" */ | 1250 | static int inverse; /* "matroxfb:inverse" */ |
1258 | static int sgram; /* "matroxfb:sgram" */ | 1251 | static int sgram; /* "matroxfb:sgram" */ |
1259 | #ifdef CONFIG_MTRR | ||
1260 | static int mtrr = 1; /* "matroxfb:nomtrr" */ | 1252 | static int mtrr = 1; /* "matroxfb:nomtrr" */ |
1261 | #endif | ||
1262 | static int grayscale; /* "matroxfb:grayscale" */ | 1253 | static int grayscale; /* "matroxfb:grayscale" */ |
1263 | static int dev = -1; /* "matroxfb:dev:xxxxx" */ | 1254 | static int dev = -1; /* "matroxfb:dev:xxxxx" */ |
1264 | static unsigned int vesa = ~0; /* "matroxfb:vesa:xxxxx" */ | 1255 | static unsigned int vesa = ~0; /* "matroxfb:vesa:xxxxx" */ |
@@ -1717,14 +1708,17 @@ static int initMatrox2(struct matrox_fb_info *minfo, struct board *b) | |||
1717 | if (mem && (mem < memsize)) | 1708 | if (mem && (mem < memsize)) |
1718 | memsize = mem; | 1709 | memsize = mem; |
1719 | err = -ENOMEM; | 1710 | err = -ENOMEM; |
1720 | if (mga_ioremap(ctrlptr_phys, 16384, MGA_IOREMAP_MMIO, &minfo->mmio.vbase)) { | 1711 | |
1712 | minfo->mmio.vbase.vaddr = ioremap_nocache(ctrlptr_phys, 16384); | ||
1713 | if (!minfo->mmio.vbase.vaddr) { | ||
1721 | printk(KERN_ERR "matroxfb: cannot ioremap(%lX, 16384), matroxfb disabled\n", ctrlptr_phys); | 1714 | printk(KERN_ERR "matroxfb: cannot ioremap(%lX, 16384), matroxfb disabled\n", ctrlptr_phys); |
1722 | goto failVideoMR; | 1715 | goto failVideoMR; |
1723 | } | 1716 | } |
1724 | minfo->mmio.base = ctrlptr_phys; | 1717 | minfo->mmio.base = ctrlptr_phys; |
1725 | minfo->mmio.len = 16384; | 1718 | minfo->mmio.len = 16384; |
1726 | minfo->video.base = video_base_phys; | 1719 | minfo->video.base = video_base_phys; |
1727 | if (mga_ioremap(video_base_phys, memsize, MGA_IOREMAP_FB, &minfo->video.vbase)) { | 1720 | minfo->video.vbase.vaddr = ioremap_wc(video_base_phys, memsize); |
1721 | if (!minfo->video.vbase.vaddr) { | ||
1728 | printk(KERN_ERR "matroxfb: cannot ioremap(%lX, %d), matroxfb disabled\n", | 1722 | printk(KERN_ERR "matroxfb: cannot ioremap(%lX, %d), matroxfb disabled\n", |
1729 | video_base_phys, memsize); | 1723 | video_base_phys, memsize); |
1730 | goto failCtrlIO; | 1724 | goto failCtrlIO; |
@@ -1772,13 +1766,9 @@ static int initMatrox2(struct matrox_fb_info *minfo, struct board *b) | |||
1772 | minfo->video.len_usable = minfo->video.len; | 1766 | minfo->video.len_usable = minfo->video.len; |
1773 | if (minfo->video.len_usable > b->base->maxdisplayable) | 1767 | if (minfo->video.len_usable > b->base->maxdisplayable) |
1774 | minfo->video.len_usable = b->base->maxdisplayable; | 1768 | minfo->video.len_usable = b->base->maxdisplayable; |
1775 | #ifdef CONFIG_MTRR | 1769 | if (mtrr) |
1776 | if (mtrr) { | 1770 | minfo->wc_cookie = arch_phys_wc_add(video_base_phys, |
1777 | minfo->mtrr.vram = mtrr_add(video_base_phys, minfo->video.len, MTRR_TYPE_WRCOMB, 1); | 1771 | minfo->video.len); |
1778 | minfo->mtrr.vram_valid = 1; | ||
1779 | printk(KERN_INFO "matroxfb: MTRR's turned on\n"); | ||
1780 | } | ||
1781 | #endif /* CONFIG_MTRR */ | ||
1782 | 1772 | ||
1783 | if (!minfo->devflags.novga) | 1773 | if (!minfo->devflags.novga) |
1784 | request_region(0x3C0, 32, "matrox"); | 1774 | request_region(0x3C0, 32, "matrox"); |
@@ -1947,9 +1937,9 @@ static int initMatrox2(struct matrox_fb_info *minfo, struct board *b) | |||
1947 | return 0; | 1937 | return 0; |
1948 | failVideoIO:; | 1938 | failVideoIO:; |
1949 | matroxfb_g450_shutdown(minfo); | 1939 | matroxfb_g450_shutdown(minfo); |
1950 | mga_iounmap(minfo->video.vbase); | 1940 | iounmap(minfo->video.vbase.vaddr); |
1951 | failCtrlIO:; | 1941 | failCtrlIO:; |
1952 | mga_iounmap(minfo->mmio.vbase); | 1942 | iounmap(minfo->mmio.vbase.vaddr); |
1953 | failVideoMR:; | 1943 | failVideoMR:; |
1954 | release_mem_region(video_base_phys, minfo->video.len_maximum); | 1944 | release_mem_region(video_base_phys, minfo->video.len_maximum); |
1955 | failCtrlMR:; | 1945 | failCtrlMR:; |
@@ -2443,10 +2433,8 @@ static int __init matroxfb_setup(char *options) { | |||
2443 | nobios = !value; | 2433 | nobios = !value; |
2444 | else if (!strcmp(this_opt, "init")) | 2434 | else if (!strcmp(this_opt, "init")) |
2445 | noinit = !value; | 2435 | noinit = !value; |
2446 | #ifdef CONFIG_MTRR | ||
2447 | else if (!strcmp(this_opt, "mtrr")) | 2436 | else if (!strcmp(this_opt, "mtrr")) |
2448 | mtrr = value; | 2437 | mtrr = value; |
2449 | #endif | ||
2450 | else if (!strcmp(this_opt, "inv24")) | 2438 | else if (!strcmp(this_opt, "inv24")) |
2451 | inv24 = value; | 2439 | inv24 = value; |
2452 | else if (!strcmp(this_opt, "cross4MB")) | 2440 | else if (!strcmp(this_opt, "cross4MB")) |
@@ -2515,10 +2503,8 @@ module_param(noinit, int, 0); | |||
2515 | MODULE_PARM_DESC(noinit, "Disables W/SG/SD-RAM and bus interface initialization (0 or 1=do not initialize) (default=0)"); | 2503 | MODULE_PARM_DESC(noinit, "Disables W/SG/SD-RAM and bus interface initialization (0 or 1=do not initialize) (default=0)"); |
2516 | module_param(memtype, int, 0); | 2504 | module_param(memtype, int, 0); |
2517 | MODULE_PARM_DESC(memtype, "Memory type for G200/G400 (see Documentation/fb/matroxfb.txt for explanation) (default=3 for G200, 0 for G400)"); | 2505 | MODULE_PARM_DESC(memtype, "Memory type for G200/G400 (see Documentation/fb/matroxfb.txt for explanation) (default=3 for G200, 0 for G400)"); |
2518 | #ifdef CONFIG_MTRR | ||
2519 | module_param(mtrr, int, 0); | 2506 | module_param(mtrr, int, 0); |
2520 | MODULE_PARM_DESC(mtrr, "This speeds up video memory accesses (0=disabled or 1) (default=1)"); | 2507 | MODULE_PARM_DESC(mtrr, "This speeds up video memory accesses (0=disabled or 1) (default=1)"); |
2521 | #endif | ||
2522 | module_param(sgram, int, 0); | 2508 | module_param(sgram, int, 0); |
2523 | MODULE_PARM_DESC(sgram, "Indicates that G100/G200/G400 has SGRAM memory (0=SDRAM, 1=SGRAM) (default=0)"); | 2509 | MODULE_PARM_DESC(sgram, "Indicates that G100/G200/G400 has SGRAM memory (0=SDRAM, 1=SGRAM) (default=0)"); |
2524 | module_param(inv24, int, 0); | 2510 | module_param(inv24, int, 0); |
diff --git a/drivers/video/fbdev/matrox/matroxfb_base.h b/drivers/video/fbdev/matrox/matroxfb_base.h index 89a8a89a5eb2..09b02cd1eb0e 100644 --- a/drivers/video/fbdev/matrox/matroxfb_base.h +++ b/drivers/video/fbdev/matrox/matroxfb_base.h | |||
@@ -44,9 +44,6 @@ | |||
44 | 44 | ||
45 | #include <asm/io.h> | 45 | #include <asm/io.h> |
46 | #include <asm/unaligned.h> | 46 | #include <asm/unaligned.h> |
47 | #ifdef CONFIG_MTRR | ||
48 | #include <asm/mtrr.h> | ||
49 | #endif | ||
50 | 47 | ||
51 | #if defined(CONFIG_PPC_PMAC) | 48 | #if defined(CONFIG_PPC_PMAC) |
52 | #include <asm/prom.h> | 49 | #include <asm/prom.h> |
@@ -187,23 +184,6 @@ static inline void __iomem* vaddr_va(vaddr_t va) { | |||
187 | return va.vaddr; | 184 | return va.vaddr; |
188 | } | 185 | } |
189 | 186 | ||
190 | #define MGA_IOREMAP_NORMAL 0 | ||
191 | #define MGA_IOREMAP_NOCACHE 1 | ||
192 | |||
193 | #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE | ||
194 | #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE | ||
195 | static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) { | ||
196 | if (flags & MGA_IOREMAP_NOCACHE) | ||
197 | virt->vaddr = ioremap_nocache(phys, size); | ||
198 | else | ||
199 | virt->vaddr = ioremap(phys, size); | ||
200 | return (virt->vaddr == NULL); /* 0, !0... 0, error_code in future */ | ||
201 | } | ||
202 | |||
203 | static inline void mga_iounmap(vaddr_t va) { | ||
204 | iounmap(va.vaddr); | ||
205 | } | ||
206 | |||
207 | struct my_timming { | 187 | struct my_timming { |
208 | unsigned int pixclock; | 188 | unsigned int pixclock; |
209 | int mnp; | 189 | int mnp; |
@@ -449,12 +429,7 @@ struct matrox_fb_info { | |||
449 | int plnwt; | 429 | int plnwt; |
450 | int srcorg; | 430 | int srcorg; |
451 | } capable; | 431 | } capable; |
452 | #ifdef CONFIG_MTRR | 432 | int wc_cookie; |
453 | struct { | ||
454 | int vram; | ||
455 | int vram_valid; | ||
456 | } mtrr; | ||
457 | #endif | ||
458 | struct { | 433 | struct { |
459 | int precise_width; | 434 | int precise_width; |
460 | int mga_24bpp_fix; | 435 | int mga_24bpp_fix; |
diff --git a/drivers/video/fbdev/msm/Makefile b/drivers/video/fbdev/msm/Makefile deleted file mode 100644 index 802d6ae523fb..000000000000 --- a/drivers/video/fbdev/msm/Makefile +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | |||
2 | # core framebuffer | ||
3 | # | ||
4 | obj-y := msm_fb.o | ||
5 | |||
6 | # MDP DMA/PPP engine | ||
7 | # | ||
8 | obj-y += mdp.o mdp_scale_tables.o mdp_ppp.o | ||
9 | |||
10 | # MDDI interface | ||
11 | # | ||
12 | obj-y += mddi.o | ||
13 | |||
14 | # MDDI client/panel drivers | ||
15 | # | ||
16 | obj-y += mddi_client_dummy.o | ||
17 | obj-y += mddi_client_toshiba.o | ||
18 | obj-y += mddi_client_nt35399.o | ||
19 | |||
diff --git a/drivers/video/fbdev/msm/mddi.c b/drivers/video/fbdev/msm/mddi.c deleted file mode 100644 index e0f8011a3c4b..000000000000 --- a/drivers/video/fbdev/msm/mddi.c +++ /dev/null | |||
@@ -1,821 +0,0 @@ | |||
1 | /* | ||
2 | * MSM MDDI Transport | ||
3 | * | ||
4 | * Copyright (C) 2007 Google Incorporated | ||
5 | * Copyright (C) 2007 QUALCOMM Incorporated | ||
6 | * | ||
7 | * This software is licensed under the terms of the GNU General Public | ||
8 | * License version 2, as published by the Free Software Foundation, and | ||
9 | * may be copied, distributed, and modified under those terms. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | #include <linux/module.h> | ||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/dma-mapping.h> | ||
21 | #include <linux/interrupt.h> | ||
22 | #include <linux/platform_device.h> | ||
23 | #include <linux/delay.h> | ||
24 | #include <linux/gfp.h> | ||
25 | #include <linux/spinlock.h> | ||
26 | #include <linux/clk.h> | ||
27 | #include <linux/io.h> | ||
28 | #include <linux/sched.h> | ||
29 | #include <linux/platform_data/video-msm_fb.h> | ||
30 | #include "mddi_hw.h" | ||
31 | |||
32 | #define FLAG_DISABLE_HIBERNATION 0x0001 | ||
33 | #define FLAG_HAVE_CAPS 0x0002 | ||
34 | #define FLAG_HAS_VSYNC_IRQ 0x0004 | ||
35 | #define FLAG_HAVE_STATUS 0x0008 | ||
36 | |||
37 | #define CMD_GET_CLIENT_CAP 0x0601 | ||
38 | #define CMD_GET_CLIENT_STATUS 0x0602 | ||
39 | |||
40 | union mddi_rev { | ||
41 | unsigned char raw[MDDI_REV_BUFFER_SIZE]; | ||
42 | struct mddi_rev_packet hdr; | ||
43 | struct mddi_client_status status; | ||
44 | struct mddi_client_caps caps; | ||
45 | struct mddi_register_access reg; | ||
46 | }; | ||
47 | |||
48 | struct reg_read_info { | ||
49 | struct completion done; | ||
50 | uint32_t reg; | ||
51 | uint32_t status; | ||
52 | uint32_t result; | ||
53 | }; | ||
54 | |||
55 | struct mddi_info { | ||
56 | uint16_t flags; | ||
57 | uint16_t version; | ||
58 | char __iomem *base; | ||
59 | int irq; | ||
60 | struct clk *clk; | ||
61 | struct msm_mddi_client_data client_data; | ||
62 | |||
63 | /* buffer for rev encap packets */ | ||
64 | void *rev_data; | ||
65 | dma_addr_t rev_addr; | ||
66 | struct mddi_llentry *reg_write_data; | ||
67 | dma_addr_t reg_write_addr; | ||
68 | struct mddi_llentry *reg_read_data; | ||
69 | dma_addr_t reg_read_addr; | ||
70 | size_t rev_data_curr; | ||
71 | |||
72 | spinlock_t int_lock; | ||
73 | uint32_t int_enable; | ||
74 | uint32_t got_int; | ||
75 | wait_queue_head_t int_wait; | ||
76 | |||
77 | struct mutex reg_write_lock; | ||
78 | struct mutex reg_read_lock; | ||
79 | struct reg_read_info *reg_read; | ||
80 | |||
81 | struct mddi_client_caps caps; | ||
82 | struct mddi_client_status status; | ||
83 | |||
84 | void (*power_client)(struct msm_mddi_client_data *, int); | ||
85 | |||
86 | /* client device published to bind us to the | ||
87 | * appropriate mddi_client driver | ||
88 | */ | ||
89 | char client_name[20]; | ||
90 | |||
91 | struct platform_device client_pdev; | ||
92 | }; | ||
93 | |||
94 | static void mddi_init_rev_encap(struct mddi_info *mddi); | ||
95 | |||
96 | #define mddi_readl(r) readl(mddi->base + (MDDI_##r)) | ||
97 | #define mddi_writel(v, r) writel((v), mddi->base + (MDDI_##r)) | ||
98 | |||
99 | void mddi_activate_link(struct msm_mddi_client_data *cdata) | ||
100 | { | ||
101 | struct mddi_info *mddi = container_of(cdata, struct mddi_info, | ||
102 | client_data); | ||
103 | |||
104 | mddi_writel(MDDI_CMD_LINK_ACTIVE, CMD); | ||
105 | } | ||
106 | |||
107 | static void mddi_handle_link_list_done(struct mddi_info *mddi) | ||
108 | { | ||
109 | } | ||
110 | |||
111 | static void mddi_reset_rev_encap_ptr(struct mddi_info *mddi) | ||
112 | { | ||
113 | printk(KERN_INFO "mddi: resetting rev ptr\n"); | ||
114 | mddi->rev_data_curr = 0; | ||
115 | mddi_writel(mddi->rev_addr, REV_PTR); | ||
116 | mddi_writel(mddi->rev_addr, REV_PTR); | ||
117 | mddi_writel(MDDI_CMD_FORCE_NEW_REV_PTR, CMD); | ||
118 | } | ||
119 | |||
120 | static void mddi_handle_rev_data(struct mddi_info *mddi, union mddi_rev *rev) | ||
121 | { | ||
122 | int i; | ||
123 | struct reg_read_info *ri; | ||
124 | |||
125 | if ((rev->hdr.length <= MDDI_REV_BUFFER_SIZE - 2) && | ||
126 | (rev->hdr.length >= sizeof(struct mddi_rev_packet) - 2)) { | ||
127 | |||
128 | switch (rev->hdr.type) { | ||
129 | case TYPE_CLIENT_CAPS: | ||
130 | memcpy(&mddi->caps, &rev->caps, | ||
131 | sizeof(struct mddi_client_caps)); | ||
132 | mddi->flags |= FLAG_HAVE_CAPS; | ||
133 | wake_up(&mddi->int_wait); | ||
134 | break; | ||
135 | case TYPE_CLIENT_STATUS: | ||
136 | memcpy(&mddi->status, &rev->status, | ||
137 | sizeof(struct mddi_client_status)); | ||
138 | mddi->flags |= FLAG_HAVE_STATUS; | ||
139 | wake_up(&mddi->int_wait); | ||
140 | break; | ||
141 | case TYPE_REGISTER_ACCESS: | ||
142 | ri = mddi->reg_read; | ||
143 | if (ri == 0) { | ||
144 | printk(KERN_INFO "rev: got reg %x = %x without " | ||
145 | " pending read\n", | ||
146 | rev->reg.register_address, | ||
147 | rev->reg.register_data_list); | ||
148 | break; | ||
149 | } | ||
150 | if (ri->reg != rev->reg.register_address) { | ||
151 | printk(KERN_INFO "rev: got reg %x = %x for " | ||
152 | "wrong register, expected " | ||
153 | "%x\n", | ||
154 | rev->reg.register_address, | ||
155 | rev->reg.register_data_list, ri->reg); | ||
156 | break; | ||
157 | } | ||
158 | mddi->reg_read = NULL; | ||
159 | ri->status = 0; | ||
160 | ri->result = rev->reg.register_data_list; | ||
161 | complete(&ri->done); | ||
162 | break; | ||
163 | default: | ||
164 | printk(KERN_INFO "rev: unknown reverse packet: " | ||
165 | "len=%04x type=%04x CURR_REV_PTR=%x\n", | ||
166 | rev->hdr.length, rev->hdr.type, | ||
167 | mddi_readl(CURR_REV_PTR)); | ||
168 | for (i = 0; i < rev->hdr.length + 2; i++) { | ||
169 | if ((i % 16) == 0) | ||
170 | printk(KERN_INFO "\n"); | ||
171 | printk(KERN_INFO " %02x", rev->raw[i]); | ||
172 | } | ||
173 | printk(KERN_INFO "\n"); | ||
174 | mddi_reset_rev_encap_ptr(mddi); | ||
175 | } | ||
176 | } else { | ||
177 | printk(KERN_INFO "bad rev length, %d, CURR_REV_PTR %x\n", | ||
178 | rev->hdr.length, mddi_readl(CURR_REV_PTR)); | ||
179 | mddi_reset_rev_encap_ptr(mddi); | ||
180 | } | ||
181 | } | ||
182 | |||
183 | static void mddi_wait_interrupt(struct mddi_info *mddi, uint32_t intmask); | ||
184 | |||
185 | static void mddi_handle_rev_data_avail(struct mddi_info *mddi) | ||
186 | { | ||
187 | uint32_t rev_data_count; | ||
188 | uint32_t rev_crc_err_count; | ||
189 | struct reg_read_info *ri; | ||
190 | size_t prev_offset; | ||
191 | uint16_t length; | ||
192 | |||
193 | union mddi_rev *crev = mddi->rev_data + mddi->rev_data_curr; | ||
194 | |||
195 | /* clear the interrupt */ | ||
196 | mddi_writel(MDDI_INT_REV_DATA_AVAIL, INT); | ||
197 | rev_data_count = mddi_readl(REV_PKT_CNT); | ||
198 | rev_crc_err_count = mddi_readl(REV_CRC_ERR); | ||
199 | if (rev_data_count > 1) | ||
200 | printk(KERN_INFO "rev_data_count %d\n", rev_data_count); | ||
201 | |||
202 | if (rev_crc_err_count) { | ||
203 | printk(KERN_INFO "rev_crc_err_count %d, INT %x\n", | ||
204 | rev_crc_err_count, mddi_readl(INT)); | ||
205 | ri = mddi->reg_read; | ||
206 | if (ri == 0) { | ||
207 | printk(KERN_INFO "rev: got crc error without pending " | ||
208 | "read\n"); | ||
209 | } else { | ||
210 | mddi->reg_read = NULL; | ||
211 | ri->status = -EIO; | ||
212 | ri->result = -1; | ||
213 | complete(&ri->done); | ||
214 | } | ||
215 | } | ||
216 | |||
217 | if (rev_data_count == 0) | ||
218 | return; | ||
219 | |||
220 | prev_offset = mddi->rev_data_curr; | ||
221 | |||
222 | length = *((uint8_t *)mddi->rev_data + mddi->rev_data_curr); | ||
223 | mddi->rev_data_curr++; | ||
224 | if (mddi->rev_data_curr == MDDI_REV_BUFFER_SIZE) | ||
225 | mddi->rev_data_curr = 0; | ||
226 | length += *((uint8_t *)mddi->rev_data + mddi->rev_data_curr) << 8; | ||
227 | mddi->rev_data_curr += 1 + length; | ||
228 | if (mddi->rev_data_curr >= MDDI_REV_BUFFER_SIZE) | ||
229 | mddi->rev_data_curr = | ||
230 | mddi->rev_data_curr % MDDI_REV_BUFFER_SIZE; | ||
231 | |||
232 | if (length > MDDI_REV_BUFFER_SIZE - 2) { | ||
233 | printk(KERN_INFO "mddi: rev data length greater than buffer" | ||
234 | "size\n"); | ||
235 | mddi_reset_rev_encap_ptr(mddi); | ||
236 | return; | ||
237 | } | ||
238 | |||
239 | if (prev_offset + 2 + length >= MDDI_REV_BUFFER_SIZE) { | ||
240 | union mddi_rev tmprev; | ||
241 | size_t rem = MDDI_REV_BUFFER_SIZE - prev_offset; | ||
242 | memcpy(&tmprev.raw[0], mddi->rev_data + prev_offset, rem); | ||
243 | memcpy(&tmprev.raw[rem], mddi->rev_data, 2 + length - rem); | ||
244 | mddi_handle_rev_data(mddi, &tmprev); | ||
245 | } else { | ||
246 | mddi_handle_rev_data(mddi, crev); | ||
247 | } | ||
248 | |||
249 | if (prev_offset < MDDI_REV_BUFFER_SIZE / 2 && | ||
250 | mddi->rev_data_curr >= MDDI_REV_BUFFER_SIZE / 2) { | ||
251 | mddi_writel(mddi->rev_addr, REV_PTR); | ||
252 | } | ||
253 | } | ||
254 | |||
255 | static irqreturn_t mddi_isr(int irq, void *data) | ||
256 | { | ||
257 | struct msm_mddi_client_data *cdata = data; | ||
258 | struct mddi_info *mddi = container_of(cdata, struct mddi_info, | ||
259 | client_data); | ||
260 | uint32_t active, status; | ||
261 | |||
262 | spin_lock(&mddi->int_lock); | ||
263 | |||
264 | active = mddi_readl(INT); | ||
265 | status = mddi_readl(STAT); | ||
266 | |||
267 | mddi_writel(active, INT); | ||
268 | |||
269 | /* ignore any interrupts we have disabled */ | ||
270 | active &= mddi->int_enable; | ||
271 | |||
272 | mddi->got_int |= active; | ||
273 | wake_up(&mddi->int_wait); | ||
274 | |||
275 | if (active & MDDI_INT_PRI_LINK_LIST_DONE) { | ||
276 | mddi->int_enable &= (~MDDI_INT_PRI_LINK_LIST_DONE); | ||
277 | mddi_handle_link_list_done(mddi); | ||
278 | } | ||
279 | if (active & MDDI_INT_REV_DATA_AVAIL) | ||
280 | mddi_handle_rev_data_avail(mddi); | ||
281 | |||
282 | if (active & ~MDDI_INT_NEED_CLEAR) | ||
283 | mddi->int_enable &= ~(active & ~MDDI_INT_NEED_CLEAR); | ||
284 | |||
285 | if (active & MDDI_INT_LINK_ACTIVE) { | ||
286 | mddi->int_enable &= (~MDDI_INT_LINK_ACTIVE); | ||
287 | mddi->int_enable |= MDDI_INT_IN_HIBERNATION; | ||
288 | } | ||
289 | |||
290 | if (active & MDDI_INT_IN_HIBERNATION) { | ||
291 | mddi->int_enable &= (~MDDI_INT_IN_HIBERNATION); | ||
292 | mddi->int_enable |= MDDI_INT_LINK_ACTIVE; | ||
293 | } | ||
294 | |||
295 | mddi_writel(mddi->int_enable, INTEN); | ||
296 | spin_unlock(&mddi->int_lock); | ||
297 | |||
298 | return IRQ_HANDLED; | ||
299 | } | ||
300 | |||
301 | static long mddi_wait_interrupt_timeout(struct mddi_info *mddi, | ||
302 | uint32_t intmask, int timeout) | ||
303 | { | ||
304 | unsigned long irq_flags; | ||
305 | |||
306 | spin_lock_irqsave(&mddi->int_lock, irq_flags); | ||
307 | mddi->got_int &= ~intmask; | ||
308 | mddi->int_enable |= intmask; | ||
309 | mddi_writel(mddi->int_enable, INTEN); | ||
310 | spin_unlock_irqrestore(&mddi->int_lock, irq_flags); | ||
311 | return wait_event_timeout(mddi->int_wait, mddi->got_int & intmask, | ||
312 | timeout); | ||
313 | } | ||
314 | |||
315 | static void mddi_wait_interrupt(struct mddi_info *mddi, uint32_t intmask) | ||
316 | { | ||
317 | if (mddi_wait_interrupt_timeout(mddi, intmask, HZ/10) == 0) | ||
318 | printk(KERN_INFO "mddi_wait_interrupt %d, timeout " | ||
319 | "waiting for %x, INT = %x, STAT = %x gotint = %x\n", | ||
320 | current->pid, intmask, mddi_readl(INT), mddi_readl(STAT), | ||
321 | mddi->got_int); | ||
322 | } | ||
323 | |||
324 | static void mddi_init_rev_encap(struct mddi_info *mddi) | ||
325 | { | ||
326 | memset(mddi->rev_data, 0xee, MDDI_REV_BUFFER_SIZE); | ||
327 | mddi_writel(mddi->rev_addr, REV_PTR); | ||
328 | mddi_writel(MDDI_CMD_FORCE_NEW_REV_PTR, CMD); | ||
329 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
330 | } | ||
331 | |||
332 | void mddi_set_auto_hibernate(struct msm_mddi_client_data *cdata, int on) | ||
333 | { | ||
334 | struct mddi_info *mddi = container_of(cdata, struct mddi_info, | ||
335 | client_data); | ||
336 | mddi_writel(MDDI_CMD_POWERDOWN, CMD); | ||
337 | mddi_wait_interrupt(mddi, MDDI_INT_IN_HIBERNATION); | ||
338 | mddi_writel(MDDI_CMD_HIBERNATE | !!on, CMD); | ||
339 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
340 | } | ||
341 | |||
342 | |||
343 | static uint16_t mddi_init_registers(struct mddi_info *mddi) | ||
344 | { | ||
345 | mddi_writel(0x0001, VERSION); | ||
346 | mddi_writel(MDDI_HOST_BYTES_PER_SUBFRAME, BPS); | ||
347 | mddi_writel(0x0003, SPM); /* subframes per media */ | ||
348 | mddi_writel(0x0005, TA1_LEN); | ||
349 | mddi_writel(MDDI_HOST_TA2_LEN, TA2_LEN); | ||
350 | mddi_writel(0x0096, DRIVE_HI); | ||
351 | /* 0x32 normal, 0x50 for Toshiba display */ | ||
352 | mddi_writel(0x0050, DRIVE_LO); | ||
353 | mddi_writel(0x003C, DISP_WAKE); /* wakeup counter */ | ||
354 | mddi_writel(MDDI_HOST_REV_RATE_DIV, REV_RATE_DIV); | ||
355 | |||
356 | mddi_writel(MDDI_REV_BUFFER_SIZE, REV_SIZE); | ||
357 | mddi_writel(MDDI_MAX_REV_PKT_SIZE, REV_ENCAP_SZ); | ||
358 | |||
359 | /* disable periodic rev encap */ | ||
360 | mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP, CMD); | ||
361 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
362 | |||
363 | if (mddi_readl(PAD_CTL) == 0) { | ||
364 | /* If we are turning on band gap, need to wait 5us before | ||
365 | * turning on the rest of the PAD */ | ||
366 | mddi_writel(0x08000, PAD_CTL); | ||
367 | udelay(5); | ||
368 | } | ||
369 | |||
370 | /* Recommendation from PAD hw team */ | ||
371 | mddi_writel(0xa850f, PAD_CTL); | ||
372 | |||
373 | |||
374 | /* Need an even number for counts */ | ||
375 | mddi_writel(0x60006, DRIVER_START_CNT); | ||
376 | |||
377 | mddi_set_auto_hibernate(&mddi->client_data, 0); | ||
378 | |||
379 | mddi_writel(MDDI_CMD_DISP_IGNORE, CMD); | ||
380 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
381 | |||
382 | mddi_init_rev_encap(mddi); | ||
383 | return mddi_readl(CORE_VER) & 0xffff; | ||
384 | } | ||
385 | |||
386 | static void mddi_suspend(struct msm_mddi_client_data *cdata) | ||
387 | { | ||
388 | struct mddi_info *mddi = container_of(cdata, struct mddi_info, | ||
389 | client_data); | ||
390 | /* turn off the client */ | ||
391 | if (mddi->power_client) | ||
392 | mddi->power_client(&mddi->client_data, 0); | ||
393 | /* turn off the link */ | ||
394 | mddi_writel(MDDI_CMD_RESET, CMD); | ||
395 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
396 | /* turn off the clock */ | ||
397 | clk_disable(mddi->clk); | ||
398 | } | ||
399 | |||
400 | static void mddi_resume(struct msm_mddi_client_data *cdata) | ||
401 | { | ||
402 | struct mddi_info *mddi = container_of(cdata, struct mddi_info, | ||
403 | client_data); | ||
404 | mddi_set_auto_hibernate(&mddi->client_data, 0); | ||
405 | /* turn on the client */ | ||
406 | if (mddi->power_client) | ||
407 | mddi->power_client(&mddi->client_data, 1); | ||
408 | /* turn on the clock */ | ||
409 | clk_enable(mddi->clk); | ||
410 | /* set up the local registers */ | ||
411 | mddi->rev_data_curr = 0; | ||
412 | mddi_init_registers(mddi); | ||
413 | mddi_writel(mddi->int_enable, INTEN); | ||
414 | mddi_writel(MDDI_CMD_LINK_ACTIVE, CMD); | ||
415 | mddi_writel(MDDI_CMD_SEND_RTD, CMD); | ||
416 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
417 | mddi_set_auto_hibernate(&mddi->client_data, 1); | ||
418 | } | ||
419 | |||
420 | static int mddi_get_client_caps(struct mddi_info *mddi) | ||
421 | { | ||
422 | int i, j; | ||
423 | |||
424 | /* clear any stale interrupts */ | ||
425 | mddi_writel(0xffffffff, INT); | ||
426 | |||
427 | mddi->int_enable = MDDI_INT_LINK_ACTIVE | | ||
428 | MDDI_INT_IN_HIBERNATION | | ||
429 | MDDI_INT_PRI_LINK_LIST_DONE | | ||
430 | MDDI_INT_REV_DATA_AVAIL | | ||
431 | MDDI_INT_REV_OVERFLOW | | ||
432 | MDDI_INT_REV_OVERWRITE | | ||
433 | MDDI_INT_RTD_FAILURE; | ||
434 | mddi_writel(mddi->int_enable, INTEN); | ||
435 | |||
436 | mddi_writel(MDDI_CMD_LINK_ACTIVE, CMD); | ||
437 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
438 | |||
439 | for (j = 0; j < 3; j++) { | ||
440 | /* the toshiba vga panel does not respond to get | ||
441 | * caps unless you SEND_RTD, but the first SEND_RTD | ||
442 | * will fail... | ||
443 | */ | ||
444 | for (i = 0; i < 4; i++) { | ||
445 | uint32_t stat; | ||
446 | |||
447 | mddi_writel(MDDI_CMD_SEND_RTD, CMD); | ||
448 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
449 | stat = mddi_readl(STAT); | ||
450 | printk(KERN_INFO "mddi cmd send rtd: int %x, stat %x, " | ||
451 | "rtd val %x\n", mddi_readl(INT), stat, | ||
452 | mddi_readl(RTD_VAL)); | ||
453 | if ((stat & MDDI_STAT_RTD_MEAS_FAIL) == 0) | ||
454 | break; | ||
455 | msleep(1); | ||
456 | } | ||
457 | |||
458 | mddi_writel(CMD_GET_CLIENT_CAP, CMD); | ||
459 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
460 | wait_event_timeout(mddi->int_wait, mddi->flags & FLAG_HAVE_CAPS, | ||
461 | HZ / 100); | ||
462 | |||
463 | if (mddi->flags & FLAG_HAVE_CAPS) | ||
464 | break; | ||
465 | printk(KERN_INFO "mddi_init, timeout waiting for caps\n"); | ||
466 | } | ||
467 | return mddi->flags & FLAG_HAVE_CAPS; | ||
468 | } | ||
469 | |||
470 | /* link must be active when this is called */ | ||
471 | int mddi_check_status(struct mddi_info *mddi) | ||
472 | { | ||
473 | int ret = -1, retry = 3; | ||
474 | mutex_lock(&mddi->reg_read_lock); | ||
475 | mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP | 1, CMD); | ||
476 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
477 | |||
478 | do { | ||
479 | mddi->flags &= ~FLAG_HAVE_STATUS; | ||
480 | mddi_writel(CMD_GET_CLIENT_STATUS, CMD); | ||
481 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
482 | wait_event_timeout(mddi->int_wait, | ||
483 | mddi->flags & FLAG_HAVE_STATUS, | ||
484 | HZ / 100); | ||
485 | |||
486 | if (mddi->flags & FLAG_HAVE_STATUS) { | ||
487 | if (mddi->status.crc_error_count) | ||
488 | printk(KERN_INFO "mddi status: crc_error " | ||
489 | "count: %d\n", | ||
490 | mddi->status.crc_error_count); | ||
491 | else | ||
492 | ret = 0; | ||
493 | break; | ||
494 | } else | ||
495 | printk(KERN_INFO "mddi status: failed to get client " | ||
496 | "status\n"); | ||
497 | mddi_writel(MDDI_CMD_SEND_RTD, CMD); | ||
498 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
499 | } while (--retry); | ||
500 | |||
501 | mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP | 0, CMD); | ||
502 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
503 | mutex_unlock(&mddi->reg_read_lock); | ||
504 | return ret; | ||
505 | } | ||
506 | |||
507 | |||
508 | void mddi_remote_write(struct msm_mddi_client_data *cdata, uint32_t val, | ||
509 | uint32_t reg) | ||
510 | { | ||
511 | struct mddi_info *mddi = container_of(cdata, struct mddi_info, | ||
512 | client_data); | ||
513 | struct mddi_llentry *ll; | ||
514 | struct mddi_register_access *ra; | ||
515 | |||
516 | mutex_lock(&mddi->reg_write_lock); | ||
517 | |||
518 | ll = mddi->reg_write_data; | ||
519 | |||
520 | ra = &(ll->u.r); | ||
521 | ra->length = 14 + 4; | ||
522 | ra->type = TYPE_REGISTER_ACCESS; | ||
523 | ra->client_id = 0; | ||
524 | ra->read_write_info = MDDI_WRITE | 1; | ||
525 | ra->crc16 = 0; | ||
526 | |||
527 | ra->register_address = reg; | ||
528 | ra->register_data_list = val; | ||
529 | |||
530 | ll->flags = 1; | ||
531 | ll->header_count = 14; | ||
532 | ll->data_count = 4; | ||
533 | ll->data = mddi->reg_write_addr + offsetof(struct mddi_llentry, | ||
534 | u.r.register_data_list); | ||
535 | ll->next = 0; | ||
536 | ll->reserved = 0; | ||
537 | |||
538 | mddi_writel(mddi->reg_write_addr, PRI_PTR); | ||
539 | |||
540 | mddi_wait_interrupt(mddi, MDDI_INT_PRI_LINK_LIST_DONE); | ||
541 | mutex_unlock(&mddi->reg_write_lock); | ||
542 | } | ||
543 | |||
544 | uint32_t mddi_remote_read(struct msm_mddi_client_data *cdata, uint32_t reg) | ||
545 | { | ||
546 | struct mddi_info *mddi = container_of(cdata, struct mddi_info, | ||
547 | client_data); | ||
548 | struct mddi_llentry *ll; | ||
549 | struct mddi_register_access *ra; | ||
550 | struct reg_read_info ri; | ||
551 | unsigned s; | ||
552 | int retry_count = 2; | ||
553 | unsigned long irq_flags; | ||
554 | |||
555 | mutex_lock(&mddi->reg_read_lock); | ||
556 | |||
557 | ll = mddi->reg_read_data; | ||
558 | |||
559 | ra = &(ll->u.r); | ||
560 | ra->length = 14; | ||
561 | ra->type = TYPE_REGISTER_ACCESS; | ||
562 | ra->client_id = 0; | ||
563 | ra->read_write_info = MDDI_READ | 1; | ||
564 | ra->crc16 = 0; | ||
565 | |||
566 | ra->register_address = reg; | ||
567 | |||
568 | ll->flags = 0x11; | ||
569 | ll->header_count = 14; | ||
570 | ll->data_count = 0; | ||
571 | ll->data = 0; | ||
572 | ll->next = 0; | ||
573 | ll->reserved = 0; | ||
574 | |||
575 | s = mddi_readl(STAT); | ||
576 | |||
577 | ri.reg = reg; | ||
578 | ri.status = -1; | ||
579 | |||
580 | do { | ||
581 | init_completion(&ri.done); | ||
582 | mddi->reg_read = &ri; | ||
583 | mddi_writel(mddi->reg_read_addr, PRI_PTR); | ||
584 | |||
585 | mddi_wait_interrupt(mddi, MDDI_INT_PRI_LINK_LIST_DONE); | ||
586 | |||
587 | /* Enable Periodic Reverse Encapsulation. */ | ||
588 | mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP | 1, CMD); | ||
589 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
590 | if (wait_for_completion_timeout(&ri.done, HZ/10) == 0 && | ||
591 | !ri.done.done) { | ||
592 | printk(KERN_INFO "mddi_remote_read(%x) timeout " | ||
593 | "(%d %d %d)\n", | ||
594 | reg, ri.status, ri.result, ri.done.done); | ||
595 | spin_lock_irqsave(&mddi->int_lock, irq_flags); | ||
596 | mddi->reg_read = NULL; | ||
597 | spin_unlock_irqrestore(&mddi->int_lock, irq_flags); | ||
598 | ri.status = -1; | ||
599 | ri.result = -1; | ||
600 | } | ||
601 | if (ri.status == 0) | ||
602 | break; | ||
603 | |||
604 | mddi_writel(MDDI_CMD_SEND_RTD, CMD); | ||
605 | mddi_writel(MDDI_CMD_LINK_ACTIVE, CMD); | ||
606 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
607 | printk(KERN_INFO "mddi_remote_read: failed, sent " | ||
608 | "MDDI_CMD_SEND_RTD: int %x, stat %x, rtd val %x " | ||
609 | "curr_rev_ptr %x\n", mddi_readl(INT), mddi_readl(STAT), | ||
610 | mddi_readl(RTD_VAL), mddi_readl(CURR_REV_PTR)); | ||
611 | } while (retry_count-- > 0); | ||
612 | /* Disable Periodic Reverse Encapsulation. */ | ||
613 | mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP | 0, CMD); | ||
614 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
615 | mddi->reg_read = NULL; | ||
616 | mutex_unlock(&mddi->reg_read_lock); | ||
617 | return ri.result; | ||
618 | } | ||
619 | |||
620 | static struct mddi_info mddi_info[2]; | ||
621 | |||
622 | static int mddi_clk_setup(struct platform_device *pdev, struct mddi_info *mddi, | ||
623 | unsigned long clk_rate) | ||
624 | { | ||
625 | int ret; | ||
626 | |||
627 | /* set up the clocks */ | ||
628 | mddi->clk = clk_get(&pdev->dev, "mddi_clk"); | ||
629 | if (IS_ERR(mddi->clk)) { | ||
630 | printk(KERN_INFO "mddi: failed to get clock\n"); | ||
631 | return PTR_ERR(mddi->clk); | ||
632 | } | ||
633 | ret = clk_enable(mddi->clk); | ||
634 | if (ret) | ||
635 | goto fail; | ||
636 | ret = clk_set_rate(mddi->clk, clk_rate); | ||
637 | if (ret) | ||
638 | goto fail; | ||
639 | return 0; | ||
640 | |||
641 | fail: | ||
642 | clk_put(mddi->clk); | ||
643 | return ret; | ||
644 | } | ||
645 | |||
646 | static int __init mddi_rev_data_setup(struct mddi_info *mddi) | ||
647 | { | ||
648 | void *dma; | ||
649 | dma_addr_t dma_addr; | ||
650 | |||
651 | /* set up dma buffer */ | ||
652 | dma = dma_alloc_coherent(NULL, 0x1000, &dma_addr, GFP_KERNEL); | ||
653 | if (dma == 0) | ||
654 | return -ENOMEM; | ||
655 | mddi->rev_data = dma; | ||
656 | mddi->rev_data_curr = 0; | ||
657 | mddi->rev_addr = dma_addr; | ||
658 | mddi->reg_write_data = dma + MDDI_REV_BUFFER_SIZE; | ||
659 | mddi->reg_write_addr = dma_addr + MDDI_REV_BUFFER_SIZE; | ||
660 | mddi->reg_read_data = mddi->reg_write_data + 1; | ||
661 | mddi->reg_read_addr = mddi->reg_write_addr + | ||
662 | sizeof(*mddi->reg_write_data); | ||
663 | return 0; | ||
664 | } | ||
665 | |||
666 | static int mddi_probe(struct platform_device *pdev) | ||
667 | { | ||
668 | struct msm_mddi_platform_data *pdata = pdev->dev.platform_data; | ||
669 | struct mddi_info *mddi = &mddi_info[pdev->id]; | ||
670 | struct resource *resource; | ||
671 | int ret, i; | ||
672 | |||
673 | resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
674 | if (!resource) { | ||
675 | printk(KERN_ERR "mddi: no associated mem resource!\n"); | ||
676 | return -ENOMEM; | ||
677 | } | ||
678 | mddi->base = ioremap(resource->start, resource_size(resource)); | ||
679 | if (!mddi->base) { | ||
680 | printk(KERN_ERR "mddi: failed to remap base!\n"); | ||
681 | ret = -EINVAL; | ||
682 | goto error_ioremap; | ||
683 | } | ||
684 | resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
685 | if (!resource) { | ||
686 | printk(KERN_ERR "mddi: no associated irq resource!\n"); | ||
687 | ret = -EINVAL; | ||
688 | goto error_get_irq_resource; | ||
689 | } | ||
690 | mddi->irq = resource->start; | ||
691 | printk(KERN_INFO "mddi: init() base=0x%p irq=%d\n", mddi->base, | ||
692 | mddi->irq); | ||
693 | mddi->power_client = pdata->power_client; | ||
694 | |||
695 | mutex_init(&mddi->reg_write_lock); | ||
696 | mutex_init(&mddi->reg_read_lock); | ||
697 | spin_lock_init(&mddi->int_lock); | ||
698 | init_waitqueue_head(&mddi->int_wait); | ||
699 | |||
700 | ret = mddi_clk_setup(pdev, mddi, pdata->clk_rate); | ||
701 | if (ret) { | ||
702 | printk(KERN_ERR "mddi: failed to setup clock!\n"); | ||
703 | goto error_clk_setup; | ||
704 | } | ||
705 | |||
706 | ret = mddi_rev_data_setup(mddi); | ||
707 | if (ret) { | ||
708 | printk(KERN_ERR "mddi: failed to setup rev data!\n"); | ||
709 | goto error_rev_data; | ||
710 | } | ||
711 | |||
712 | mddi->int_enable = 0; | ||
713 | mddi_writel(mddi->int_enable, INTEN); | ||
714 | ret = request_irq(mddi->irq, mddi_isr, 0, "mddi", | ||
715 | &mddi->client_data); | ||
716 | if (ret) { | ||
717 | printk(KERN_ERR "mddi: failed to request enable irq!\n"); | ||
718 | goto error_request_irq; | ||
719 | } | ||
720 | |||
721 | /* turn on the mddi client bridge chip */ | ||
722 | if (mddi->power_client) | ||
723 | mddi->power_client(&mddi->client_data, 1); | ||
724 | |||
725 | /* initialize the mddi registers */ | ||
726 | mddi_set_auto_hibernate(&mddi->client_data, 0); | ||
727 | mddi_writel(MDDI_CMD_RESET, CMD); | ||
728 | mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND); | ||
729 | mddi->version = mddi_init_registers(mddi); | ||
730 | if (mddi->version < 0x20) { | ||
731 | printk(KERN_ERR "mddi: unsupported version 0x%x\n", | ||
732 | mddi->version); | ||
733 | ret = -ENODEV; | ||
734 | goto error_mddi_version; | ||
735 | } | ||
736 | |||
737 | /* read the capabilities off the client */ | ||
738 | if (!mddi_get_client_caps(mddi)) { | ||
739 | printk(KERN_INFO "mddi: no client found\n"); | ||
740 | /* power down the panel */ | ||
741 | mddi_writel(MDDI_CMD_POWERDOWN, CMD); | ||
742 | printk(KERN_INFO "mddi powerdown: stat %x\n", mddi_readl(STAT)); | ||
743 | msleep(100); | ||
744 | printk(KERN_INFO "mddi powerdown: stat %x\n", mddi_readl(STAT)); | ||
745 | return 0; | ||
746 | } | ||
747 | mddi_set_auto_hibernate(&mddi->client_data, 1); | ||
748 | |||
749 | if (mddi->caps.Mfr_Name == 0 && mddi->caps.Product_Code == 0) | ||
750 | pdata->fixup(&mddi->caps.Mfr_Name, &mddi->caps.Product_Code); | ||
751 | |||
752 | mddi->client_pdev.id = 0; | ||
753 | for (i = 0; i < pdata->num_clients; i++) { | ||
754 | if (pdata->client_platform_data[i].product_id == | ||
755 | (mddi->caps.Mfr_Name << 16 | mddi->caps.Product_Code)) { | ||
756 | mddi->client_data.private_client_data = | ||
757 | pdata->client_platform_data[i].client_data; | ||
758 | mddi->client_pdev.name = | ||
759 | pdata->client_platform_data[i].name; | ||
760 | mddi->client_pdev.id = | ||
761 | pdata->client_platform_data[i].id; | ||
762 | /* XXX: possibly set clock */ | ||
763 | break; | ||
764 | } | ||
765 | } | ||
766 | |||
767 | if (i >= pdata->num_clients) | ||
768 | mddi->client_pdev.name = "mddi_c_dummy"; | ||
769 | printk(KERN_INFO "mddi: registering panel %s\n", | ||
770 | mddi->client_pdev.name); | ||
771 | |||
772 | mddi->client_data.suspend = mddi_suspend; | ||
773 | mddi->client_data.resume = mddi_resume; | ||
774 | mddi->client_data.activate_link = mddi_activate_link; | ||
775 | mddi->client_data.remote_write = mddi_remote_write; | ||
776 | mddi->client_data.remote_read = mddi_remote_read; | ||
777 | mddi->client_data.auto_hibernate = mddi_set_auto_hibernate; | ||
778 | mddi->client_data.fb_resource = pdata->fb_resource; | ||
779 | if (pdev->id == 0) | ||
780 | mddi->client_data.interface_type = MSM_MDDI_PMDH_INTERFACE; | ||
781 | else if (pdev->id == 1) | ||
782 | mddi->client_data.interface_type = MSM_MDDI_EMDH_INTERFACE; | ||
783 | else { | ||
784 | printk(KERN_ERR "mddi: can not determine interface %d!\n", | ||
785 | pdev->id); | ||
786 | ret = -EINVAL; | ||
787 | goto error_mddi_interface; | ||
788 | } | ||
789 | |||
790 | mddi->client_pdev.dev.platform_data = &mddi->client_data; | ||
791 | printk(KERN_INFO "mddi: publish: %s\n", mddi->client_name); | ||
792 | platform_device_register(&mddi->client_pdev); | ||
793 | return 0; | ||
794 | |||
795 | error_mddi_interface: | ||
796 | error_mddi_version: | ||
797 | free_irq(mddi->irq, 0); | ||
798 | error_request_irq: | ||
799 | dma_free_coherent(NULL, 0x1000, mddi->rev_data, mddi->rev_addr); | ||
800 | error_rev_data: | ||
801 | error_clk_setup: | ||
802 | error_get_irq_resource: | ||
803 | iounmap(mddi->base); | ||
804 | error_ioremap: | ||
805 | |||
806 | printk(KERN_INFO "mddi: mddi_init() failed (%d)\n", ret); | ||
807 | return ret; | ||
808 | } | ||
809 | |||
810 | |||
811 | static struct platform_driver mddi_driver = { | ||
812 | .probe = mddi_probe, | ||
813 | .driver = { .name = "msm_mddi" }, | ||
814 | }; | ||
815 | |||
816 | static int __init _mddi_init(void) | ||
817 | { | ||
818 | return platform_driver_register(&mddi_driver); | ||
819 | } | ||
820 | |||
821 | module_init(_mddi_init); | ||
diff --git a/drivers/video/fbdev/msm/mddi_client_dummy.c b/drivers/video/fbdev/msm/mddi_client_dummy.c deleted file mode 100644 index cdb8f69a5d88..000000000000 --- a/drivers/video/fbdev/msm/mddi_client_dummy.c +++ /dev/null | |||
@@ -1,85 +0,0 @@ | |||
1 | /* drivers/video/msm_fb/mddi_client_dummy.c | ||
2 | * | ||
3 | * Support for "dummy" mddi client devices which require no | ||
4 | * special initialization code. | ||
5 | * | ||
6 | * Copyright (C) 2007 Google Incorporated | ||
7 | * | ||
8 | * This software is licensed under the terms of the GNU General Public | ||
9 | * License version 2, as published by the Free Software Foundation, and | ||
10 | * may be copied, distributed, and modified under those terms. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | */ | ||
17 | |||
18 | #include <linux/device.h> | ||
19 | #include <linux/slab.h> | ||
20 | #include <linux/module.h> | ||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/platform_device.h> | ||
23 | |||
24 | #include <linux/platform_data/video-msm_fb.h> | ||
25 | |||
26 | struct panel_info { | ||
27 | struct platform_device pdev; | ||
28 | struct msm_panel_data panel_data; | ||
29 | }; | ||
30 | |||
31 | static int mddi_dummy_suspend(struct msm_panel_data *panel_data) | ||
32 | { | ||
33 | return 0; | ||
34 | } | ||
35 | |||
36 | static int mddi_dummy_resume(struct msm_panel_data *panel_data) | ||
37 | { | ||
38 | return 0; | ||
39 | } | ||
40 | |||
41 | static int mddi_dummy_blank(struct msm_panel_data *panel_data) | ||
42 | { | ||
43 | return 0; | ||
44 | } | ||
45 | |||
46 | static int mddi_dummy_unblank(struct msm_panel_data *panel_data) | ||
47 | { | ||
48 | return 0; | ||
49 | } | ||
50 | |||
51 | static int mddi_dummy_probe(struct platform_device *pdev) | ||
52 | { | ||
53 | struct msm_mddi_client_data *client_data = pdev->dev.platform_data; | ||
54 | struct panel_info *panel = | ||
55 | devm_kzalloc(&pdev->dev, sizeof(struct panel_info), GFP_KERNEL); | ||
56 | if (!panel) | ||
57 | return -ENOMEM; | ||
58 | platform_set_drvdata(pdev, panel); | ||
59 | panel->panel_data.suspend = mddi_dummy_suspend; | ||
60 | panel->panel_data.resume = mddi_dummy_resume; | ||
61 | panel->panel_data.blank = mddi_dummy_blank; | ||
62 | panel->panel_data.unblank = mddi_dummy_unblank; | ||
63 | panel->panel_data.caps = MSMFB_CAP_PARTIAL_UPDATES; | ||
64 | panel->pdev.name = "msm_panel"; | ||
65 | panel->pdev.id = pdev->id; | ||
66 | platform_device_add_resources(&panel->pdev, | ||
67 | client_data->fb_resource, 1); | ||
68 | panel->panel_data.fb_data = client_data->private_client_data; | ||
69 | panel->pdev.dev.platform_data = &panel->panel_data; | ||
70 | return platform_device_register(&panel->pdev); | ||
71 | } | ||
72 | |||
73 | static struct platform_driver mddi_client_dummy = { | ||
74 | .probe = mddi_dummy_probe, | ||
75 | .driver = { .name = "mddi_c_dummy" }, | ||
76 | }; | ||
77 | |||
78 | static int __init mddi_client_dummy_init(void) | ||
79 | { | ||
80 | platform_driver_register(&mddi_client_dummy); | ||
81 | return 0; | ||
82 | } | ||
83 | |||
84 | module_init(mddi_client_dummy_init); | ||
85 | |||
diff --git a/drivers/video/fbdev/msm/mddi_client_nt35399.c b/drivers/video/fbdev/msm/mddi_client_nt35399.c deleted file mode 100644 index f96df32e5509..000000000000 --- a/drivers/video/fbdev/msm/mddi_client_nt35399.c +++ /dev/null | |||
@@ -1,252 +0,0 @@ | |||
1 | /* drivers/video/msm_fb/mddi_client_nt35399.c | ||
2 | * | ||
3 | * Support for Novatek NT35399 MDDI client of Sapphire | ||
4 | * | ||
5 | * Copyright (C) 2008 HTC Incorporated | ||
6 | * Author: Solomon Chiu (solomon_chiu@htc.com) | ||
7 | * | ||
8 | * This software is licensed under the terms of the GNU General Public | ||
9 | * License version 2, as published by the Free Software Foundation, and | ||
10 | * may be copied, distributed, and modified under those terms. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | */ | ||
17 | |||
18 | #include <linux/module.h> | ||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/interrupt.h> | ||
22 | #include <linux/sched.h> | ||
23 | #include <linux/gpio.h> | ||
24 | #include <linux/slab.h> | ||
25 | #include <linux/platform_data/video-msm_fb.h> | ||
26 | |||
27 | static DECLARE_WAIT_QUEUE_HEAD(nt35399_vsync_wait); | ||
28 | |||
29 | struct panel_info { | ||
30 | struct msm_mddi_client_data *client_data; | ||
31 | struct platform_device pdev; | ||
32 | struct msm_panel_data panel_data; | ||
33 | struct msmfb_callback *fb_callback; | ||
34 | struct work_struct panel_work; | ||
35 | struct workqueue_struct *fb_wq; | ||
36 | int nt35399_got_int; | ||
37 | }; | ||
38 | |||
39 | static void | ||
40 | nt35399_request_vsync(struct msm_panel_data *panel_data, | ||
41 | struct msmfb_callback *callback) | ||
42 | { | ||
43 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
44 | panel_data); | ||
45 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
46 | |||
47 | panel->fb_callback = callback; | ||
48 | if (panel->nt35399_got_int) { | ||
49 | panel->nt35399_got_int = 0; | ||
50 | client_data->activate_link(client_data); /* clears interrupt */ | ||
51 | } | ||
52 | } | ||
53 | |||
54 | static void nt35399_wait_vsync(struct msm_panel_data *panel_data) | ||
55 | { | ||
56 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
57 | panel_data); | ||
58 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
59 | |||
60 | if (panel->nt35399_got_int) { | ||
61 | panel->nt35399_got_int = 0; | ||
62 | client_data->activate_link(client_data); /* clears interrupt */ | ||
63 | } | ||
64 | |||
65 | if (wait_event_timeout(nt35399_vsync_wait, panel->nt35399_got_int, | ||
66 | HZ/2) == 0) | ||
67 | printk(KERN_ERR "timeout waiting for VSYNC\n"); | ||
68 | |||
69 | panel->nt35399_got_int = 0; | ||
70 | /* interrupt clears when screen dma starts */ | ||
71 | } | ||
72 | |||
73 | static int nt35399_suspend(struct msm_panel_data *panel_data) | ||
74 | { | ||
75 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
76 | panel_data); | ||
77 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
78 | |||
79 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
80 | client_data->private_client_data; | ||
81 | int ret; | ||
82 | |||
83 | ret = bridge_data->uninit(bridge_data, client_data); | ||
84 | if (ret) { | ||
85 | printk(KERN_INFO "mddi nt35399 client: non zero return from " | ||
86 | "uninit\n"); | ||
87 | return ret; | ||
88 | } | ||
89 | client_data->suspend(client_data); | ||
90 | return 0; | ||
91 | } | ||
92 | |||
93 | static int nt35399_resume(struct msm_panel_data *panel_data) | ||
94 | { | ||
95 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
96 | panel_data); | ||
97 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
98 | |||
99 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
100 | client_data->private_client_data; | ||
101 | int ret; | ||
102 | |||
103 | client_data->resume(client_data); | ||
104 | ret = bridge_data->init(bridge_data, client_data); | ||
105 | if (ret) | ||
106 | return ret; | ||
107 | return 0; | ||
108 | } | ||
109 | |||
110 | static int nt35399_blank(struct msm_panel_data *panel_data) | ||
111 | { | ||
112 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
113 | panel_data); | ||
114 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
115 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
116 | client_data->private_client_data; | ||
117 | |||
118 | return bridge_data->blank(bridge_data, client_data); | ||
119 | } | ||
120 | |||
121 | static int nt35399_unblank(struct msm_panel_data *panel_data) | ||
122 | { | ||
123 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
124 | panel_data); | ||
125 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
126 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
127 | client_data->private_client_data; | ||
128 | |||
129 | return bridge_data->unblank(bridge_data, client_data); | ||
130 | } | ||
131 | |||
132 | irqreturn_t nt35399_vsync_interrupt(int irq, void *data) | ||
133 | { | ||
134 | struct panel_info *panel = data; | ||
135 | |||
136 | panel->nt35399_got_int = 1; | ||
137 | |||
138 | if (panel->fb_callback) { | ||
139 | panel->fb_callback->func(panel->fb_callback); | ||
140 | panel->fb_callback = NULL; | ||
141 | } | ||
142 | |||
143 | wake_up(&nt35399_vsync_wait); | ||
144 | |||
145 | return IRQ_HANDLED; | ||
146 | } | ||
147 | |||
148 | static int setup_vsync(struct panel_info *panel, int init) | ||
149 | { | ||
150 | int ret; | ||
151 | int gpio = 97; | ||
152 | unsigned int irq; | ||
153 | |||
154 | if (!init) { | ||
155 | ret = 0; | ||
156 | goto uninit; | ||
157 | } | ||
158 | ret = gpio_request_one(gpio, GPIOF_IN, "vsync"); | ||
159 | if (ret) | ||
160 | goto err_request_gpio_failed; | ||
161 | |||
162 | ret = irq = gpio_to_irq(gpio); | ||
163 | if (ret < 0) | ||
164 | goto err_get_irq_num_failed; | ||
165 | |||
166 | ret = request_irq(irq, nt35399_vsync_interrupt, IRQF_TRIGGER_RISING, | ||
167 | "vsync", panel); | ||
168 | if (ret) | ||
169 | goto err_request_irq_failed; | ||
170 | |||
171 | printk(KERN_INFO "vsync on gpio %d now %d\n", | ||
172 | gpio, gpio_get_value(gpio)); | ||
173 | return 0; | ||
174 | |||
175 | uninit: | ||
176 | free_irq(gpio_to_irq(gpio), panel->client_data); | ||
177 | err_request_irq_failed: | ||
178 | err_get_irq_num_failed: | ||
179 | gpio_free(gpio); | ||
180 | err_request_gpio_failed: | ||
181 | return ret; | ||
182 | } | ||
183 | |||
184 | static int mddi_nt35399_probe(struct platform_device *pdev) | ||
185 | { | ||
186 | struct msm_mddi_client_data *client_data = pdev->dev.platform_data; | ||
187 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
188 | client_data->private_client_data; | ||
189 | |||
190 | int ret; | ||
191 | |||
192 | struct panel_info *panel = devm_kzalloc(&pdev->dev, | ||
193 | sizeof(struct panel_info), | ||
194 | GFP_KERNEL); | ||
195 | |||
196 | printk(KERN_DEBUG "%s: enter.\n", __func__); | ||
197 | |||
198 | if (!panel) | ||
199 | return -ENOMEM; | ||
200 | platform_set_drvdata(pdev, panel); | ||
201 | |||
202 | ret = setup_vsync(panel, 1); | ||
203 | if (ret) { | ||
204 | dev_err(&pdev->dev, "mddi_nt35399_setup_vsync failed\n"); | ||
205 | return ret; | ||
206 | } | ||
207 | |||
208 | panel->client_data = client_data; | ||
209 | panel->panel_data.suspend = nt35399_suspend; | ||
210 | panel->panel_data.resume = nt35399_resume; | ||
211 | panel->panel_data.wait_vsync = nt35399_wait_vsync; | ||
212 | panel->panel_data.request_vsync = nt35399_request_vsync; | ||
213 | panel->panel_data.blank = nt35399_blank; | ||
214 | panel->panel_data.unblank = nt35399_unblank; | ||
215 | panel->panel_data.fb_data = &bridge_data->fb_data; | ||
216 | panel->panel_data.caps = 0; | ||
217 | |||
218 | panel->pdev.name = "msm_panel"; | ||
219 | panel->pdev.id = pdev->id; | ||
220 | panel->pdev.resource = client_data->fb_resource; | ||
221 | panel->pdev.num_resources = 1; | ||
222 | panel->pdev.dev.platform_data = &panel->panel_data; | ||
223 | |||
224 | if (bridge_data->init) | ||
225 | bridge_data->init(bridge_data, client_data); | ||
226 | |||
227 | platform_device_register(&panel->pdev); | ||
228 | |||
229 | return 0; | ||
230 | } | ||
231 | |||
232 | static int mddi_nt35399_remove(struct platform_device *pdev) | ||
233 | { | ||
234 | struct panel_info *panel = platform_get_drvdata(pdev); | ||
235 | |||
236 | setup_vsync(panel, 0); | ||
237 | return 0; | ||
238 | } | ||
239 | |||
240 | static struct platform_driver mddi_client_0bda_8a47 = { | ||
241 | .probe = mddi_nt35399_probe, | ||
242 | .remove = mddi_nt35399_remove, | ||
243 | .driver = { .name = "mddi_c_0bda_8a47" }, | ||
244 | }; | ||
245 | |||
246 | static int __init mddi_client_nt35399_init(void) | ||
247 | { | ||
248 | return platform_driver_register(&mddi_client_0bda_8a47); | ||
249 | } | ||
250 | |||
251 | module_init(mddi_client_nt35399_init); | ||
252 | |||
diff --git a/drivers/video/fbdev/msm/mddi_client_toshiba.c b/drivers/video/fbdev/msm/mddi_client_toshiba.c deleted file mode 100644 index 061d7dfebbf3..000000000000 --- a/drivers/video/fbdev/msm/mddi_client_toshiba.c +++ /dev/null | |||
@@ -1,280 +0,0 @@ | |||
1 | /* drivers/video/msm_fb/mddi_client_toshiba.c | ||
2 | * | ||
3 | * Support for Toshiba TC358720XBG mddi client devices which require no | ||
4 | * special initialization code. | ||
5 | * | ||
6 | * Copyright (C) 2007 Google Incorporated | ||
7 | * | ||
8 | * This software is licensed under the terms of the GNU General Public | ||
9 | * License version 2, as published by the Free Software Foundation, and | ||
10 | * may be copied, distributed, and modified under those terms. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | */ | ||
17 | |||
18 | #include <linux/module.h> | ||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/interrupt.h> | ||
22 | #include <linux/gpio.h> | ||
23 | #include <linux/sched.h> | ||
24 | #include <linux/slab.h> | ||
25 | #include <linux/platform_data/video-msm_fb.h> | ||
26 | |||
27 | |||
28 | #define LCD_CONTROL_BLOCK_BASE 0x110000 | ||
29 | #define CMN (LCD_CONTROL_BLOCK_BASE|0x10) | ||
30 | #define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) | ||
31 | #define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) | ||
32 | #define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) | ||
33 | #define VPOS (LCD_CONTROL_BLOCK_BASE|0xC0) | ||
34 | #define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) | ||
35 | #define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) | ||
36 | #define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58) | ||
37 | #define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) | ||
38 | |||
39 | #define BASE5 0x150000 | ||
40 | #define BASE6 0x160000 | ||
41 | #define BASE7 0x170000 | ||
42 | |||
43 | #define GPIOIEV (BASE5 + 0x10) | ||
44 | #define GPIOIE (BASE5 + 0x14) | ||
45 | #define GPIORIS (BASE5 + 0x18) | ||
46 | #define GPIOMIS (BASE5 + 0x1C) | ||
47 | #define GPIOIC (BASE5 + 0x20) | ||
48 | |||
49 | #define INTMASK (BASE6 + 0x0C) | ||
50 | #define INTMASK_VWAKEOUT (1U << 0) | ||
51 | #define INTMASK_VWAKEOUT_ACTIVE_LOW (1U << 8) | ||
52 | #define GPIOSEL (BASE7 + 0x00) | ||
53 | #define GPIOSEL_VWAKEINT (1U << 0) | ||
54 | |||
55 | static DECLARE_WAIT_QUEUE_HEAD(toshiba_vsync_wait); | ||
56 | |||
57 | struct panel_info { | ||
58 | struct msm_mddi_client_data *client_data; | ||
59 | struct platform_device pdev; | ||
60 | struct msm_panel_data panel_data; | ||
61 | struct msmfb_callback *toshiba_callback; | ||
62 | int toshiba_got_int; | ||
63 | }; | ||
64 | |||
65 | |||
66 | static void toshiba_request_vsync(struct msm_panel_data *panel_data, | ||
67 | struct msmfb_callback *callback) | ||
68 | { | ||
69 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
70 | panel_data); | ||
71 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
72 | |||
73 | panel->toshiba_callback = callback; | ||
74 | if (panel->toshiba_got_int) { | ||
75 | panel->toshiba_got_int = 0; | ||
76 | client_data->activate_link(client_data); | ||
77 | } | ||
78 | } | ||
79 | |||
80 | static void toshiba_clear_vsync(struct msm_panel_data *panel_data) | ||
81 | { | ||
82 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
83 | panel_data); | ||
84 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
85 | |||
86 | client_data->activate_link(client_data); | ||
87 | } | ||
88 | |||
89 | static void toshiba_wait_vsync(struct msm_panel_data *panel_data) | ||
90 | { | ||
91 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
92 | panel_data); | ||
93 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
94 | |||
95 | if (panel->toshiba_got_int) { | ||
96 | panel->toshiba_got_int = 0; | ||
97 | client_data->activate_link(client_data); /* clears interrupt */ | ||
98 | } | ||
99 | if (wait_event_timeout(toshiba_vsync_wait, panel->toshiba_got_int, | ||
100 | HZ/2) == 0) | ||
101 | printk(KERN_ERR "timeout waiting for VSYNC\n"); | ||
102 | panel->toshiba_got_int = 0; | ||
103 | /* interrupt clears when screen dma starts */ | ||
104 | } | ||
105 | |||
106 | static int toshiba_suspend(struct msm_panel_data *panel_data) | ||
107 | { | ||
108 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
109 | panel_data); | ||
110 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
111 | |||
112 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
113 | client_data->private_client_data; | ||
114 | int ret; | ||
115 | |||
116 | ret = bridge_data->uninit(bridge_data, client_data); | ||
117 | if (ret) { | ||
118 | printk(KERN_INFO "mddi toshiba client: non zero return from " | ||
119 | "uninit\n"); | ||
120 | return ret; | ||
121 | } | ||
122 | client_data->suspend(client_data); | ||
123 | return 0; | ||
124 | } | ||
125 | |||
126 | static int toshiba_resume(struct msm_panel_data *panel_data) | ||
127 | { | ||
128 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
129 | panel_data); | ||
130 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
131 | |||
132 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
133 | client_data->private_client_data; | ||
134 | int ret; | ||
135 | |||
136 | client_data->resume(client_data); | ||
137 | ret = bridge_data->init(bridge_data, client_data); | ||
138 | if (ret) | ||
139 | return ret; | ||
140 | return 0; | ||
141 | } | ||
142 | |||
143 | static int toshiba_blank(struct msm_panel_data *panel_data) | ||
144 | { | ||
145 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
146 | panel_data); | ||
147 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
148 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
149 | client_data->private_client_data; | ||
150 | |||
151 | return bridge_data->blank(bridge_data, client_data); | ||
152 | } | ||
153 | |||
154 | static int toshiba_unblank(struct msm_panel_data *panel_data) | ||
155 | { | ||
156 | struct panel_info *panel = container_of(panel_data, struct panel_info, | ||
157 | panel_data); | ||
158 | struct msm_mddi_client_data *client_data = panel->client_data; | ||
159 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
160 | client_data->private_client_data; | ||
161 | |||
162 | return bridge_data->unblank(bridge_data, client_data); | ||
163 | } | ||
164 | |||
165 | irqreturn_t toshiba_vsync_interrupt(int irq, void *data) | ||
166 | { | ||
167 | struct panel_info *panel = data; | ||
168 | |||
169 | panel->toshiba_got_int = 1; | ||
170 | if (panel->toshiba_callback) { | ||
171 | panel->toshiba_callback->func(panel->toshiba_callback); | ||
172 | panel->toshiba_callback = 0; | ||
173 | } | ||
174 | wake_up(&toshiba_vsync_wait); | ||
175 | return IRQ_HANDLED; | ||
176 | } | ||
177 | |||
178 | static int setup_vsync(struct panel_info *panel, | ||
179 | int init) | ||
180 | { | ||
181 | int ret; | ||
182 | int gpio = 97; | ||
183 | unsigned int irq; | ||
184 | |||
185 | if (!init) { | ||
186 | ret = 0; | ||
187 | goto uninit; | ||
188 | } | ||
189 | ret = gpio_request_one(gpio, GPIOF_IN, "vsync"); | ||
190 | if (ret) | ||
191 | goto err_request_gpio_failed; | ||
192 | |||
193 | ret = irq = gpio_to_irq(gpio); | ||
194 | if (ret < 0) | ||
195 | goto err_get_irq_num_failed; | ||
196 | |||
197 | ret = request_irq(irq, toshiba_vsync_interrupt, IRQF_TRIGGER_RISING, | ||
198 | "vsync", panel); | ||
199 | if (ret) | ||
200 | goto err_request_irq_failed; | ||
201 | printk(KERN_INFO "vsync on gpio %d now %d\n", | ||
202 | gpio, gpio_get_value(gpio)); | ||
203 | return 0; | ||
204 | |||
205 | uninit: | ||
206 | free_irq(gpio_to_irq(gpio), panel); | ||
207 | err_request_irq_failed: | ||
208 | err_get_irq_num_failed: | ||
209 | gpio_free(gpio); | ||
210 | err_request_gpio_failed: | ||
211 | return ret; | ||
212 | } | ||
213 | |||
214 | static int mddi_toshiba_probe(struct platform_device *pdev) | ||
215 | { | ||
216 | int ret; | ||
217 | struct msm_mddi_client_data *client_data = pdev->dev.platform_data; | ||
218 | struct msm_mddi_bridge_platform_data *bridge_data = | ||
219 | client_data->private_client_data; | ||
220 | struct panel_info *panel = | ||
221 | kzalloc(sizeof(struct panel_info), GFP_KERNEL); | ||
222 | if (!panel) | ||
223 | return -ENOMEM; | ||
224 | platform_set_drvdata(pdev, panel); | ||
225 | |||
226 | /* mddi_remote_write(mddi, 0, WAKEUP); */ | ||
227 | client_data->remote_write(client_data, GPIOSEL_VWAKEINT, GPIOSEL); | ||
228 | client_data->remote_write(client_data, INTMASK_VWAKEOUT, INTMASK); | ||
229 | |||
230 | ret = setup_vsync(panel, 1); | ||
231 | if (ret) { | ||
232 | dev_err(&pdev->dev, "mddi_bridge_setup_vsync failed\n"); | ||
233 | return ret; | ||
234 | } | ||
235 | |||
236 | panel->client_data = client_data; | ||
237 | panel->panel_data.suspend = toshiba_suspend; | ||
238 | panel->panel_data.resume = toshiba_resume; | ||
239 | panel->panel_data.wait_vsync = toshiba_wait_vsync; | ||
240 | panel->panel_data.request_vsync = toshiba_request_vsync; | ||
241 | panel->panel_data.clear_vsync = toshiba_clear_vsync; | ||
242 | panel->panel_data.blank = toshiba_blank; | ||
243 | panel->panel_data.unblank = toshiba_unblank; | ||
244 | panel->panel_data.fb_data = &bridge_data->fb_data; | ||
245 | panel->panel_data.caps = MSMFB_CAP_PARTIAL_UPDATES; | ||
246 | |||
247 | panel->pdev.name = "msm_panel"; | ||
248 | panel->pdev.id = pdev->id; | ||
249 | panel->pdev.resource = client_data->fb_resource; | ||
250 | panel->pdev.num_resources = 1; | ||
251 | panel->pdev.dev.platform_data = &panel->panel_data; | ||
252 | bridge_data->init(bridge_data, client_data); | ||
253 | platform_device_register(&panel->pdev); | ||
254 | |||
255 | return 0; | ||
256 | } | ||
257 | |||
258 | static int mddi_toshiba_remove(struct platform_device *pdev) | ||
259 | { | ||
260 | struct panel_info *panel = platform_get_drvdata(pdev); | ||
261 | |||
262 | setup_vsync(panel, 0); | ||
263 | kfree(panel); | ||
264 | return 0; | ||
265 | } | ||
266 | |||
267 | static struct platform_driver mddi_client_d263_0000 = { | ||
268 | .probe = mddi_toshiba_probe, | ||
269 | .remove = mddi_toshiba_remove, | ||
270 | .driver = { .name = "mddi_c_d263_0000" }, | ||
271 | }; | ||
272 | |||
273 | static int __init mddi_client_toshiba_init(void) | ||
274 | { | ||
275 | platform_driver_register(&mddi_client_d263_0000); | ||
276 | return 0; | ||
277 | } | ||
278 | |||
279 | module_init(mddi_client_toshiba_init); | ||
280 | |||
diff --git a/drivers/video/fbdev/msm/mddi_hw.h b/drivers/video/fbdev/msm/mddi_hw.h deleted file mode 100644 index 45cc01fc1e7f..000000000000 --- a/drivers/video/fbdev/msm/mddi_hw.h +++ /dev/null | |||
@@ -1,305 +0,0 @@ | |||
1 | /* drivers/video/msm_fb/mddi_hw.h | ||
2 | * | ||
3 | * MSM MDDI Hardware Registers and Structures | ||
4 | * | ||
5 | * Copyright (C) 2007 QUALCOMM Incorporated | ||
6 | * Copyright (C) 2007 Google Incorporated | ||
7 | * | ||
8 | * This software is licensed under the terms of the GNU General Public | ||
9 | * License version 2, as published by the Free Software Foundation, and | ||
10 | * may be copied, distributed, and modified under those terms. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | */ | ||
17 | |||
18 | #ifndef _MDDI_HW_H_ | ||
19 | #define _MDDI_HW_H_ | ||
20 | |||
21 | #include <linux/types.h> | ||
22 | |||
23 | #define MDDI_CMD 0x0000 | ||
24 | #define MDDI_VERSION 0x0004 | ||
25 | #define MDDI_PRI_PTR 0x0008 | ||
26 | #define MDDI_SEC_PTR 0x000c | ||
27 | #define MDDI_BPS 0x0010 | ||
28 | #define MDDI_SPM 0x0014 | ||
29 | #define MDDI_INT 0x0018 | ||
30 | #define MDDI_INTEN 0x001c | ||
31 | #define MDDI_REV_PTR 0x0020 | ||
32 | #define MDDI_REV_SIZE 0x0024 | ||
33 | #define MDDI_STAT 0x0028 | ||
34 | #define MDDI_REV_RATE_DIV 0x002c | ||
35 | #define MDDI_REV_CRC_ERR 0x0030 | ||
36 | #define MDDI_TA1_LEN 0x0034 | ||
37 | #define MDDI_TA2_LEN 0x0038 | ||
38 | #define MDDI_TEST_BUS 0x003c | ||
39 | #define MDDI_TEST 0x0040 | ||
40 | #define MDDI_REV_PKT_CNT 0x0044 | ||
41 | #define MDDI_DRIVE_HI 0x0048 | ||
42 | #define MDDI_DRIVE_LO 0x004c | ||
43 | #define MDDI_DISP_WAKE 0x0050 | ||
44 | #define MDDI_REV_ENCAP_SZ 0x0054 | ||
45 | #define MDDI_RTD_VAL 0x0058 | ||
46 | #define MDDI_PAD_CTL 0x0068 | ||
47 | #define MDDI_DRIVER_START_CNT 0x006c | ||
48 | #define MDDI_NEXT_PRI_PTR 0x0070 | ||
49 | #define MDDI_NEXT_SEC_PTR 0x0074 | ||
50 | #define MDDI_MISR_CTL 0x0078 | ||
51 | #define MDDI_MISR_DATA 0x007c | ||
52 | #define MDDI_SF_CNT 0x0080 | ||
53 | #define MDDI_MF_CNT 0x0084 | ||
54 | #define MDDI_CURR_REV_PTR 0x0088 | ||
55 | #define MDDI_CORE_VER 0x008c | ||
56 | |||
57 | #define MDDI_INT_PRI_PTR_READ 0x0001 | ||
58 | #define MDDI_INT_SEC_PTR_READ 0x0002 | ||
59 | #define MDDI_INT_REV_DATA_AVAIL 0x0004 | ||
60 | #define MDDI_INT_DISP_REQ 0x0008 | ||
61 | #define MDDI_INT_PRI_UNDERFLOW 0x0010 | ||
62 | #define MDDI_INT_SEC_UNDERFLOW 0x0020 | ||
63 | #define MDDI_INT_REV_OVERFLOW 0x0040 | ||
64 | #define MDDI_INT_CRC_ERROR 0x0080 | ||
65 | #define MDDI_INT_MDDI_IN 0x0100 | ||
66 | #define MDDI_INT_PRI_OVERWRITE 0x0200 | ||
67 | #define MDDI_INT_SEC_OVERWRITE 0x0400 | ||
68 | #define MDDI_INT_REV_OVERWRITE 0x0800 | ||
69 | #define MDDI_INT_DMA_FAILURE 0x1000 | ||
70 | #define MDDI_INT_LINK_ACTIVE 0x2000 | ||
71 | #define MDDI_INT_IN_HIBERNATION 0x4000 | ||
72 | #define MDDI_INT_PRI_LINK_LIST_DONE 0x8000 | ||
73 | #define MDDI_INT_SEC_LINK_LIST_DONE 0x10000 | ||
74 | #define MDDI_INT_NO_CMD_PKTS_PEND 0x20000 | ||
75 | #define MDDI_INT_RTD_FAILURE 0x40000 | ||
76 | #define MDDI_INT_REV_PKT_RECEIVED 0x80000 | ||
77 | #define MDDI_INT_REV_PKTS_AVAIL 0x100000 | ||
78 | |||
79 | #define MDDI_INT_NEED_CLEAR ( \ | ||
80 | MDDI_INT_REV_DATA_AVAIL | \ | ||
81 | MDDI_INT_PRI_UNDERFLOW | \ | ||
82 | MDDI_INT_SEC_UNDERFLOW | \ | ||
83 | MDDI_INT_REV_OVERFLOW | \ | ||
84 | MDDI_INT_CRC_ERROR | \ | ||
85 | MDDI_INT_REV_PKT_RECEIVED) | ||
86 | |||
87 | |||
88 | #define MDDI_STAT_LINK_ACTIVE 0x0001 | ||
89 | #define MDDI_STAT_NEW_REV_PTR 0x0002 | ||
90 | #define MDDI_STAT_NEW_PRI_PTR 0x0004 | ||
91 | #define MDDI_STAT_NEW_SEC_PTR 0x0008 | ||
92 | #define MDDI_STAT_IN_HIBERNATION 0x0010 | ||
93 | #define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020 | ||
94 | #define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040 | ||
95 | #define MDDI_STAT_PENDING_TIMING_PKT 0x0080 | ||
96 | #define MDDI_STAT_PENDING_REV_ENCAP 0x0100 | ||
97 | #define MDDI_STAT_PENDING_POWERDOWN 0x0200 | ||
98 | #define MDDI_STAT_RTD_MEAS_FAIL 0x0800 | ||
99 | #define MDDI_STAT_CLIENT_WAKEUP_REQ 0x1000 | ||
100 | |||
101 | |||
102 | #define MDDI_CMD_POWERDOWN 0x0100 | ||
103 | #define MDDI_CMD_POWERUP 0x0200 | ||
104 | #define MDDI_CMD_HIBERNATE 0x0300 | ||
105 | #define MDDI_CMD_RESET 0x0400 | ||
106 | #define MDDI_CMD_DISP_IGNORE 0x0501 | ||
107 | #define MDDI_CMD_DISP_LISTEN 0x0500 | ||
108 | #define MDDI_CMD_SEND_REV_ENCAP 0x0600 | ||
109 | #define MDDI_CMD_GET_CLIENT_CAP 0x0601 | ||
110 | #define MDDI_CMD_GET_CLIENT_STATUS 0x0602 | ||
111 | #define MDDI_CMD_SEND_RTD 0x0700 | ||
112 | #define MDDI_CMD_LINK_ACTIVE 0x0900 | ||
113 | #define MDDI_CMD_PERIODIC_REV_ENCAP 0x0A00 | ||
114 | #define MDDI_CMD_FORCE_NEW_REV_PTR 0x0C00 | ||
115 | |||
116 | |||
117 | |||
118 | #define MDDI_VIDEO_REV_PKT_SIZE 0x40 | ||
119 | #define MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE 0x60 | ||
120 | #define MDDI_MAX_REV_PKT_SIZE 0x60 | ||
121 | |||
122 | /* #define MDDI_REV_BUFFER_SIZE 128 */ | ||
123 | #define MDDI_REV_BUFFER_SIZE (MDDI_MAX_REV_PKT_SIZE * 4) | ||
124 | |||
125 | /* MDP sends 256 pixel packets, so lower value hibernates more without | ||
126 | * significantly increasing latency of waiting for next subframe */ | ||
127 | #define MDDI_HOST_BYTES_PER_SUBFRAME 0x3C00 | ||
128 | #define MDDI_HOST_TA2_LEN 0x000c | ||
129 | #define MDDI_HOST_REV_RATE_DIV 0x0002 | ||
130 | |||
131 | |||
132 | struct __attribute__((packed)) mddi_rev_packet { | ||
133 | uint16_t length; | ||
134 | uint16_t type; | ||
135 | uint16_t client_id; | ||
136 | }; | ||
137 | |||
138 | struct __attribute__((packed)) mddi_client_status { | ||
139 | uint16_t length; | ||
140 | uint16_t type; | ||
141 | uint16_t client_id; | ||
142 | uint16_t reverse_link_request; /* bytes needed in rev encap message */ | ||
143 | uint8_t crc_error_count; | ||
144 | uint8_t capability_change; | ||
145 | uint16_t graphics_busy_flags; | ||
146 | uint16_t crc16; | ||
147 | }; | ||
148 | |||
149 | struct __attribute__((packed)) mddi_client_caps { | ||
150 | uint16_t length; /* length, exclusive of this field */ | ||
151 | uint16_t type; /* 66 */ | ||
152 | uint16_t client_id; | ||
153 | |||
154 | uint16_t Protocol_Version; | ||
155 | uint16_t Minimum_Protocol_Version; | ||
156 | uint16_t Data_Rate_Capability; | ||
157 | uint8_t Interface_Type_Capability; | ||
158 | uint8_t Number_of_Alt_Displays; | ||
159 | uint16_t PostCal_Data_Rate; | ||
160 | uint16_t Bitmap_Width; | ||
161 | uint16_t Bitmap_Height; | ||
162 | uint16_t Display_Window_Width; | ||
163 | uint16_t Display_Window_Height; | ||
164 | uint32_t Color_Map_Size; | ||
165 | uint16_t Color_Map_RGB_Width; | ||
166 | uint16_t RGB_Capability; | ||
167 | uint8_t Monochrome_Capability; | ||
168 | uint8_t Reserved_1; | ||
169 | uint16_t Y_Cb_Cr_Capability; | ||
170 | uint16_t Bayer_Capability; | ||
171 | uint16_t Alpha_Cursor_Image_Planes; | ||
172 | uint32_t Client_Feature_Capability_Indicators; | ||
173 | uint8_t Maximum_Video_Frame_Rate_Capability; | ||
174 | uint8_t Minimum_Video_Frame_Rate_Capability; | ||
175 | uint16_t Minimum_Sub_frame_Rate; | ||
176 | uint16_t Audio_Buffer_Depth; | ||
177 | uint16_t Audio_Channel_Capability; | ||
178 | uint16_t Audio_Sample_Rate_Capability; | ||
179 | uint8_t Audio_Sample_Resolution; | ||
180 | uint8_t Mic_Audio_Sample_Resolution; | ||
181 | uint16_t Mic_Sample_Rate_Capability; | ||
182 | uint8_t Keyboard_Data_Format; | ||
183 | uint8_t pointing_device_data_format; | ||
184 | uint16_t content_protection_type; | ||
185 | uint16_t Mfr_Name; | ||
186 | uint16_t Product_Code; | ||
187 | uint16_t Reserved_3; | ||
188 | uint32_t Serial_Number; | ||
189 | uint8_t Week_of_Manufacture; | ||
190 | uint8_t Year_of_Manufacture; | ||
191 | |||
192 | uint16_t crc16; | ||
193 | } mddi_client_capability_type; | ||
194 | |||
195 | |||
196 | struct __attribute__((packed)) mddi_video_stream { | ||
197 | uint16_t length; | ||
198 | uint16_t type; /* 16 */ | ||
199 | uint16_t client_id; /* 0 */ | ||
200 | |||
201 | uint16_t video_data_format_descriptor; | ||
202 | /* format of each pixel in the Pixel Data in the present stream in the | ||
203 | * present packet. | ||
204 | * If bits [15:13] = 000 monochrome | ||
205 | * If bits [15:13] = 001 color pixels (palette). | ||
206 | * If bits [15:13] = 010 color pixels in raw RGB | ||
207 | * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format | ||
208 | * If bits [15:13] = 100 Bayer pixels | ||
209 | */ | ||
210 | |||
211 | uint16_t pixel_data_attributes; | ||
212 | /* interpreted as follows: | ||
213 | * Bits [1:0] = 11 pixel data is displayed to both eyes | ||
214 | * Bits [1:0] = 10 pixel data is routed to the left eye only. | ||
215 | * Bits [1:0] = 01 pixel data is routed to the right eye only. | ||
216 | * Bits [1:0] = 00 pixel data is routed to the alternate display. | ||
217 | * Bit 2 is 0 Pixel Data is in the standard progressive format. | ||
218 | * Bit 2 is 1 Pixel Data is in interlace format. | ||
219 | * Bit 3 is 0 Pixel Data is in the standard progressive format. | ||
220 | * Bit 3 is 1 Pixel Data is in alternate pixel format. | ||
221 | * Bit 4 is 0 Pixel Data is to or from the display frame buffer. | ||
222 | * Bit 4 is 1 Pixel Data is to or from the camera. | ||
223 | * Bit 5 is 0 pixel data contains the next consecutive row of pixels. | ||
224 | * Bit 5 is 1 X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge, | ||
225 | * X Start, and Y Start parameters are not defined and | ||
226 | * shall be ignored by the client. | ||
227 | * Bits [7:6] = 01 Pixel data is written to the offline image buffer. | ||
228 | * Bits [7:6] = 00 Pixel data is written to the buffer to refresh display. | ||
229 | * Bits [7:6] = 11 Pixel data is written to all image buffers. | ||
230 | * Bits [7:6] = 10 Invalid. Reserved for future use. | ||
231 | * Bits 8 through 11 alternate display number. | ||
232 | * Bits 12 through 14 are reserved for future use and shall be set to zero. | ||
233 | * Bit 15 is 1 the row of pixels is the last row of pixels in a frame. | ||
234 | */ | ||
235 | |||
236 | uint16_t x_left_edge; | ||
237 | uint16_t y_top_edge; | ||
238 | /* X,Y coordinate of the top left edge of the screen window */ | ||
239 | |||
240 | uint16_t x_right_edge; | ||
241 | uint16_t y_bottom_edge; | ||
242 | /* X,Y coordinate of the bottom right edge of the window being | ||
243 | * updated. */ | ||
244 | |||
245 | uint16_t x_start; | ||
246 | uint16_t y_start; | ||
247 | /* (X Start, Y Start) is the first pixel in the Pixel Data field | ||
248 | * below. */ | ||
249 | |||
250 | uint16_t pixel_count; | ||
251 | /* number of pixels in the Pixel Data field below. */ | ||
252 | |||
253 | uint16_t parameter_CRC; | ||
254 | /* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */ | ||
255 | |||
256 | uint16_t reserved; | ||
257 | /* 16-bit variable to make structure align on 4 byte boundary */ | ||
258 | }; | ||
259 | |||
260 | #define TYPE_VIDEO_STREAM 16 | ||
261 | #define TYPE_CLIENT_CAPS 66 | ||
262 | #define TYPE_REGISTER_ACCESS 146 | ||
263 | #define TYPE_CLIENT_STATUS 70 | ||
264 | |||
265 | struct __attribute__((packed)) mddi_register_access { | ||
266 | uint16_t length; | ||
267 | uint16_t type; /* 146 */ | ||
268 | uint16_t client_id; | ||
269 | |||
270 | uint16_t read_write_info; | ||
271 | /* Bits 13:0 a 14-bit unsigned integer that specifies the number of | ||
272 | * 32-bit Register Data List items to be transferred in the | ||
273 | * Register Data List field. | ||
274 | * Bits[15:14] = 00 Write to register(s); | ||
275 | * Bits[15:14] = 10 Read from register(s); | ||
276 | * Bits[15:14] = 11 Response to a Read. | ||
277 | * Bits[15:14] = 01 this value is reserved for future use. */ | ||
278 | #define MDDI_WRITE (0 << 14) | ||
279 | #define MDDI_READ (2 << 14) | ||
280 | #define MDDI_READ_RESP (3 << 14) | ||
281 | |||
282 | uint32_t register_address; | ||
283 | /* the register address that is to be written to or read from. */ | ||
284 | |||
285 | uint16_t crc16; | ||
286 | |||
287 | uint32_t register_data_list; | ||
288 | /* list of 4-byte register data values for/from client registers */ | ||
289 | }; | ||
290 | |||
291 | struct __attribute__((packed)) mddi_llentry { | ||
292 | uint16_t flags; | ||
293 | uint16_t header_count; | ||
294 | uint16_t data_count; | ||
295 | dma_addr_t data; /* 32 bit */ | ||
296 | struct mddi_llentry *next; | ||
297 | uint16_t reserved; | ||
298 | union { | ||
299 | struct mddi_video_stream v; | ||
300 | struct mddi_register_access r; | ||
301 | uint32_t _[12]; | ||
302 | } u; | ||
303 | }; | ||
304 | |||
305 | #endif | ||
diff --git a/drivers/video/fbdev/msm/mdp.c b/drivers/video/fbdev/msm/mdp.c deleted file mode 100644 index 113c7876c855..000000000000 --- a/drivers/video/fbdev/msm/mdp.c +++ /dev/null | |||
@@ -1,520 +0,0 @@ | |||
1 | /* drivers/video/msm_fb/mdp.c | ||
2 | * | ||
3 | * MSM MDP Interface (used by framebuffer core) | ||
4 | * | ||
5 | * Copyright (C) 2007 QUALCOMM Incorporated | ||
6 | * Copyright (C) 2007 Google Incorporated | ||
7 | * | ||
8 | * This software is licensed under the terms of the GNU General Public | ||
9 | * License version 2, as published by the Free Software Foundation, and | ||
10 | * may be copied, distributed, and modified under those terms. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | */ | ||
17 | |||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/fb.h> | ||
20 | #include <linux/msm_mdp.h> | ||
21 | #include <linux/interrupt.h> | ||
22 | #include <linux/wait.h> | ||
23 | #include <linux/clk.h> | ||
24 | #include <linux/file.h> | ||
25 | #include <linux/major.h> | ||
26 | #include <linux/slab.h> | ||
27 | |||
28 | #include <linux/platform_data/video-msm_fb.h> | ||
29 | #include <linux/platform_device.h> | ||
30 | #include <linux/export.h> | ||
31 | |||
32 | #include "mdp_hw.h" | ||
33 | |||
34 | struct class *mdp_class; | ||
35 | |||
36 | #define MDP_CMD_DEBUG_ACCESS_BASE (0x10000) | ||
37 | |||
38 | static uint16_t mdp_default_ccs[] = { | ||
39 | 0x254, 0x000, 0x331, 0x254, 0xF38, 0xE61, 0x254, 0x409, 0x000, | ||
40 | 0x010, 0x080, 0x080 | ||
41 | }; | ||
42 | |||
43 | static DECLARE_WAIT_QUEUE_HEAD(mdp_dma2_waitqueue); | ||
44 | static DECLARE_WAIT_QUEUE_HEAD(mdp_ppp_waitqueue); | ||
45 | static struct msmfb_callback *dma_callback; | ||
46 | static struct clk *clk; | ||
47 | static unsigned int mdp_irq_mask; | ||
48 | static DEFINE_SPINLOCK(mdp_lock); | ||
49 | DEFINE_MUTEX(mdp_mutex); | ||
50 | |||
51 | static int enable_mdp_irq(struct mdp_info *mdp, uint32_t mask) | ||
52 | { | ||
53 | unsigned long irq_flags; | ||
54 | int ret = 0; | ||
55 | |||
56 | BUG_ON(!mask); | ||
57 | |||
58 | spin_lock_irqsave(&mdp_lock, irq_flags); | ||
59 | /* if the mask bits are already set return an error, this interrupt | ||
60 | * is already enabled */ | ||
61 | if (mdp_irq_mask & mask) { | ||
62 | printk(KERN_ERR "mdp irq already on already on %x %x\n", | ||
63 | mdp_irq_mask, mask); | ||
64 | ret = -1; | ||
65 | } | ||
66 | /* if the mdp irq is not already enabled enable it */ | ||
67 | if (!mdp_irq_mask) { | ||
68 | if (clk) | ||
69 | clk_enable(clk); | ||
70 | enable_irq(mdp->irq); | ||
71 | } | ||
72 | |||
73 | /* update the irq mask to reflect the fact that the interrupt is | ||
74 | * enabled */ | ||
75 | mdp_irq_mask |= mask; | ||
76 | spin_unlock_irqrestore(&mdp_lock, irq_flags); | ||
77 | return ret; | ||
78 | } | ||
79 | |||
80 | static int locked_disable_mdp_irq(struct mdp_info *mdp, uint32_t mask) | ||
81 | { | ||
82 | /* this interrupt is already disabled! */ | ||
83 | if (!(mdp_irq_mask & mask)) { | ||
84 | printk(KERN_ERR "mdp irq already off %x %x\n", | ||
85 | mdp_irq_mask, mask); | ||
86 | return -1; | ||
87 | } | ||
88 | /* update the irq mask to reflect the fact that the interrupt is | ||
89 | * disabled */ | ||
90 | mdp_irq_mask &= ~(mask); | ||
91 | /* if no one is waiting on the interrupt, disable it */ | ||
92 | if (!mdp_irq_mask) { | ||
93 | disable_irq_nosync(mdp->irq); | ||
94 | if (clk) | ||
95 | clk_disable(clk); | ||
96 | } | ||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | static int disable_mdp_irq(struct mdp_info *mdp, uint32_t mask) | ||
101 | { | ||
102 | unsigned long irq_flags; | ||
103 | int ret; | ||
104 | |||
105 | spin_lock_irqsave(&mdp_lock, irq_flags); | ||
106 | ret = locked_disable_mdp_irq(mdp, mask); | ||
107 | spin_unlock_irqrestore(&mdp_lock, irq_flags); | ||
108 | return ret; | ||
109 | } | ||
110 | |||
111 | static irqreturn_t mdp_isr(int irq, void *data) | ||
112 | { | ||
113 | uint32_t status; | ||
114 | unsigned long irq_flags; | ||
115 | struct mdp_info *mdp = data; | ||
116 | |||
117 | spin_lock_irqsave(&mdp_lock, irq_flags); | ||
118 | |||
119 | status = mdp_readl(mdp, MDP_INTR_STATUS); | ||
120 | mdp_writel(mdp, status, MDP_INTR_CLEAR); | ||
121 | |||
122 | status &= mdp_irq_mask; | ||
123 | if (status & DL0_DMA2_TERM_DONE) { | ||
124 | if (dma_callback) { | ||
125 | dma_callback->func(dma_callback); | ||
126 | dma_callback = NULL; | ||
127 | } | ||
128 | wake_up(&mdp_dma2_waitqueue); | ||
129 | } | ||
130 | |||
131 | if (status & DL0_ROI_DONE) | ||
132 | wake_up(&mdp_ppp_waitqueue); | ||
133 | |||
134 | if (status) | ||
135 | locked_disable_mdp_irq(mdp, status); | ||
136 | |||
137 | spin_unlock_irqrestore(&mdp_lock, irq_flags); | ||
138 | return IRQ_HANDLED; | ||
139 | } | ||
140 | |||
141 | static uint32_t mdp_check_mask(uint32_t mask) | ||
142 | { | ||
143 | uint32_t ret; | ||
144 | unsigned long irq_flags; | ||
145 | |||
146 | spin_lock_irqsave(&mdp_lock, irq_flags); | ||
147 | ret = mdp_irq_mask & mask; | ||
148 | spin_unlock_irqrestore(&mdp_lock, irq_flags); | ||
149 | return ret; | ||
150 | } | ||
151 | |||
152 | static int mdp_wait(struct mdp_info *mdp, uint32_t mask, wait_queue_head_t *wq) | ||
153 | { | ||
154 | int ret = 0; | ||
155 | unsigned long irq_flags; | ||
156 | |||
157 | wait_event_timeout(*wq, !mdp_check_mask(mask), HZ); | ||
158 | |||
159 | spin_lock_irqsave(&mdp_lock, irq_flags); | ||
160 | if (mdp_irq_mask & mask) { | ||
161 | locked_disable_mdp_irq(mdp, mask); | ||
162 | printk(KERN_WARNING "timeout waiting for mdp to complete %x\n", | ||
163 | mask); | ||
164 | ret = -ETIMEDOUT; | ||
165 | } | ||
166 | spin_unlock_irqrestore(&mdp_lock, irq_flags); | ||
167 | |||
168 | return ret; | ||
169 | } | ||
170 | |||
171 | void mdp_dma_wait(struct mdp_device *mdp_dev) | ||
172 | { | ||
173 | #define MDP_MAX_TIMEOUTS 20 | ||
174 | static int timeout_count; | ||
175 | struct mdp_info *mdp = container_of(mdp_dev, struct mdp_info, mdp_dev); | ||
176 | |||
177 | if (mdp_wait(mdp, DL0_DMA2_TERM_DONE, &mdp_dma2_waitqueue) == -ETIMEDOUT) | ||
178 | timeout_count++; | ||
179 | else | ||
180 | timeout_count = 0; | ||
181 | |||
182 | if (timeout_count > MDP_MAX_TIMEOUTS) { | ||
183 | printk(KERN_ERR "mdp: dma failed %d times, somethings wrong!\n", | ||
184 | MDP_MAX_TIMEOUTS); | ||
185 | BUG(); | ||
186 | } | ||
187 | } | ||
188 | |||
189 | static int mdp_ppp_wait(struct mdp_info *mdp) | ||
190 | { | ||
191 | return mdp_wait(mdp, DL0_ROI_DONE, &mdp_ppp_waitqueue); | ||
192 | } | ||
193 | |||
194 | void mdp_dma_to_mddi(struct mdp_info *mdp, uint32_t addr, uint32_t stride, | ||
195 | uint32_t width, uint32_t height, uint32_t x, uint32_t y, | ||
196 | struct msmfb_callback *callback) | ||
197 | { | ||
198 | uint32_t dma2_cfg; | ||
199 | uint16_t ld_param = 0; /* 0=PRIM, 1=SECD, 2=EXT */ | ||
200 | |||
201 | if (enable_mdp_irq(mdp, DL0_DMA2_TERM_DONE)) { | ||
202 | printk(KERN_ERR "mdp_dma_to_mddi: busy\n"); | ||
203 | return; | ||
204 | } | ||
205 | |||
206 | dma_callback = callback; | ||
207 | |||
208 | dma2_cfg = DMA_PACK_TIGHT | | ||
209 | DMA_PACK_ALIGN_LSB | | ||
210 | DMA_PACK_PATTERN_RGB | | ||
211 | DMA_OUT_SEL_AHB | | ||
212 | DMA_IBUF_NONCONTIGUOUS; | ||
213 | |||
214 | dma2_cfg |= DMA_IBUF_FORMAT_RGB565; | ||
215 | |||
216 | dma2_cfg |= DMA_OUT_SEL_MDDI; | ||
217 | |||
218 | dma2_cfg |= DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY; | ||
219 | |||
220 | dma2_cfg |= DMA_DITHER_EN; | ||
221 | |||
222 | /* setup size, address, and stride */ | ||
223 | mdp_writel(mdp, (height << 16) | (width), | ||
224 | MDP_CMD_DEBUG_ACCESS_BASE + 0x0184); | ||
225 | mdp_writel(mdp, addr, MDP_CMD_DEBUG_ACCESS_BASE + 0x0188); | ||
226 | mdp_writel(mdp, stride, MDP_CMD_DEBUG_ACCESS_BASE + 0x018C); | ||
227 | |||
228 | /* 666 18BPP */ | ||
229 | dma2_cfg |= DMA_DSTC0G_6BITS | DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS; | ||
230 | |||
231 | /* set y & x offset and MDDI transaction parameters */ | ||
232 | mdp_writel(mdp, (y << 16) | (x), MDP_CMD_DEBUG_ACCESS_BASE + 0x0194); | ||
233 | mdp_writel(mdp, ld_param, MDP_CMD_DEBUG_ACCESS_BASE + 0x01a0); | ||
234 | mdp_writel(mdp, (MDDI_VDO_PACKET_DESC << 16) | MDDI_VDO_PACKET_PRIM, | ||
235 | MDP_CMD_DEBUG_ACCESS_BASE + 0x01a4); | ||
236 | |||
237 | mdp_writel(mdp, dma2_cfg, MDP_CMD_DEBUG_ACCESS_BASE + 0x0180); | ||
238 | |||
239 | /* start DMA2 */ | ||
240 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0044); | ||
241 | } | ||
242 | |||
243 | void mdp_dma(struct mdp_device *mdp_dev, uint32_t addr, uint32_t stride, | ||
244 | uint32_t width, uint32_t height, uint32_t x, uint32_t y, | ||
245 | struct msmfb_callback *callback, int interface) | ||
246 | { | ||
247 | struct mdp_info *mdp = container_of(mdp_dev, struct mdp_info, mdp_dev); | ||
248 | |||
249 | if (interface == MSM_MDDI_PMDH_INTERFACE) { | ||
250 | mdp_dma_to_mddi(mdp, addr, stride, width, height, x, y, | ||
251 | callback); | ||
252 | } | ||
253 | } | ||
254 | |||
255 | int get_img(struct mdp_img *img, struct fb_info *info, | ||
256 | unsigned long *start, unsigned long *len, | ||
257 | struct file **filep) | ||
258 | { | ||
259 | int ret = 0; | ||
260 | struct fd f = fdget(img->memory_id); | ||
261 | if (f.file == NULL) | ||
262 | return -1; | ||
263 | |||
264 | if (MAJOR(file_inode(f.file)->i_rdev) == FB_MAJOR) { | ||
265 | *start = info->fix.smem_start; | ||
266 | *len = info->fix.smem_len; | ||
267 | } else | ||
268 | ret = -1; | ||
269 | fdput(f); | ||
270 | |||
271 | return ret; | ||
272 | } | ||
273 | |||
274 | void put_img(struct file *src_file, struct file *dst_file) | ||
275 | { | ||
276 | } | ||
277 | |||
278 | int mdp_blit(struct mdp_device *mdp_dev, struct fb_info *fb, | ||
279 | struct mdp_blit_req *req) | ||
280 | { | ||
281 | int ret; | ||
282 | unsigned long src_start = 0, src_len = 0, dst_start = 0, dst_len = 0; | ||
283 | struct mdp_info *mdp = container_of(mdp_dev, struct mdp_info, mdp_dev); | ||
284 | struct file *src_file = 0, *dst_file = 0; | ||
285 | |||
286 | /* WORKAROUND FOR HARDWARE BUG IN BG TILE FETCH */ | ||
287 | if (unlikely(req->src_rect.h == 0 || | ||
288 | req->src_rect.w == 0)) { | ||
289 | printk(KERN_ERR "mpd_ppp: src img of zero size!\n"); | ||
290 | return -EINVAL; | ||
291 | } | ||
292 | if (unlikely(req->dst_rect.h == 0 || | ||
293 | req->dst_rect.w == 0)) | ||
294 | return -EINVAL; | ||
295 | |||
296 | /* do this first so that if this fails, the caller can always | ||
297 | * safely call put_img */ | ||
298 | if (unlikely(get_img(&req->src, fb, &src_start, &src_len, &src_file))) { | ||
299 | printk(KERN_ERR "mpd_ppp: could not retrieve src image from " | ||
300 | "memory\n"); | ||
301 | return -EINVAL; | ||
302 | } | ||
303 | |||
304 | if (unlikely(get_img(&req->dst, fb, &dst_start, &dst_len, &dst_file))) { | ||
305 | printk(KERN_ERR "mpd_ppp: could not retrieve dst image from " | ||
306 | "memory\n"); | ||
307 | return -EINVAL; | ||
308 | } | ||
309 | mutex_lock(&mdp_mutex); | ||
310 | |||
311 | /* transp_masking unimplemented */ | ||
312 | req->transp_mask = MDP_TRANSP_NOP; | ||
313 | if (unlikely((req->transp_mask != MDP_TRANSP_NOP || | ||
314 | req->alpha != MDP_ALPHA_NOP || | ||
315 | HAS_ALPHA(req->src.format)) && | ||
316 | (req->flags & MDP_ROT_90 && | ||
317 | req->dst_rect.w <= 16 && req->dst_rect.h >= 16))) { | ||
318 | int i; | ||
319 | unsigned int tiles = req->dst_rect.h / 16; | ||
320 | unsigned int remainder = req->dst_rect.h % 16; | ||
321 | req->src_rect.w = 16*req->src_rect.w / req->dst_rect.h; | ||
322 | req->dst_rect.h = 16; | ||
323 | for (i = 0; i < tiles; i++) { | ||
324 | enable_mdp_irq(mdp, DL0_ROI_DONE); | ||
325 | ret = mdp_ppp_blit(mdp, req, src_file, src_start, | ||
326 | src_len, dst_file, dst_start, | ||
327 | dst_len); | ||
328 | if (ret) | ||
329 | goto err_bad_blit; | ||
330 | ret = mdp_ppp_wait(mdp); | ||
331 | if (ret) | ||
332 | goto err_wait_failed; | ||
333 | req->dst_rect.y += 16; | ||
334 | req->src_rect.x += req->src_rect.w; | ||
335 | } | ||
336 | if (!remainder) | ||
337 | goto end; | ||
338 | req->src_rect.w = remainder*req->src_rect.w / req->dst_rect.h; | ||
339 | req->dst_rect.h = remainder; | ||
340 | } | ||
341 | enable_mdp_irq(mdp, DL0_ROI_DONE); | ||
342 | ret = mdp_ppp_blit(mdp, req, src_file, src_start, src_len, dst_file, | ||
343 | dst_start, | ||
344 | dst_len); | ||
345 | if (ret) | ||
346 | goto err_bad_blit; | ||
347 | ret = mdp_ppp_wait(mdp); | ||
348 | if (ret) | ||
349 | goto err_wait_failed; | ||
350 | end: | ||
351 | put_img(src_file, dst_file); | ||
352 | mutex_unlock(&mdp_mutex); | ||
353 | return 0; | ||
354 | err_bad_blit: | ||
355 | disable_mdp_irq(mdp, DL0_ROI_DONE); | ||
356 | err_wait_failed: | ||
357 | put_img(src_file, dst_file); | ||
358 | mutex_unlock(&mdp_mutex); | ||
359 | return ret; | ||
360 | } | ||
361 | |||
362 | void mdp_set_grp_disp(struct mdp_device *mdp_dev, unsigned disp_id) | ||
363 | { | ||
364 | struct mdp_info *mdp = container_of(mdp_dev, struct mdp_info, mdp_dev); | ||
365 | |||
366 | disp_id &= 0xf; | ||
367 | mdp_writel(mdp, disp_id, MDP_FULL_BYPASS_WORD43); | ||
368 | } | ||
369 | |||
370 | int register_mdp_client(struct class_interface *cint) | ||
371 | { | ||
372 | if (!mdp_class) { | ||
373 | pr_err("mdp: no mdp_class when registering mdp client\n"); | ||
374 | return -ENODEV; | ||
375 | } | ||
376 | cint->class = mdp_class; | ||
377 | return class_interface_register(cint); | ||
378 | } | ||
379 | |||
380 | #include "mdp_csc_table.h" | ||
381 | #include "mdp_scale_tables.h" | ||
382 | |||
383 | int mdp_probe(struct platform_device *pdev) | ||
384 | { | ||
385 | struct resource *resource; | ||
386 | int ret; | ||
387 | int n; | ||
388 | struct mdp_info *mdp; | ||
389 | |||
390 | resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
391 | if (!resource) { | ||
392 | pr_err("mdp: can not get mdp mem resource!\n"); | ||
393 | return -ENOMEM; | ||
394 | } | ||
395 | |||
396 | mdp = kzalloc(sizeof(struct mdp_info), GFP_KERNEL); | ||
397 | if (!mdp) | ||
398 | return -ENOMEM; | ||
399 | |||
400 | mdp->irq = platform_get_irq(pdev, 0); | ||
401 | if (mdp->irq < 0) { | ||
402 | pr_err("mdp: can not get mdp irq\n"); | ||
403 | ret = mdp->irq; | ||
404 | goto error_get_irq; | ||
405 | } | ||
406 | |||
407 | mdp->base = ioremap(resource->start, resource_size(resource)); | ||
408 | if (mdp->base == 0) { | ||
409 | printk(KERN_ERR "msmfb: cannot allocate mdp regs!\n"); | ||
410 | ret = -ENOMEM; | ||
411 | goto error_ioremap; | ||
412 | } | ||
413 | |||
414 | mdp->mdp_dev.dma = mdp_dma; | ||
415 | mdp->mdp_dev.dma_wait = mdp_dma_wait; | ||
416 | mdp->mdp_dev.blit = mdp_blit; | ||
417 | mdp->mdp_dev.set_grp_disp = mdp_set_grp_disp; | ||
418 | |||
419 | clk = clk_get(&pdev->dev, "mdp_clk"); | ||
420 | if (IS_ERR(clk)) { | ||
421 | printk(KERN_INFO "mdp: failed to get mdp clk"); | ||
422 | ret = PTR_ERR(clk); | ||
423 | goto error_get_clk; | ||
424 | } | ||
425 | |||
426 | ret = request_irq(mdp->irq, mdp_isr, 0, "msm_mdp", mdp); | ||
427 | if (ret) | ||
428 | goto error_request_irq; | ||
429 | disable_irq(mdp->irq); | ||
430 | mdp_irq_mask = 0; | ||
431 | |||
432 | /* debug interface write access */ | ||
433 | mdp_writel(mdp, 1, 0x60); | ||
434 | |||
435 | mdp_writel(mdp, MDP_ANY_INTR_MASK, MDP_INTR_ENABLE); | ||
436 | mdp_writel(mdp, 1, MDP_EBI2_PORTMAP_MODE); | ||
437 | |||
438 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01f8); | ||
439 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01fc); | ||
440 | |||
441 | for (n = 0; n < ARRAY_SIZE(csc_table); n++) | ||
442 | mdp_writel(mdp, csc_table[n].val, csc_table[n].reg); | ||
443 | |||
444 | /* clear up unused fg/main registers */ | ||
445 | /* comp.plane 2&3 ystride */ | ||
446 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0120); | ||
447 | |||
448 | /* unpacked pattern */ | ||
449 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x012c); | ||
450 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0130); | ||
451 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0134); | ||
452 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0158); | ||
453 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x015c); | ||
454 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0160); | ||
455 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0170); | ||
456 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0174); | ||
457 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x017c); | ||
458 | |||
459 | /* comp.plane 2 & 3 */ | ||
460 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0114); | ||
461 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0118); | ||
462 | |||
463 | /* clear unused bg registers */ | ||
464 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01c8); | ||
465 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01d0); | ||
466 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01dc); | ||
467 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01e0); | ||
468 | mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01e4); | ||
469 | |||
470 | for (n = 0; n < ARRAY_SIZE(mdp_upscale_table); n++) | ||
471 | mdp_writel(mdp, mdp_upscale_table[n].val, | ||
472 | mdp_upscale_table[n].reg); | ||
473 | |||
474 | for (n = 0; n < 9; n++) | ||
475 | mdp_writel(mdp, mdp_default_ccs[n], 0x40440 + 4 * n); | ||
476 | mdp_writel(mdp, mdp_default_ccs[9], 0x40500 + 4 * 0); | ||
477 | mdp_writel(mdp, mdp_default_ccs[10], 0x40500 + 4 * 0); | ||
478 | mdp_writel(mdp, mdp_default_ccs[11], 0x40500 + 4 * 0); | ||
479 | |||
480 | /* register mdp device */ | ||
481 | mdp->mdp_dev.dev.parent = &pdev->dev; | ||
482 | mdp->mdp_dev.dev.class = mdp_class; | ||
483 | dev_set_name(&mdp->mdp_dev.dev, "mdp%d", pdev->id); | ||
484 | |||
485 | /* if you can remove the platform device you'd have to implement | ||
486 | * this: | ||
487 | mdp_dev.release = mdp_class; */ | ||
488 | |||
489 | ret = device_register(&mdp->mdp_dev.dev); | ||
490 | if (ret) | ||
491 | goto error_device_register; | ||
492 | return 0; | ||
493 | |||
494 | error_device_register: | ||
495 | free_irq(mdp->irq, mdp); | ||
496 | error_request_irq: | ||
497 | error_get_clk: | ||
498 | iounmap(mdp->base); | ||
499 | error_get_irq: | ||
500 | error_ioremap: | ||
501 | kfree(mdp); | ||
502 | return ret; | ||
503 | } | ||
504 | |||
505 | static struct platform_driver msm_mdp_driver = { | ||
506 | .probe = mdp_probe, | ||
507 | .driver = {.name = "msm_mdp"}, | ||
508 | }; | ||
509 | |||
510 | static int __init mdp_init(void) | ||
511 | { | ||
512 | mdp_class = class_create(THIS_MODULE, "msm_mdp"); | ||
513 | if (IS_ERR(mdp_class)) { | ||
514 | printk(KERN_ERR "Error creating mdp class\n"); | ||
515 | return PTR_ERR(mdp_class); | ||
516 | } | ||
517 | return platform_driver_register(&msm_mdp_driver); | ||
518 | } | ||
519 | |||
520 | subsys_initcall(mdp_init); | ||
diff --git a/drivers/video/fbdev/msm/mdp_csc_table.h b/drivers/video/fbdev/msm/mdp_csc_table.h deleted file mode 100644 index d1cde30ead52..000000000000 --- a/drivers/video/fbdev/msm/mdp_csc_table.h +++ /dev/null | |||
@@ -1,582 +0,0 @@ | |||
1 | /* drivers/video/msm_fb/mdp_csc_table.h | ||
2 | * | ||
3 | * Copyright (C) 2007 QUALCOMM Incorporated | ||
4 | * Copyright (C) 2007 Google Incorporated | ||
5 | * | ||
6 | * This software is licensed under the terms of the GNU General Public | ||
7 | * License version 2, as published by the Free Software Foundation, and | ||
8 | * may be copied, distributed, and modified under those terms. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | static struct { | ||
17 | uint32_t reg; | ||
18 | uint32_t val; | ||
19 | } csc_table[] = { | ||
20 | { 0x40400, 0x83 }, | ||
21 | { 0x40404, 0x102 }, | ||
22 | { 0x40408, 0x32 }, | ||
23 | { 0x4040c, 0xffffffb5 }, | ||
24 | { 0x40410, 0xffffff6c }, | ||
25 | { 0x40414, 0xe1 }, | ||
26 | { 0x40418, 0xe1 }, | ||
27 | { 0x4041c, 0xffffff45 }, | ||
28 | { 0x40420, 0xffffffdc }, | ||
29 | { 0x40440, 0x254 }, | ||
30 | { 0x40444, 0x0 }, | ||
31 | { 0x40448, 0x331 }, | ||
32 | { 0x4044c, 0x254 }, | ||
33 | { 0x40450, 0xffffff38 }, | ||
34 | { 0x40454, 0xfffffe61 }, | ||
35 | { 0x40458, 0x254 }, | ||
36 | { 0x4045c, 0x409 }, | ||
37 | { 0x40460, 0x0 }, | ||
38 | { 0x40480, 0x5d }, | ||
39 | { 0x40484, 0x13a }, | ||
40 | { 0x40488, 0x20 }, | ||
41 | { 0x4048c, 0xffffffcd }, | ||
42 | { 0x40490, 0xffffff54 }, | ||
43 | { 0x40494, 0xe1 }, | ||
44 | { 0x40498, 0xe1 }, | ||
45 | { 0x4049c, 0xffffff35 }, | ||
46 | { 0x404a0, 0xffffffec }, | ||
47 | { 0x404c0, 0x254 }, | ||
48 | { 0x404c4, 0x0 }, | ||
49 | { 0x404c8, 0x396 }, | ||
50 | { 0x404cc, 0x254 }, | ||
51 | { 0x404d0, 0xffffff94 }, | ||
52 | { 0x404d4, 0xfffffef0 }, | ||
53 | { 0x404d8, 0x254 }, | ||
54 | { 0x404dc, 0x43a }, | ||
55 | { 0x404e0, 0x0 }, | ||
56 | { 0x40500, 0x10 }, | ||
57 | { 0x40504, 0x80 }, | ||
58 | { 0x40508, 0x80 }, | ||
59 | { 0x40540, 0x10 }, | ||
60 | { 0x40544, 0x80 }, | ||
61 | { 0x40548, 0x80 }, | ||
62 | { 0x40580, 0x10 }, | ||
63 | { 0x40584, 0xeb }, | ||
64 | { 0x40588, 0x10 }, | ||
65 | { 0x4058c, 0xf0 }, | ||
66 | { 0x405c0, 0x10 }, | ||
67 | { 0x405c4, 0xeb }, | ||
68 | { 0x405c8, 0x10 }, | ||
69 | { 0x405cc, 0xf0 }, | ||
70 | { 0x40800, 0x0 }, | ||
71 | { 0x40804, 0x151515 }, | ||
72 | { 0x40808, 0x1d1d1d }, | ||
73 | { 0x4080c, 0x232323 }, | ||
74 | { 0x40810, 0x272727 }, | ||
75 | { 0x40814, 0x2b2b2b }, | ||
76 | { 0x40818, 0x2f2f2f }, | ||
77 | { 0x4081c, 0x333333 }, | ||
78 | { 0x40820, 0x363636 }, | ||
79 | { 0x40824, 0x393939 }, | ||
80 | { 0x40828, 0x3b3b3b }, | ||
81 | { 0x4082c, 0x3e3e3e }, | ||
82 | { 0x40830, 0x404040 }, | ||
83 | { 0x40834, 0x434343 }, | ||
84 | { 0x40838, 0x454545 }, | ||
85 | { 0x4083c, 0x474747 }, | ||
86 | { 0x40840, 0x494949 }, | ||
87 | { 0x40844, 0x4b4b4b }, | ||
88 | { 0x40848, 0x4d4d4d }, | ||
89 | { 0x4084c, 0x4f4f4f }, | ||
90 | { 0x40850, 0x515151 }, | ||
91 | { 0x40854, 0x535353 }, | ||
92 | { 0x40858, 0x555555 }, | ||
93 | { 0x4085c, 0x565656 }, | ||
94 | { 0x40860, 0x585858 }, | ||
95 | { 0x40864, 0x5a5a5a }, | ||
96 | { 0x40868, 0x5b5b5b }, | ||
97 | { 0x4086c, 0x5d5d5d }, | ||
98 | { 0x40870, 0x5e5e5e }, | ||
99 | { 0x40874, 0x606060 }, | ||
100 | { 0x40878, 0x616161 }, | ||
101 | { 0x4087c, 0x636363 }, | ||
102 | { 0x40880, 0x646464 }, | ||
103 | { 0x40884, 0x666666 }, | ||
104 | { 0x40888, 0x676767 }, | ||
105 | { 0x4088c, 0x686868 }, | ||
106 | { 0x40890, 0x6a6a6a }, | ||
107 | { 0x40894, 0x6b6b6b }, | ||
108 | { 0x40898, 0x6c6c6c }, | ||
109 | { 0x4089c, 0x6e6e6e }, | ||
110 | { 0x408a0, 0x6f6f6f }, | ||
111 | { 0x408a4, 0x707070 }, | ||
112 | { 0x408a8, 0x717171 }, | ||
113 | { 0x408ac, 0x727272 }, | ||
114 | { 0x408b0, 0x747474 }, | ||
115 | { 0x408b4, 0x757575 }, | ||
116 | { 0x408b8, 0x767676 }, | ||
117 | { 0x408bc, 0x777777 }, | ||
118 | { 0x408c0, 0x787878 }, | ||
119 | { 0x408c4, 0x797979 }, | ||
120 | { 0x408c8, 0x7a7a7a }, | ||
121 | { 0x408cc, 0x7c7c7c }, | ||
122 | { 0x408d0, 0x7d7d7d }, | ||
123 | { 0x408d4, 0x7e7e7e }, | ||
124 | { 0x408d8, 0x7f7f7f }, | ||
125 | { 0x408dc, 0x808080 }, | ||
126 | { 0x408e0, 0x818181 }, | ||
127 | { 0x408e4, 0x828282 }, | ||
128 | { 0x408e8, 0x838383 }, | ||
129 | { 0x408ec, 0x848484 }, | ||
130 | { 0x408f0, 0x858585 }, | ||
131 | { 0x408f4, 0x868686 }, | ||
132 | { 0x408f8, 0x878787 }, | ||
133 | { 0x408fc, 0x888888 }, | ||
134 | { 0x40900, 0x898989 }, | ||
135 | { 0x40904, 0x8a8a8a }, | ||
136 | { 0x40908, 0x8b8b8b }, | ||
137 | { 0x4090c, 0x8c8c8c }, | ||
138 | { 0x40910, 0x8d8d8d }, | ||
139 | { 0x40914, 0x8e8e8e }, | ||
140 | { 0x40918, 0x8f8f8f }, | ||
141 | { 0x4091c, 0x8f8f8f }, | ||
142 | { 0x40920, 0x909090 }, | ||
143 | { 0x40924, 0x919191 }, | ||
144 | { 0x40928, 0x929292 }, | ||
145 | { 0x4092c, 0x939393 }, | ||
146 | { 0x40930, 0x949494 }, | ||
147 | { 0x40934, 0x959595 }, | ||
148 | { 0x40938, 0x969696 }, | ||
149 | { 0x4093c, 0x969696 }, | ||
150 | { 0x40940, 0x979797 }, | ||
151 | { 0x40944, 0x989898 }, | ||
152 | { 0x40948, 0x999999 }, | ||
153 | { 0x4094c, 0x9a9a9a }, | ||
154 | { 0x40950, 0x9b9b9b }, | ||
155 | { 0x40954, 0x9c9c9c }, | ||
156 | { 0x40958, 0x9c9c9c }, | ||
157 | { 0x4095c, 0x9d9d9d }, | ||
158 | { 0x40960, 0x9e9e9e }, | ||
159 | { 0x40964, 0x9f9f9f }, | ||
160 | { 0x40968, 0xa0a0a0 }, | ||
161 | { 0x4096c, 0xa0a0a0 }, | ||
162 | { 0x40970, 0xa1a1a1 }, | ||
163 | { 0x40974, 0xa2a2a2 }, | ||
164 | { 0x40978, 0xa3a3a3 }, | ||
165 | { 0x4097c, 0xa4a4a4 }, | ||
166 | { 0x40980, 0xa4a4a4 }, | ||
167 | { 0x40984, 0xa5a5a5 }, | ||
168 | { 0x40988, 0xa6a6a6 }, | ||
169 | { 0x4098c, 0xa7a7a7 }, | ||
170 | { 0x40990, 0xa7a7a7 }, | ||
171 | { 0x40994, 0xa8a8a8 }, | ||
172 | { 0x40998, 0xa9a9a9 }, | ||
173 | { 0x4099c, 0xaaaaaa }, | ||
174 | { 0x409a0, 0xaaaaaa }, | ||
175 | { 0x409a4, 0xababab }, | ||
176 | { 0x409a8, 0xacacac }, | ||
177 | { 0x409ac, 0xadadad }, | ||
178 | { 0x409b0, 0xadadad }, | ||
179 | { 0x409b4, 0xaeaeae }, | ||
180 | { 0x409b8, 0xafafaf }, | ||
181 | { 0x409bc, 0xafafaf }, | ||
182 | { 0x409c0, 0xb0b0b0 }, | ||
183 | { 0x409c4, 0xb1b1b1 }, | ||
184 | { 0x409c8, 0xb2b2b2 }, | ||
185 | { 0x409cc, 0xb2b2b2 }, | ||
186 | { 0x409d0, 0xb3b3b3 }, | ||
187 | { 0x409d4, 0xb4b4b4 }, | ||
188 | { 0x409d8, 0xb4b4b4 }, | ||
189 | { 0x409dc, 0xb5b5b5 }, | ||
190 | { 0x409e0, 0xb6b6b6 }, | ||
191 | { 0x409e4, 0xb6b6b6 }, | ||
192 | { 0x409e8, 0xb7b7b7 }, | ||
193 | { 0x409ec, 0xb8b8b8 }, | ||
194 | { 0x409f0, 0xb8b8b8 }, | ||
195 | { 0x409f4, 0xb9b9b9 }, | ||
196 | { 0x409f8, 0xbababa }, | ||
197 | { 0x409fc, 0xbababa }, | ||
198 | { 0x40a00, 0xbbbbbb }, | ||
199 | { 0x40a04, 0xbcbcbc }, | ||
200 | { 0x40a08, 0xbcbcbc }, | ||
201 | { 0x40a0c, 0xbdbdbd }, | ||
202 | { 0x40a10, 0xbebebe }, | ||
203 | { 0x40a14, 0xbebebe }, | ||
204 | { 0x40a18, 0xbfbfbf }, | ||
205 | { 0x40a1c, 0xc0c0c0 }, | ||
206 | { 0x40a20, 0xc0c0c0 }, | ||
207 | { 0x40a24, 0xc1c1c1 }, | ||
208 | { 0x40a28, 0xc1c1c1 }, | ||
209 | { 0x40a2c, 0xc2c2c2 }, | ||
210 | { 0x40a30, 0xc3c3c3 }, | ||
211 | { 0x40a34, 0xc3c3c3 }, | ||
212 | { 0x40a38, 0xc4c4c4 }, | ||
213 | { 0x40a3c, 0xc5c5c5 }, | ||
214 | { 0x40a40, 0xc5c5c5 }, | ||
215 | { 0x40a44, 0xc6c6c6 }, | ||
216 | { 0x40a48, 0xc6c6c6 }, | ||
217 | { 0x40a4c, 0xc7c7c7 }, | ||
218 | { 0x40a50, 0xc8c8c8 }, | ||
219 | { 0x40a54, 0xc8c8c8 }, | ||
220 | { 0x40a58, 0xc9c9c9 }, | ||
221 | { 0x40a5c, 0xc9c9c9 }, | ||
222 | { 0x40a60, 0xcacaca }, | ||
223 | { 0x40a64, 0xcbcbcb }, | ||
224 | { 0x40a68, 0xcbcbcb }, | ||
225 | { 0x40a6c, 0xcccccc }, | ||
226 | { 0x40a70, 0xcccccc }, | ||
227 | { 0x40a74, 0xcdcdcd }, | ||
228 | { 0x40a78, 0xcecece }, | ||
229 | { 0x40a7c, 0xcecece }, | ||
230 | { 0x40a80, 0xcfcfcf }, | ||
231 | { 0x40a84, 0xcfcfcf }, | ||
232 | { 0x40a88, 0xd0d0d0 }, | ||
233 | { 0x40a8c, 0xd0d0d0 }, | ||
234 | { 0x40a90, 0xd1d1d1 }, | ||
235 | { 0x40a94, 0xd2d2d2 }, | ||
236 | { 0x40a98, 0xd2d2d2 }, | ||
237 | { 0x40a9c, 0xd3d3d3 }, | ||
238 | { 0x40aa0, 0xd3d3d3 }, | ||
239 | { 0x40aa4, 0xd4d4d4 }, | ||
240 | { 0x40aa8, 0xd4d4d4 }, | ||
241 | { 0x40aac, 0xd5d5d5 }, | ||
242 | { 0x40ab0, 0xd6d6d6 }, | ||
243 | { 0x40ab4, 0xd6d6d6 }, | ||
244 | { 0x40ab8, 0xd7d7d7 }, | ||
245 | { 0x40abc, 0xd7d7d7 }, | ||
246 | { 0x40ac0, 0xd8d8d8 }, | ||
247 | { 0x40ac4, 0xd8d8d8 }, | ||
248 | { 0x40ac8, 0xd9d9d9 }, | ||
249 | { 0x40acc, 0xd9d9d9 }, | ||
250 | { 0x40ad0, 0xdadada }, | ||
251 | { 0x40ad4, 0xdbdbdb }, | ||
252 | { 0x40ad8, 0xdbdbdb }, | ||
253 | { 0x40adc, 0xdcdcdc }, | ||
254 | { 0x40ae0, 0xdcdcdc }, | ||
255 | { 0x40ae4, 0xdddddd }, | ||
256 | { 0x40ae8, 0xdddddd }, | ||
257 | { 0x40aec, 0xdedede }, | ||
258 | { 0x40af0, 0xdedede }, | ||
259 | { 0x40af4, 0xdfdfdf }, | ||
260 | { 0x40af8, 0xdfdfdf }, | ||
261 | { 0x40afc, 0xe0e0e0 }, | ||
262 | { 0x40b00, 0xe0e0e0 }, | ||
263 | { 0x40b04, 0xe1e1e1 }, | ||
264 | { 0x40b08, 0xe1e1e1 }, | ||
265 | { 0x40b0c, 0xe2e2e2 }, | ||
266 | { 0x40b10, 0xe3e3e3 }, | ||
267 | { 0x40b14, 0xe3e3e3 }, | ||
268 | { 0x40b18, 0xe4e4e4 }, | ||
269 | { 0x40b1c, 0xe4e4e4 }, | ||
270 | { 0x40b20, 0xe5e5e5 }, | ||
271 | { 0x40b24, 0xe5e5e5 }, | ||
272 | { 0x40b28, 0xe6e6e6 }, | ||
273 | { 0x40b2c, 0xe6e6e6 }, | ||
274 | { 0x40b30, 0xe7e7e7 }, | ||
275 | { 0x40b34, 0xe7e7e7 }, | ||
276 | { 0x40b38, 0xe8e8e8 }, | ||
277 | { 0x40b3c, 0xe8e8e8 }, | ||
278 | { 0x40b40, 0xe9e9e9 }, | ||
279 | { 0x40b44, 0xe9e9e9 }, | ||
280 | { 0x40b48, 0xeaeaea }, | ||
281 | { 0x40b4c, 0xeaeaea }, | ||
282 | { 0x40b50, 0xebebeb }, | ||
283 | { 0x40b54, 0xebebeb }, | ||
284 | { 0x40b58, 0xececec }, | ||
285 | { 0x40b5c, 0xececec }, | ||
286 | { 0x40b60, 0xededed }, | ||
287 | { 0x40b64, 0xededed }, | ||
288 | { 0x40b68, 0xeeeeee }, | ||
289 | { 0x40b6c, 0xeeeeee }, | ||
290 | { 0x40b70, 0xefefef }, | ||
291 | { 0x40b74, 0xefefef }, | ||
292 | { 0x40b78, 0xf0f0f0 }, | ||
293 | { 0x40b7c, 0xf0f0f0 }, | ||
294 | { 0x40b80, 0xf1f1f1 }, | ||
295 | { 0x40b84, 0xf1f1f1 }, | ||
296 | { 0x40b88, 0xf2f2f2 }, | ||
297 | { 0x40b8c, 0xf2f2f2 }, | ||
298 | { 0x40b90, 0xf2f2f2 }, | ||
299 | { 0x40b94, 0xf3f3f3 }, | ||
300 | { 0x40b98, 0xf3f3f3 }, | ||
301 | { 0x40b9c, 0xf4f4f4 }, | ||
302 | { 0x40ba0, 0xf4f4f4 }, | ||
303 | { 0x40ba4, 0xf5f5f5 }, | ||
304 | { 0x40ba8, 0xf5f5f5 }, | ||
305 | { 0x40bac, 0xf6f6f6 }, | ||
306 | { 0x40bb0, 0xf6f6f6 }, | ||
307 | { 0x40bb4, 0xf7f7f7 }, | ||
308 | { 0x40bb8, 0xf7f7f7 }, | ||
309 | { 0x40bbc, 0xf8f8f8 }, | ||
310 | { 0x40bc0, 0xf8f8f8 }, | ||
311 | { 0x40bc4, 0xf9f9f9 }, | ||
312 | { 0x40bc8, 0xf9f9f9 }, | ||
313 | { 0x40bcc, 0xfafafa }, | ||
314 | { 0x40bd0, 0xfafafa }, | ||
315 | { 0x40bd4, 0xfafafa }, | ||
316 | { 0x40bd8, 0xfbfbfb }, | ||
317 | { 0x40bdc, 0xfbfbfb }, | ||
318 | { 0x40be0, 0xfcfcfc }, | ||
319 | { 0x40be4, 0xfcfcfc }, | ||
320 | { 0x40be8, 0xfdfdfd }, | ||
321 | { 0x40bec, 0xfdfdfd }, | ||
322 | { 0x40bf0, 0xfefefe }, | ||
323 | { 0x40bf4, 0xfefefe }, | ||
324 | { 0x40bf8, 0xffffff }, | ||
325 | { 0x40bfc, 0xffffff }, | ||
326 | { 0x40c00, 0x0 }, | ||
327 | { 0x40c04, 0x0 }, | ||
328 | { 0x40c08, 0x0 }, | ||
329 | { 0x40c0c, 0x0 }, | ||
330 | { 0x40c10, 0x0 }, | ||
331 | { 0x40c14, 0x0 }, | ||
332 | { 0x40c18, 0x0 }, | ||
333 | { 0x40c1c, 0x0 }, | ||
334 | { 0x40c20, 0x0 }, | ||
335 | { 0x40c24, 0x0 }, | ||
336 | { 0x40c28, 0x0 }, | ||
337 | { 0x40c2c, 0x0 }, | ||
338 | { 0x40c30, 0x0 }, | ||
339 | { 0x40c34, 0x0 }, | ||
340 | { 0x40c38, 0x0 }, | ||
341 | { 0x40c3c, 0x0 }, | ||
342 | { 0x40c40, 0x10101 }, | ||
343 | { 0x40c44, 0x10101 }, | ||
344 | { 0x40c48, 0x10101 }, | ||
345 | { 0x40c4c, 0x10101 }, | ||
346 | { 0x40c50, 0x10101 }, | ||
347 | { 0x40c54, 0x10101 }, | ||
348 | { 0x40c58, 0x10101 }, | ||
349 | { 0x40c5c, 0x10101 }, | ||
350 | { 0x40c60, 0x10101 }, | ||
351 | { 0x40c64, 0x10101 }, | ||
352 | { 0x40c68, 0x20202 }, | ||
353 | { 0x40c6c, 0x20202 }, | ||
354 | { 0x40c70, 0x20202 }, | ||
355 | { 0x40c74, 0x20202 }, | ||
356 | { 0x40c78, 0x20202 }, | ||
357 | { 0x40c7c, 0x20202 }, | ||
358 | { 0x40c80, 0x30303 }, | ||
359 | { 0x40c84, 0x30303 }, | ||
360 | { 0x40c88, 0x30303 }, | ||
361 | { 0x40c8c, 0x30303 }, | ||
362 | { 0x40c90, 0x30303 }, | ||
363 | { 0x40c94, 0x40404 }, | ||
364 | { 0x40c98, 0x40404 }, | ||
365 | { 0x40c9c, 0x40404 }, | ||
366 | { 0x40ca0, 0x40404 }, | ||
367 | { 0x40ca4, 0x40404 }, | ||
368 | { 0x40ca8, 0x50505 }, | ||
369 | { 0x40cac, 0x50505 }, | ||
370 | { 0x40cb0, 0x50505 }, | ||
371 | { 0x40cb4, 0x50505 }, | ||
372 | { 0x40cb8, 0x60606 }, | ||
373 | { 0x40cbc, 0x60606 }, | ||
374 | { 0x40cc0, 0x60606 }, | ||
375 | { 0x40cc4, 0x70707 }, | ||
376 | { 0x40cc8, 0x70707 }, | ||
377 | { 0x40ccc, 0x70707 }, | ||
378 | { 0x40cd0, 0x70707 }, | ||
379 | { 0x40cd4, 0x80808 }, | ||
380 | { 0x40cd8, 0x80808 }, | ||
381 | { 0x40cdc, 0x80808 }, | ||
382 | { 0x40ce0, 0x90909 }, | ||
383 | { 0x40ce4, 0x90909 }, | ||
384 | { 0x40ce8, 0xa0a0a }, | ||
385 | { 0x40cec, 0xa0a0a }, | ||
386 | { 0x40cf0, 0xa0a0a }, | ||
387 | { 0x40cf4, 0xb0b0b }, | ||
388 | { 0x40cf8, 0xb0b0b }, | ||
389 | { 0x40cfc, 0xb0b0b }, | ||
390 | { 0x40d00, 0xc0c0c }, | ||
391 | { 0x40d04, 0xc0c0c }, | ||
392 | { 0x40d08, 0xd0d0d }, | ||
393 | { 0x40d0c, 0xd0d0d }, | ||
394 | { 0x40d10, 0xe0e0e }, | ||
395 | { 0x40d14, 0xe0e0e }, | ||
396 | { 0x40d18, 0xe0e0e }, | ||
397 | { 0x40d1c, 0xf0f0f }, | ||
398 | { 0x40d20, 0xf0f0f }, | ||
399 | { 0x40d24, 0x101010 }, | ||
400 | { 0x40d28, 0x101010 }, | ||
401 | { 0x40d2c, 0x111111 }, | ||
402 | { 0x40d30, 0x111111 }, | ||
403 | { 0x40d34, 0x121212 }, | ||
404 | { 0x40d38, 0x121212 }, | ||
405 | { 0x40d3c, 0x131313 }, | ||
406 | { 0x40d40, 0x131313 }, | ||
407 | { 0x40d44, 0x141414 }, | ||
408 | { 0x40d48, 0x151515 }, | ||
409 | { 0x40d4c, 0x151515 }, | ||
410 | { 0x40d50, 0x161616 }, | ||
411 | { 0x40d54, 0x161616 }, | ||
412 | { 0x40d58, 0x171717 }, | ||
413 | { 0x40d5c, 0x171717 }, | ||
414 | { 0x40d60, 0x181818 }, | ||
415 | { 0x40d64, 0x191919 }, | ||
416 | { 0x40d68, 0x191919 }, | ||
417 | { 0x40d6c, 0x1a1a1a }, | ||
418 | { 0x40d70, 0x1b1b1b }, | ||
419 | { 0x40d74, 0x1b1b1b }, | ||
420 | { 0x40d78, 0x1c1c1c }, | ||
421 | { 0x40d7c, 0x1c1c1c }, | ||
422 | { 0x40d80, 0x1d1d1d }, | ||
423 | { 0x40d84, 0x1e1e1e }, | ||
424 | { 0x40d88, 0x1f1f1f }, | ||
425 | { 0x40d8c, 0x1f1f1f }, | ||
426 | { 0x40d90, 0x202020 }, | ||
427 | { 0x40d94, 0x212121 }, | ||
428 | { 0x40d98, 0x212121 }, | ||
429 | { 0x40d9c, 0x222222 }, | ||
430 | { 0x40da0, 0x232323 }, | ||
431 | { 0x40da4, 0x242424 }, | ||
432 | { 0x40da8, 0x242424 }, | ||
433 | { 0x40dac, 0x252525 }, | ||
434 | { 0x40db0, 0x262626 }, | ||
435 | { 0x40db4, 0x272727 }, | ||
436 | { 0x40db8, 0x272727 }, | ||
437 | { 0x40dbc, 0x282828 }, | ||
438 | { 0x40dc0, 0x292929 }, | ||
439 | { 0x40dc4, 0x2a2a2a }, | ||
440 | { 0x40dc8, 0x2b2b2b }, | ||
441 | { 0x40dcc, 0x2c2c2c }, | ||
442 | { 0x40dd0, 0x2c2c2c }, | ||
443 | { 0x40dd4, 0x2d2d2d }, | ||
444 | { 0x40dd8, 0x2e2e2e }, | ||
445 | { 0x40ddc, 0x2f2f2f }, | ||
446 | { 0x40de0, 0x303030 }, | ||
447 | { 0x40de4, 0x313131 }, | ||
448 | { 0x40de8, 0x323232 }, | ||
449 | { 0x40dec, 0x333333 }, | ||
450 | { 0x40df0, 0x333333 }, | ||
451 | { 0x40df4, 0x343434 }, | ||
452 | { 0x40df8, 0x353535 }, | ||
453 | { 0x40dfc, 0x363636 }, | ||
454 | { 0x40e00, 0x373737 }, | ||
455 | { 0x40e04, 0x383838 }, | ||
456 | { 0x40e08, 0x393939 }, | ||
457 | { 0x40e0c, 0x3a3a3a }, | ||
458 | { 0x40e10, 0x3b3b3b }, | ||
459 | { 0x40e14, 0x3c3c3c }, | ||
460 | { 0x40e18, 0x3d3d3d }, | ||
461 | { 0x40e1c, 0x3e3e3e }, | ||
462 | { 0x40e20, 0x3f3f3f }, | ||
463 | { 0x40e24, 0x404040 }, | ||
464 | { 0x40e28, 0x414141 }, | ||
465 | { 0x40e2c, 0x424242 }, | ||
466 | { 0x40e30, 0x434343 }, | ||
467 | { 0x40e34, 0x444444 }, | ||
468 | { 0x40e38, 0x464646 }, | ||
469 | { 0x40e3c, 0x474747 }, | ||
470 | { 0x40e40, 0x484848 }, | ||
471 | { 0x40e44, 0x494949 }, | ||
472 | { 0x40e48, 0x4a4a4a }, | ||
473 | { 0x40e4c, 0x4b4b4b }, | ||
474 | { 0x40e50, 0x4c4c4c }, | ||
475 | { 0x40e54, 0x4d4d4d }, | ||
476 | { 0x40e58, 0x4f4f4f }, | ||
477 | { 0x40e5c, 0x505050 }, | ||
478 | { 0x40e60, 0x515151 }, | ||
479 | { 0x40e64, 0x525252 }, | ||
480 | { 0x40e68, 0x535353 }, | ||
481 | { 0x40e6c, 0x545454 }, | ||
482 | { 0x40e70, 0x565656 }, | ||
483 | { 0x40e74, 0x575757 }, | ||
484 | { 0x40e78, 0x585858 }, | ||
485 | { 0x40e7c, 0x595959 }, | ||
486 | { 0x40e80, 0x5b5b5b }, | ||
487 | { 0x40e84, 0x5c5c5c }, | ||
488 | { 0x40e88, 0x5d5d5d }, | ||
489 | { 0x40e8c, 0x5e5e5e }, | ||
490 | { 0x40e90, 0x606060 }, | ||
491 | { 0x40e94, 0x616161 }, | ||
492 | { 0x40e98, 0x626262 }, | ||
493 | { 0x40e9c, 0x646464 }, | ||
494 | { 0x40ea0, 0x656565 }, | ||
495 | { 0x40ea4, 0x666666 }, | ||
496 | { 0x40ea8, 0x686868 }, | ||
497 | { 0x40eac, 0x696969 }, | ||
498 | { 0x40eb0, 0x6a6a6a }, | ||
499 | { 0x40eb4, 0x6c6c6c }, | ||
500 | { 0x40eb8, 0x6d6d6d }, | ||
501 | { 0x40ebc, 0x6f6f6f }, | ||
502 | { 0x40ec0, 0x707070 }, | ||
503 | { 0x40ec4, 0x717171 }, | ||
504 | { 0x40ec8, 0x737373 }, | ||
505 | { 0x40ecc, 0x747474 }, | ||
506 | { 0x40ed0, 0x767676 }, | ||
507 | { 0x40ed4, 0x777777 }, | ||
508 | { 0x40ed8, 0x797979 }, | ||
509 | { 0x40edc, 0x7a7a7a }, | ||
510 | { 0x40ee0, 0x7c7c7c }, | ||
511 | { 0x40ee4, 0x7d7d7d }, | ||
512 | { 0x40ee8, 0x7f7f7f }, | ||
513 | { 0x40eec, 0x808080 }, | ||
514 | { 0x40ef0, 0x828282 }, | ||
515 | { 0x40ef4, 0x838383 }, | ||
516 | { 0x40ef8, 0x858585 }, | ||
517 | { 0x40efc, 0x868686 }, | ||
518 | { 0x40f00, 0x888888 }, | ||
519 | { 0x40f04, 0x898989 }, | ||
520 | { 0x40f08, 0x8b8b8b }, | ||
521 | { 0x40f0c, 0x8d8d8d }, | ||
522 | { 0x40f10, 0x8e8e8e }, | ||
523 | { 0x40f14, 0x909090 }, | ||
524 | { 0x40f18, 0x919191 }, | ||
525 | { 0x40f1c, 0x939393 }, | ||
526 | { 0x40f20, 0x959595 }, | ||
527 | { 0x40f24, 0x969696 }, | ||
528 | { 0x40f28, 0x989898 }, | ||
529 | { 0x40f2c, 0x9a9a9a }, | ||
530 | { 0x40f30, 0x9b9b9b }, | ||
531 | { 0x40f34, 0x9d9d9d }, | ||
532 | { 0x40f38, 0x9f9f9f }, | ||
533 | { 0x40f3c, 0xa1a1a1 }, | ||
534 | { 0x40f40, 0xa2a2a2 }, | ||
535 | { 0x40f44, 0xa4a4a4 }, | ||
536 | { 0x40f48, 0xa6a6a6 }, | ||
537 | { 0x40f4c, 0xa7a7a7 }, | ||
538 | { 0x40f50, 0xa9a9a9 }, | ||
539 | { 0x40f54, 0xababab }, | ||
540 | { 0x40f58, 0xadadad }, | ||
541 | { 0x40f5c, 0xafafaf }, | ||
542 | { 0x40f60, 0xb0b0b0 }, | ||
543 | { 0x40f64, 0xb2b2b2 }, | ||
544 | { 0x40f68, 0xb4b4b4 }, | ||
545 | { 0x40f6c, 0xb6b6b6 }, | ||
546 | { 0x40f70, 0xb8b8b8 }, | ||
547 | { 0x40f74, 0xbababa }, | ||
548 | { 0x40f78, 0xbbbbbb }, | ||
549 | { 0x40f7c, 0xbdbdbd }, | ||
550 | { 0x40f80, 0xbfbfbf }, | ||
551 | { 0x40f84, 0xc1c1c1 }, | ||
552 | { 0x40f88, 0xc3c3c3 }, | ||
553 | { 0x40f8c, 0xc5c5c5 }, | ||
554 | { 0x40f90, 0xc7c7c7 }, | ||
555 | { 0x40f94, 0xc9c9c9 }, | ||
556 | { 0x40f98, 0xcbcbcb }, | ||
557 | { 0x40f9c, 0xcdcdcd }, | ||
558 | { 0x40fa0, 0xcfcfcf }, | ||
559 | { 0x40fa4, 0xd1d1d1 }, | ||
560 | { 0x40fa8, 0xd3d3d3 }, | ||
561 | { 0x40fac, 0xd5d5d5 }, | ||
562 | { 0x40fb0, 0xd7d7d7 }, | ||
563 | { 0x40fb4, 0xd9d9d9 }, | ||
564 | { 0x40fb8, 0xdbdbdb }, | ||
565 | { 0x40fbc, 0xdddddd }, | ||
566 | { 0x40fc0, 0xdfdfdf }, | ||
567 | { 0x40fc4, 0xe1e1e1 }, | ||
568 | { 0x40fc8, 0xe3e3e3 }, | ||
569 | { 0x40fcc, 0xe5e5e5 }, | ||
570 | { 0x40fd0, 0xe7e7e7 }, | ||
571 | { 0x40fd4, 0xe9e9e9 }, | ||
572 | { 0x40fd8, 0xebebeb }, | ||
573 | { 0x40fdc, 0xeeeeee }, | ||
574 | { 0x40fe0, 0xf0f0f0 }, | ||
575 | { 0x40fe4, 0xf2f2f2 }, | ||
576 | { 0x40fe8, 0xf4f4f4 }, | ||
577 | { 0x40fec, 0xf6f6f6 }, | ||
578 | { 0x40ff0, 0xf8f8f8 }, | ||
579 | { 0x40ff4, 0xfbfbfb }, | ||
580 | { 0x40ff8, 0xfdfdfd }, | ||
581 | { 0x40ffc, 0xffffff }, | ||
582 | }; | ||
diff --git a/drivers/video/fbdev/msm/mdp_hw.h b/drivers/video/fbdev/msm/mdp_hw.h deleted file mode 100644 index 35848d741001..000000000000 --- a/drivers/video/fbdev/msm/mdp_hw.h +++ /dev/null | |||
@@ -1,627 +0,0 @@ | |||
1 | /* drivers/video/msm_fb/mdp_hw.h | ||
2 | * | ||
3 | * Copyright (C) 2007 QUALCOMM Incorporated | ||
4 | * Copyright (C) 2007 Google Incorporated | ||
5 | * | ||
6 | * This software is licensed under the terms of the GNU General Public | ||
7 | * License version 2, as published by the Free Software Foundation, and | ||
8 | * may be copied, distributed, and modified under those terms. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | #ifndef _MDP_HW_H_ | ||
16 | #define _MDP_HW_H_ | ||
17 | |||
18 | #include <linux/platform_data/video-msm_fb.h> | ||
19 | |||
20 | struct mdp_info { | ||
21 | struct mdp_device mdp_dev; | ||
22 | char * __iomem base; | ||
23 | int irq; | ||
24 | }; | ||
25 | struct mdp_blit_req; | ||
26 | struct mdp_device; | ||
27 | int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, | ||
28 | struct file *src_file, unsigned long src_start, | ||
29 | unsigned long src_len, struct file *dst_file, | ||
30 | unsigned long dst_start, unsigned long dst_len); | ||
31 | #define mdp_writel(mdp, value, offset) writel(value, mdp->base + offset) | ||
32 | #define mdp_readl(mdp, offset) readl(mdp->base + offset) | ||
33 | |||
34 | #define MDP_SYNC_CONFIG_0 (0x00000) | ||
35 | #define MDP_SYNC_CONFIG_1 (0x00004) | ||
36 | #define MDP_SYNC_CONFIG_2 (0x00008) | ||
37 | #define MDP_SYNC_STATUS_0 (0x0000c) | ||
38 | #define MDP_SYNC_STATUS_1 (0x00010) | ||
39 | #define MDP_SYNC_STATUS_2 (0x00014) | ||
40 | #define MDP_SYNC_THRESH_0 (0x00018) | ||
41 | #define MDP_SYNC_THRESH_1 (0x0001c) | ||
42 | #define MDP_INTR_ENABLE (0x00020) | ||
43 | #define MDP_INTR_STATUS (0x00024) | ||
44 | #define MDP_INTR_CLEAR (0x00028) | ||
45 | #define MDP_DISPLAY0_START (0x00030) | ||
46 | #define MDP_DISPLAY1_START (0x00034) | ||
47 | #define MDP_DISPLAY_STATUS (0x00038) | ||
48 | #define MDP_EBI2_LCD0 (0x0003c) | ||
49 | #define MDP_EBI2_LCD1 (0x00040) | ||
50 | #define MDP_DISPLAY0_ADDR (0x00054) | ||
51 | #define MDP_DISPLAY1_ADDR (0x00058) | ||
52 | #define MDP_EBI2_PORTMAP_MODE (0x0005c) | ||
53 | #define MDP_MODE (0x00060) | ||
54 | #define MDP_TV_OUT_STATUS (0x00064) | ||
55 | #define MDP_HW_VERSION (0x00070) | ||
56 | #define MDP_SW_RESET (0x00074) | ||
57 | #define MDP_AXI_ERROR_MASTER_STOP (0x00078) | ||
58 | #define MDP_SEL_CLK_OR_HCLK_TEST_BUS (0x0007c) | ||
59 | #define MDP_PRIMARY_VSYNC_OUT_CTRL (0x00080) | ||
60 | #define MDP_SECONDARY_VSYNC_OUT_CTRL (0x00084) | ||
61 | #define MDP_EXTERNAL_VSYNC_OUT_CTRL (0x00088) | ||
62 | #define MDP_VSYNC_CTRL (0x0008c) | ||
63 | #define MDP_CGC_EN (0x00100) | ||
64 | #define MDP_CMD_STATUS (0x10008) | ||
65 | #define MDP_PROFILE_EN (0x10010) | ||
66 | #define MDP_PROFILE_COUNT (0x10014) | ||
67 | #define MDP_DMA_START (0x10044) | ||
68 | #define MDP_FULL_BYPASS_WORD0 (0x10100) | ||
69 | #define MDP_FULL_BYPASS_WORD1 (0x10104) | ||
70 | #define MDP_COMMAND_CONFIG (0x10104) | ||
71 | #define MDP_FULL_BYPASS_WORD2 (0x10108) | ||
72 | #define MDP_FULL_BYPASS_WORD3 (0x1010c) | ||
73 | #define MDP_FULL_BYPASS_WORD4 (0x10110) | ||
74 | #define MDP_FULL_BYPASS_WORD6 (0x10118) | ||
75 | #define MDP_FULL_BYPASS_WORD7 (0x1011c) | ||
76 | #define MDP_FULL_BYPASS_WORD8 (0x10120) | ||
77 | #define MDP_FULL_BYPASS_WORD9 (0x10124) | ||
78 | #define MDP_PPP_SOURCE_CONFIG (0x10124) | ||
79 | #define MDP_FULL_BYPASS_WORD10 (0x10128) | ||
80 | #define MDP_FULL_BYPASS_WORD11 (0x1012c) | ||
81 | #define MDP_FULL_BYPASS_WORD12 (0x10130) | ||
82 | #define MDP_FULL_BYPASS_WORD13 (0x10134) | ||
83 | #define MDP_FULL_BYPASS_WORD14 (0x10138) | ||
84 | #define MDP_PPP_OPERATION_CONFIG (0x10138) | ||
85 | #define MDP_FULL_BYPASS_WORD15 (0x1013c) | ||
86 | #define MDP_FULL_BYPASS_WORD16 (0x10140) | ||
87 | #define MDP_FULL_BYPASS_WORD17 (0x10144) | ||
88 | #define MDP_FULL_BYPASS_WORD18 (0x10148) | ||
89 | #define MDP_FULL_BYPASS_WORD19 (0x1014c) | ||
90 | #define MDP_FULL_BYPASS_WORD20 (0x10150) | ||
91 | #define MDP_PPP_DESTINATION_CONFIG (0x10150) | ||
92 | #define MDP_FULL_BYPASS_WORD21 (0x10154) | ||
93 | #define MDP_FULL_BYPASS_WORD22 (0x10158) | ||
94 | #define MDP_FULL_BYPASS_WORD23 (0x1015c) | ||
95 | #define MDP_FULL_BYPASS_WORD24 (0x10160) | ||
96 | #define MDP_FULL_BYPASS_WORD25 (0x10164) | ||
97 | #define MDP_FULL_BYPASS_WORD26 (0x10168) | ||
98 | #define MDP_FULL_BYPASS_WORD27 (0x1016c) | ||
99 | #define MDP_FULL_BYPASS_WORD29 (0x10174) | ||
100 | #define MDP_FULL_BYPASS_WORD30 (0x10178) | ||
101 | #define MDP_FULL_BYPASS_WORD31 (0x1017c) | ||
102 | #define MDP_FULL_BYPASS_WORD32 (0x10180) | ||
103 | #define MDP_DMA_CONFIG (0x10180) | ||
104 | #define MDP_FULL_BYPASS_WORD33 (0x10184) | ||
105 | #define MDP_FULL_BYPASS_WORD34 (0x10188) | ||
106 | #define MDP_FULL_BYPASS_WORD35 (0x1018c) | ||
107 | #define MDP_FULL_BYPASS_WORD37 (0x10194) | ||
108 | #define MDP_FULL_BYPASS_WORD39 (0x1019c) | ||
109 | #define MDP_FULL_BYPASS_WORD40 (0x101a0) | ||
110 | #define MDP_FULL_BYPASS_WORD41 (0x101a4) | ||
111 | #define MDP_FULL_BYPASS_WORD43 (0x101ac) | ||
112 | #define MDP_FULL_BYPASS_WORD46 (0x101b8) | ||
113 | #define MDP_FULL_BYPASS_WORD47 (0x101bc) | ||
114 | #define MDP_FULL_BYPASS_WORD48 (0x101c0) | ||
115 | #define MDP_FULL_BYPASS_WORD49 (0x101c4) | ||
116 | #define MDP_FULL_BYPASS_WORD50 (0x101c8) | ||
117 | #define MDP_FULL_BYPASS_WORD51 (0x101cc) | ||
118 | #define MDP_FULL_BYPASS_WORD52 (0x101d0) | ||
119 | #define MDP_FULL_BYPASS_WORD53 (0x101d4) | ||
120 | #define MDP_FULL_BYPASS_WORD54 (0x101d8) | ||
121 | #define MDP_FULL_BYPASS_WORD55 (0x101dc) | ||
122 | #define MDP_FULL_BYPASS_WORD56 (0x101e0) | ||
123 | #define MDP_FULL_BYPASS_WORD57 (0x101e4) | ||
124 | #define MDP_FULL_BYPASS_WORD58 (0x101e8) | ||
125 | #define MDP_FULL_BYPASS_WORD59 (0x101ec) | ||
126 | #define MDP_FULL_BYPASS_WORD60 (0x101f0) | ||
127 | #define MDP_VSYNC_THRESHOLD (0x101f0) | ||
128 | #define MDP_FULL_BYPASS_WORD61 (0x101f4) | ||
129 | #define MDP_FULL_BYPASS_WORD62 (0x101f8) | ||
130 | #define MDP_FULL_BYPASS_WORD63 (0x101fc) | ||
131 | #define MDP_TFETCH_TEST_MODE (0x20004) | ||
132 | #define MDP_TFETCH_STATUS (0x20008) | ||
133 | #define MDP_TFETCH_TILE_COUNT (0x20010) | ||
134 | #define MDP_TFETCH_FETCH_COUNT (0x20014) | ||
135 | #define MDP_TFETCH_CONSTANT_COLOR (0x20040) | ||
136 | #define MDP_CSC_BYPASS (0x40004) | ||
137 | #define MDP_SCALE_COEFF_LSB (0x5fffc) | ||
138 | #define MDP_TV_OUT_CTL (0xc0000) | ||
139 | #define MDP_TV_OUT_FIR_COEFF (0xc0004) | ||
140 | #define MDP_TV_OUT_BUF_ADDR (0xc0008) | ||
141 | #define MDP_TV_OUT_CC_DATA (0xc000c) | ||
142 | #define MDP_TV_OUT_SOBEL (0xc0010) | ||
143 | #define MDP_TV_OUT_Y_CLAMP (0xc0018) | ||
144 | #define MDP_TV_OUT_CB_CLAMP (0xc001c) | ||
145 | #define MDP_TV_OUT_CR_CLAMP (0xc0020) | ||
146 | #define MDP_TEST_MODE_CLK (0xd0000) | ||
147 | #define MDP_TEST_MISR_RESET_CLK (0xd0004) | ||
148 | #define MDP_TEST_EXPORT_MISR_CLK (0xd0008) | ||
149 | #define MDP_TEST_MISR_CURR_VAL_CLK (0xd000c) | ||
150 | #define MDP_TEST_MODE_HCLK (0xd0100) | ||
151 | #define MDP_TEST_MISR_RESET_HCLK (0xd0104) | ||
152 | #define MDP_TEST_EXPORT_MISR_HCLK (0xd0108) | ||
153 | #define MDP_TEST_MISR_CURR_VAL_HCLK (0xd010c) | ||
154 | #define MDP_TEST_MODE_DCLK (0xd0200) | ||
155 | #define MDP_TEST_MISR_RESET_DCLK (0xd0204) | ||
156 | #define MDP_TEST_EXPORT_MISR_DCLK (0xd0208) | ||
157 | #define MDP_TEST_MISR_CURR_VAL_DCLK (0xd020c) | ||
158 | #define MDP_TEST_CAPTURED_DCLK (0xd0210) | ||
159 | #define MDP_TEST_MISR_CAPT_VAL_DCLK (0xd0214) | ||
160 | #define MDP_LCDC_CTL (0xe0000) | ||
161 | #define MDP_LCDC_HSYNC_CTL (0xe0004) | ||
162 | #define MDP_LCDC_VSYNC_CTL (0xe0008) | ||
163 | #define MDP_LCDC_ACTIVE_HCTL (0xe000c) | ||
164 | #define MDP_LCDC_ACTIVE_VCTL (0xe0010) | ||
165 | #define MDP_LCDC_BORDER_CLR (0xe0014) | ||
166 | #define MDP_LCDC_H_BLANK (0xe0018) | ||
167 | #define MDP_LCDC_V_BLANK (0xe001c) | ||
168 | #define MDP_LCDC_UNDERFLOW_CLR (0xe0020) | ||
169 | #define MDP_LCDC_HSYNC_SKEW (0xe0024) | ||
170 | #define MDP_LCDC_TEST_CTL (0xe0028) | ||
171 | #define MDP_LCDC_LINE_IRQ (0xe002c) | ||
172 | #define MDP_LCDC_CTL_POLARITY (0xe0030) | ||
173 | #define MDP_LCDC_DMA_CONFIG (0xe1000) | ||
174 | #define MDP_LCDC_DMA_SIZE (0xe1004) | ||
175 | #define MDP_LCDC_DMA_IBUF_ADDR (0xe1008) | ||
176 | #define MDP_LCDC_DMA_IBUF_Y_STRIDE (0xe100c) | ||
177 | |||
178 | |||
179 | #define MDP_DMA2_TERM 0x1 | ||
180 | #define MDP_DMA3_TERM 0x2 | ||
181 | #define MDP_PPP_TERM 0x3 | ||
182 | |||
183 | /* MDP_INTR_ENABLE */ | ||
184 | #define DL0_ROI_DONE (1<<0) | ||
185 | #define DL1_ROI_DONE (1<<1) | ||
186 | #define DL0_DMA2_TERM_DONE (1<<2) | ||
187 | #define DL1_DMA2_TERM_DONE (1<<3) | ||
188 | #define DL0_PPP_TERM_DONE (1<<4) | ||
189 | #define DL1_PPP_TERM_DONE (1<<5) | ||
190 | #define TV_OUT_DMA3_DONE (1<<6) | ||
191 | #define TV_ENC_UNDERRUN (1<<7) | ||
192 | #define DL0_FETCH_DONE (1<<11) | ||
193 | #define DL1_FETCH_DONE (1<<12) | ||
194 | |||
195 | #define MDP_PPP_BUSY_STATUS (DL0_ROI_DONE| \ | ||
196 | DL1_ROI_DONE| \ | ||
197 | DL0_PPP_TERM_DONE| \ | ||
198 | DL1_PPP_TERM_DONE) | ||
199 | |||
200 | #define MDP_ANY_INTR_MASK (DL0_ROI_DONE| \ | ||
201 | DL1_ROI_DONE| \ | ||
202 | DL0_DMA2_TERM_DONE| \ | ||
203 | DL1_DMA2_TERM_DONE| \ | ||
204 | DL0_PPP_TERM_DONE| \ | ||
205 | DL1_PPP_TERM_DONE| \ | ||
206 | DL0_FETCH_DONE| \ | ||
207 | DL1_FETCH_DONE| \ | ||
208 | TV_ENC_UNDERRUN) | ||
209 | |||
210 | #define MDP_TOP_LUMA 16 | ||
211 | #define MDP_TOP_CHROMA 0 | ||
212 | #define MDP_BOTTOM_LUMA 19 | ||
213 | #define MDP_BOTTOM_CHROMA 3 | ||
214 | #define MDP_LEFT_LUMA 22 | ||
215 | #define MDP_LEFT_CHROMA 6 | ||
216 | #define MDP_RIGHT_LUMA 25 | ||
217 | #define MDP_RIGHT_CHROMA 9 | ||
218 | |||
219 | #define CLR_G 0x0 | ||
220 | #define CLR_B 0x1 | ||
221 | #define CLR_R 0x2 | ||
222 | #define CLR_ALPHA 0x3 | ||
223 | |||
224 | #define CLR_Y CLR_G | ||
225 | #define CLR_CB CLR_B | ||
226 | #define CLR_CR CLR_R | ||
227 | |||
228 | /* from lsb to msb */ | ||
229 | #define MDP_GET_PACK_PATTERN(a, x, y, z, bit) \ | ||
230 | (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z)) | ||
231 | |||
232 | /* MDP_SYNC_CONFIG_0/1/2 */ | ||
233 | #define MDP_SYNCFG_HGT_LOC 22 | ||
234 | #define MDP_SYNCFG_VSYNC_EXT_EN (1<<21) | ||
235 | #define MDP_SYNCFG_VSYNC_INT_EN (1<<20) | ||
236 | |||
237 | /* MDP_SYNC_THRESH_0 */ | ||
238 | #define MDP_PRIM_BELOW_LOC 0 | ||
239 | #define MDP_PRIM_ABOVE_LOC 8 | ||
240 | |||
241 | /* MDP_{PRIMARY,SECONDARY,EXTERNAL}_VSYNC_OUT_CRL */ | ||
242 | #define VSYNC_PULSE_EN (1<<31) | ||
243 | #define VSYNC_PULSE_INV (1<<30) | ||
244 | |||
245 | /* MDP_VSYNC_CTRL */ | ||
246 | #define DISP0_VSYNC_MAP_VSYNC0 0 | ||
247 | #define DISP0_VSYNC_MAP_VSYNC1 (1<<0) | ||
248 | #define DISP0_VSYNC_MAP_VSYNC2 ((1<<0)|(1<<1)) | ||
249 | |||
250 | #define DISP1_VSYNC_MAP_VSYNC0 0 | ||
251 | #define DISP1_VSYNC_MAP_VSYNC1 (1<<2) | ||
252 | #define DISP1_VSYNC_MAP_VSYNC2 ((1<<2)|(1<<3)) | ||
253 | |||
254 | #define PRIMARY_LCD_SYNC_EN (1<<4) | ||
255 | #define PRIMARY_LCD_SYNC_DISABLE 0 | ||
256 | |||
257 | #define SECONDARY_LCD_SYNC_EN (1<<5) | ||
258 | #define SECONDARY_LCD_SYNC_DISABLE 0 | ||
259 | |||
260 | #define EXTERNAL_LCD_SYNC_EN (1<<6) | ||
261 | #define EXTERNAL_LCD_SYNC_DISABLE 0 | ||
262 | |||
263 | /* MDP_VSYNC_THRESHOLD / MDP_FULL_BYPASS_WORD60 */ | ||
264 | #define VSYNC_THRESHOLD_ABOVE_LOC 0 | ||
265 | #define VSYNC_THRESHOLD_BELOW_LOC 16 | ||
266 | #define VSYNC_ANTI_TEAR_EN (1<<31) | ||
267 | |||
268 | /* MDP_COMMAND_CONFIG / MDP_FULL_BYPASS_WORD1 */ | ||
269 | #define MDP_CMD_DBGBUS_EN (1<<0) | ||
270 | |||
271 | /* MDP_PPP_SOURCE_CONFIG / MDP_FULL_BYPASS_WORD9&53 */ | ||
272 | #define PPP_SRC_C0G_8BIT ((1<<1)|(1<<0)) | ||
273 | #define PPP_SRC_C1B_8BIT ((1<<3)|(1<<2)) | ||
274 | #define PPP_SRC_C2R_8BIT ((1<<5)|(1<<4)) | ||
275 | #define PPP_SRC_C3A_8BIT ((1<<7)|(1<<6)) | ||
276 | |||
277 | #define PPP_SRC_C0G_6BIT (1<<1) | ||
278 | #define PPP_SRC_C1B_6BIT (1<<3) | ||
279 | #define PPP_SRC_C2R_6BIT (1<<5) | ||
280 | |||
281 | #define PPP_SRC_C0G_5BIT (1<<0) | ||
282 | #define PPP_SRC_C1B_5BIT (1<<2) | ||
283 | #define PPP_SRC_C2R_5BIT (1<<4) | ||
284 | |||
285 | #define PPP_SRC_C3ALPHA_EN (1<<8) | ||
286 | |||
287 | #define PPP_SRC_BPP_1BYTES 0 | ||
288 | #define PPP_SRC_BPP_2BYTES (1<<9) | ||
289 | #define PPP_SRC_BPP_3BYTES (1<<10) | ||
290 | #define PPP_SRC_BPP_4BYTES ((1<<10)|(1<<9)) | ||
291 | |||
292 | #define PPP_SRC_BPP_ROI_ODD_X (1<<11) | ||
293 | #define PPP_SRC_BPP_ROI_ODD_Y (1<<12) | ||
294 | #define PPP_SRC_INTERLVD_2COMPONENTS (1<<13) | ||
295 | #define PPP_SRC_INTERLVD_3COMPONENTS (1<<14) | ||
296 | #define PPP_SRC_INTERLVD_4COMPONENTS ((1<<14)|(1<<13)) | ||
297 | |||
298 | |||
299 | /* RGB666 unpack format | ||
300 | ** TIGHT means R6+G6+B6 together | ||
301 | ** LOOSE means R6+2 +G6+2+ B6+2 (with MSB) | ||
302 | ** or 2+R6 +2+G6 +2+B6 (with LSB) | ||
303 | */ | ||
304 | #define PPP_SRC_PACK_TIGHT (1<<17) | ||
305 | #define PPP_SRC_PACK_LOOSE 0 | ||
306 | #define PPP_SRC_PACK_ALIGN_LSB 0 | ||
307 | #define PPP_SRC_PACK_ALIGN_MSB (1<<18) | ||
308 | |||
309 | #define PPP_SRC_PLANE_INTERLVD 0 | ||
310 | #define PPP_SRC_PLANE_PSEUDOPLNR (1<<20) | ||
311 | |||
312 | #define PPP_SRC_WMV9_MODE (1<<21) | ||
313 | |||
314 | /* MDP_PPP_OPERATION_CONFIG / MDP_FULL_BYPASS_WORD14 */ | ||
315 | #define PPP_OP_SCALE_X_ON (1<<0) | ||
316 | #define PPP_OP_SCALE_Y_ON (1<<1) | ||
317 | |||
318 | #define PPP_OP_CONVERT_RGB2YCBCR 0 | ||
319 | #define PPP_OP_CONVERT_YCBCR2RGB (1<<2) | ||
320 | #define PPP_OP_CONVERT_ON (1<<3) | ||
321 | |||
322 | #define PPP_OP_CONVERT_MATRIX_PRIMARY 0 | ||
323 | #define PPP_OP_CONVERT_MATRIX_SECONDARY (1<<4) | ||
324 | |||
325 | #define PPP_OP_LUT_C0_ON (1<<5) | ||
326 | #define PPP_OP_LUT_C1_ON (1<<6) | ||
327 | #define PPP_OP_LUT_C2_ON (1<<7) | ||
328 | |||
329 | /* rotate or blend enable */ | ||
330 | #define PPP_OP_ROT_ON (1<<8) | ||
331 | |||
332 | #define PPP_OP_ROT_90 (1<<9) | ||
333 | #define PPP_OP_FLIP_LR (1<<10) | ||
334 | #define PPP_OP_FLIP_UD (1<<11) | ||
335 | |||
336 | #define PPP_OP_BLEND_ON (1<<12) | ||
337 | |||
338 | #define PPP_OP_BLEND_SRCPIXEL_ALPHA 0 | ||
339 | #define PPP_OP_BLEND_DSTPIXEL_ALPHA (1<<13) | ||
340 | #define PPP_OP_BLEND_CONSTANT_ALPHA (1<<14) | ||
341 | #define PPP_OP_BLEND_SRCPIXEL_TRANSP ((1<<13)|(1<<14)) | ||
342 | |||
343 | #define PPP_OP_BLEND_ALPHA_BLEND_NORMAL 0 | ||
344 | #define PPP_OP_BLEND_ALPHA_BLEND_REVERSE (1<<15) | ||
345 | |||
346 | #define PPP_OP_DITHER_EN (1<<16) | ||
347 | |||
348 | #define PPP_OP_COLOR_SPACE_RGB 0 | ||
349 | #define PPP_OP_COLOR_SPACE_YCBCR (1<<17) | ||
350 | |||
351 | #define PPP_OP_SRC_CHROMA_RGB 0 | ||
352 | #define PPP_OP_SRC_CHROMA_H2V1 (1<<18) | ||
353 | #define PPP_OP_SRC_CHROMA_H1V2 (1<<19) | ||
354 | #define PPP_OP_SRC_CHROMA_420 ((1<<18)|(1<<19)) | ||
355 | #define PPP_OP_SRC_CHROMA_COSITE 0 | ||
356 | #define PPP_OP_SRC_CHROMA_OFFSITE (1<<20) | ||
357 | |||
358 | #define PPP_OP_DST_CHROMA_RGB 0 | ||
359 | #define PPP_OP_DST_CHROMA_H2V1 (1<<21) | ||
360 | #define PPP_OP_DST_CHROMA_H1V2 (1<<22) | ||
361 | #define PPP_OP_DST_CHROMA_420 ((1<<21)|(1<<22)) | ||
362 | #define PPP_OP_DST_CHROMA_COSITE 0 | ||
363 | #define PPP_OP_DST_CHROMA_OFFSITE (1<<23) | ||
364 | |||
365 | #define PPP_BLEND_ALPHA_TRANSP (1<<24) | ||
366 | |||
367 | #define PPP_OP_BG_CHROMA_RGB 0 | ||
368 | #define PPP_OP_BG_CHROMA_H2V1 (1<<25) | ||
369 | #define PPP_OP_BG_CHROMA_H1V2 (1<<26) | ||
370 | #define PPP_OP_BG_CHROMA_420 ((1<<25)|(1<<26)) | ||
371 | #define PPP_OP_BG_CHROMA_SITE_COSITE 0 | ||
372 | #define PPP_OP_BG_CHROMA_SITE_OFFSITE (1<<27) | ||
373 | |||
374 | /* MDP_PPP_DESTINATION_CONFIG / MDP_FULL_BYPASS_WORD20 */ | ||
375 | #define PPP_DST_C0G_8BIT ((1<<0)|(1<<1)) | ||
376 | #define PPP_DST_C1B_8BIT ((1<<3)|(1<<2)) | ||
377 | #define PPP_DST_C2R_8BIT ((1<<5)|(1<<4)) | ||
378 | #define PPP_DST_C3A_8BIT ((1<<7)|(1<<6)) | ||
379 | |||
380 | #define PPP_DST_C0G_6BIT (1<<1) | ||
381 | #define PPP_DST_C1B_6BIT (1<<3) | ||
382 | #define PPP_DST_C2R_6BIT (1<<5) | ||
383 | |||
384 | #define PPP_DST_C0G_5BIT (1<<0) | ||
385 | #define PPP_DST_C1B_5BIT (1<<2) | ||
386 | #define PPP_DST_C2R_5BIT (1<<4) | ||
387 | |||
388 | #define PPP_DST_C3A_8BIT ((1<<7)|(1<<6)) | ||
389 | #define PPP_DST_C3ALPHA_EN (1<<8) | ||
390 | |||
391 | #define PPP_DST_INTERLVD_2COMPONENTS (1<<9) | ||
392 | #define PPP_DST_INTERLVD_3COMPONENTS (1<<10) | ||
393 | #define PPP_DST_INTERLVD_4COMPONENTS ((1<<10)|(1<<9)) | ||
394 | #define PPP_DST_INTERLVD_6COMPONENTS ((1<<11)|(1<<9)) | ||
395 | |||
396 | #define PPP_DST_PACK_LOOSE 0 | ||
397 | #define PPP_DST_PACK_TIGHT (1<<13) | ||
398 | #define PPP_DST_PACK_ALIGN_LSB 0 | ||
399 | #define PPP_DST_PACK_ALIGN_MSB (1<<14) | ||
400 | |||
401 | #define PPP_DST_OUT_SEL_AXI 0 | ||
402 | #define PPP_DST_OUT_SEL_MDDI (1<<15) | ||
403 | |||
404 | #define PPP_DST_BPP_2BYTES (1<<16) | ||
405 | #define PPP_DST_BPP_3BYTES (1<<17) | ||
406 | #define PPP_DST_BPP_4BYTES ((1<<17)|(1<<16)) | ||
407 | |||
408 | #define PPP_DST_PLANE_INTERLVD 0 | ||
409 | #define PPP_DST_PLANE_PLANAR (1<<18) | ||
410 | #define PPP_DST_PLANE_PSEUDOPLNR (1<<19) | ||
411 | |||
412 | #define PPP_DST_TO_TV (1<<20) | ||
413 | |||
414 | #define PPP_DST_MDDI_PRIMARY 0 | ||
415 | #define PPP_DST_MDDI_SECONDARY (1<<21) | ||
416 | #define PPP_DST_MDDI_EXTERNAL (1<<22) | ||
417 | |||
418 | /* image configurations by image type */ | ||
419 | #define PPP_CFG_MDP_RGB_565(dir) (PPP_##dir##_C2R_5BIT | \ | ||
420 | PPP_##dir##_C0G_6BIT | \ | ||
421 | PPP_##dir##_C1B_5BIT | \ | ||
422 | PPP_##dir##_BPP_2BYTES | \ | ||
423 | PPP_##dir##_INTERLVD_3COMPONENTS | \ | ||
424 | PPP_##dir##_PACK_TIGHT | \ | ||
425 | PPP_##dir##_PACK_ALIGN_LSB | \ | ||
426 | PPP_##dir##_PLANE_INTERLVD) | ||
427 | |||
428 | #define PPP_CFG_MDP_RGB_888(dir) (PPP_##dir##_C2R_8BIT | \ | ||
429 | PPP_##dir##_C0G_8BIT | \ | ||
430 | PPP_##dir##_C1B_8BIT | \ | ||
431 | PPP_##dir##_BPP_3BYTES | \ | ||
432 | PPP_##dir##_INTERLVD_3COMPONENTS | \ | ||
433 | PPP_##dir##_PACK_TIGHT | \ | ||
434 | PPP_##dir##_PACK_ALIGN_LSB | \ | ||
435 | PPP_##dir##_PLANE_INTERLVD) | ||
436 | |||
437 | #define PPP_CFG_MDP_ARGB_8888(dir) (PPP_##dir##_C2R_8BIT | \ | ||
438 | PPP_##dir##_C0G_8BIT | \ | ||
439 | PPP_##dir##_C1B_8BIT | \ | ||
440 | PPP_##dir##_C3A_8BIT | \ | ||
441 | PPP_##dir##_C3ALPHA_EN | \ | ||
442 | PPP_##dir##_BPP_4BYTES | \ | ||
443 | PPP_##dir##_INTERLVD_4COMPONENTS | \ | ||
444 | PPP_##dir##_PACK_TIGHT | \ | ||
445 | PPP_##dir##_PACK_ALIGN_LSB | \ | ||
446 | PPP_##dir##_PLANE_INTERLVD) | ||
447 | |||
448 | #define PPP_CFG_MDP_XRGB_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) | ||
449 | #define PPP_CFG_MDP_RGBA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) | ||
450 | #define PPP_CFG_MDP_BGRA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) | ||
451 | #define PPP_CFG_MDP_RGBX_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) | ||
452 | |||
453 | #define PPP_CFG_MDP_Y_CBCR_H2V2(dir) (PPP_##dir##_C2R_8BIT | \ | ||
454 | PPP_##dir##_C0G_8BIT | \ | ||
455 | PPP_##dir##_C1B_8BIT | \ | ||
456 | PPP_##dir##_C3A_8BIT | \ | ||
457 | PPP_##dir##_BPP_2BYTES | \ | ||
458 | PPP_##dir##_INTERLVD_2COMPONENTS | \ | ||
459 | PPP_##dir##_PACK_TIGHT | \ | ||
460 | PPP_##dir##_PACK_ALIGN_LSB | \ | ||
461 | PPP_##dir##_PLANE_PSEUDOPLNR) | ||
462 | |||
463 | #define PPP_CFG_MDP_Y_CRCB_H2V2(dir) PPP_CFG_MDP_Y_CBCR_H2V2(dir) | ||
464 | |||
465 | #define PPP_CFG_MDP_YCRYCB_H2V1(dir) (PPP_##dir##_C2R_8BIT | \ | ||
466 | PPP_##dir##_C0G_8BIT | \ | ||
467 | PPP_##dir##_C1B_8BIT | \ | ||
468 | PPP_##dir##_C3A_8BIT | \ | ||
469 | PPP_##dir##_BPP_2BYTES | \ | ||
470 | PPP_##dir##_INTERLVD_4COMPONENTS | \ | ||
471 | PPP_##dir##_PACK_TIGHT | \ | ||
472 | PPP_##dir##_PACK_ALIGN_LSB |\ | ||
473 | PPP_##dir##_PLANE_INTERLVD) | ||
474 | |||
475 | #define PPP_CFG_MDP_Y_CBCR_H2V1(dir) (PPP_##dir##_C2R_8BIT | \ | ||
476 | PPP_##dir##_C0G_8BIT | \ | ||
477 | PPP_##dir##_C1B_8BIT | \ | ||
478 | PPP_##dir##_C3A_8BIT | \ | ||
479 | PPP_##dir##_BPP_2BYTES | \ | ||
480 | PPP_##dir##_INTERLVD_2COMPONENTS | \ | ||
481 | PPP_##dir##_PACK_TIGHT | \ | ||
482 | PPP_##dir##_PACK_ALIGN_LSB | \ | ||
483 | PPP_##dir##_PLANE_PSEUDOPLNR) | ||
484 | |||
485 | #define PPP_CFG_MDP_Y_CRCB_H2V1(dir) PPP_CFG_MDP_Y_CBCR_H2V1(dir) | ||
486 | |||
487 | #define PPP_PACK_PATTERN_MDP_RGB_565 \ | ||
488 | MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8) | ||
489 | #define PPP_PACK_PATTERN_MDP_RGB_888 PPP_PACK_PATTERN_MDP_RGB_565 | ||
490 | #define PPP_PACK_PATTERN_MDP_XRGB_8888 \ | ||
491 | MDP_GET_PACK_PATTERN(CLR_B, CLR_G, CLR_R, CLR_ALPHA, 8) | ||
492 | #define PPP_PACK_PATTERN_MDP_ARGB_8888 PPP_PACK_PATTERN_MDP_XRGB_8888 | ||
493 | #define PPP_PACK_PATTERN_MDP_RGBA_8888 \ | ||
494 | MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8) | ||
495 | #define PPP_PACK_PATTERN_MDP_BGRA_8888 \ | ||
496 | MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8) | ||
497 | #define PPP_PACK_PATTERN_MDP_RGBX_8888 \ | ||
498 | MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8) | ||
499 | #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 \ | ||
500 | MDP_GET_PACK_PATTERN(0, 0, CLR_CB, CLR_CR, 8) | ||
501 | #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V2 PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 | ||
502 | #define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1 \ | ||
503 | MDP_GET_PACK_PATTERN(0, 0, CLR_CR, CLR_CB, 8) | ||
504 | #define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V2 PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1 | ||
505 | #define PPP_PACK_PATTERN_MDP_YCRYCB_H2V1 \ | ||
506 | MDP_GET_PACK_PATTERN(CLR_Y, CLR_R, CLR_Y, CLR_B, 8) | ||
507 | |||
508 | #define PPP_CHROMA_SAMP_MDP_RGB_565(dir) PPP_OP_##dir##_CHROMA_RGB | ||
509 | #define PPP_CHROMA_SAMP_MDP_RGB_888(dir) PPP_OP_##dir##_CHROMA_RGB | ||
510 | #define PPP_CHROMA_SAMP_MDP_XRGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB | ||
511 | #define PPP_CHROMA_SAMP_MDP_ARGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB | ||
512 | #define PPP_CHROMA_SAMP_MDP_RGBA_8888(dir) PPP_OP_##dir##_CHROMA_RGB | ||
513 | #define PPP_CHROMA_SAMP_MDP_BGRA_8888(dir) PPP_OP_##dir##_CHROMA_RGB | ||
514 | #define PPP_CHROMA_SAMP_MDP_RGBX_8888(dir) PPP_OP_##dir##_CHROMA_RGB | ||
515 | #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 | ||
516 | #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V2(dir) PPP_OP_##dir##_CHROMA_420 | ||
517 | #define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 | ||
518 | #define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V2(dir) PPP_OP_##dir##_CHROMA_420 | ||
519 | #define PPP_CHROMA_SAMP_MDP_YCRYCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 | ||
520 | |||
521 | /* Helpful array generation macros */ | ||
522 | #define PPP_ARRAY0(name) \ | ||
523 | [MDP_RGB_565] = PPP_##name##_MDP_RGB_565,\ | ||
524 | [MDP_RGB_888] = PPP_##name##_MDP_RGB_888,\ | ||
525 | [MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888,\ | ||
526 | [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888,\ | ||
527 | [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888,\ | ||
528 | [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888,\ | ||
529 | [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888,\ | ||
530 | [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1,\ | ||
531 | [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2,\ | ||
532 | [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1,\ | ||
533 | [MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2,\ | ||
534 | [MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1 | ||
535 | |||
536 | #define PPP_ARRAY1(name, dir) \ | ||
537 | [MDP_RGB_565] = PPP_##name##_MDP_RGB_565(dir),\ | ||
538 | [MDP_RGB_888] = PPP_##name##_MDP_RGB_888(dir),\ | ||
539 | [MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888(dir),\ | ||
540 | [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888(dir),\ | ||
541 | [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888(dir),\ | ||
542 | [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888(dir),\ | ||
543 | [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888(dir),\ | ||
544 | [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1(dir),\ | ||
545 | [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2(dir),\ | ||
546 | [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1(dir),\ | ||
547 | [MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2(dir),\ | ||
548 | [MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1(dir) | ||
549 | |||
550 | #define IS_YCRCB(img) ((img == MDP_Y_CRCB_H2V2) | (img == MDP_Y_CBCR_H2V2) | \ | ||
551 | (img == MDP_Y_CRCB_H2V1) | (img == MDP_Y_CBCR_H2V1) | \ | ||
552 | (img == MDP_YCRYCB_H2V1)) | ||
553 | #define IS_RGB(img) ((img == MDP_RGB_565) | (img == MDP_RGB_888) | \ | ||
554 | (img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \ | ||
555 | (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888) | \ | ||
556 | (img == MDP_RGBX_8888)) | ||
557 | #define HAS_ALPHA(img) ((img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \ | ||
558 | (img == MDP_BGRA_8888)) | ||
559 | |||
560 | #define IS_PSEUDOPLNR(img) ((img == MDP_Y_CRCB_H2V2) | \ | ||
561 | (img == MDP_Y_CBCR_H2V2) | \ | ||
562 | (img == MDP_Y_CRCB_H2V1) | \ | ||
563 | (img == MDP_Y_CBCR_H2V1)) | ||
564 | |||
565 | /* Mappings from addr to purpose */ | ||
566 | #define PPP_ADDR_SRC_ROI MDP_FULL_BYPASS_WORD2 | ||
567 | #define PPP_ADDR_SRC0 MDP_FULL_BYPASS_WORD3 | ||
568 | #define PPP_ADDR_SRC1 MDP_FULL_BYPASS_WORD4 | ||
569 | #define PPP_ADDR_SRC_YSTRIDE MDP_FULL_BYPASS_WORD7 | ||
570 | #define PPP_ADDR_SRC_CFG MDP_FULL_BYPASS_WORD9 | ||
571 | #define PPP_ADDR_SRC_PACK_PATTERN MDP_FULL_BYPASS_WORD10 | ||
572 | #define PPP_ADDR_OPERATION MDP_FULL_BYPASS_WORD14 | ||
573 | #define PPP_ADDR_PHASEX_INIT MDP_FULL_BYPASS_WORD15 | ||
574 | #define PPP_ADDR_PHASEY_INIT MDP_FULL_BYPASS_WORD16 | ||
575 | #define PPP_ADDR_PHASEX_STEP MDP_FULL_BYPASS_WORD17 | ||
576 | #define PPP_ADDR_PHASEY_STEP MDP_FULL_BYPASS_WORD18 | ||
577 | #define PPP_ADDR_ALPHA_TRANSP MDP_FULL_BYPASS_WORD19 | ||
578 | #define PPP_ADDR_DST_CFG MDP_FULL_BYPASS_WORD20 | ||
579 | #define PPP_ADDR_DST_PACK_PATTERN MDP_FULL_BYPASS_WORD21 | ||
580 | #define PPP_ADDR_DST_ROI MDP_FULL_BYPASS_WORD25 | ||
581 | #define PPP_ADDR_DST0 MDP_FULL_BYPASS_WORD26 | ||
582 | #define PPP_ADDR_DST1 MDP_FULL_BYPASS_WORD27 | ||
583 | #define PPP_ADDR_DST_YSTRIDE MDP_FULL_BYPASS_WORD30 | ||
584 | #define PPP_ADDR_EDGE MDP_FULL_BYPASS_WORD46 | ||
585 | #define PPP_ADDR_BG0 MDP_FULL_BYPASS_WORD48 | ||
586 | #define PPP_ADDR_BG1 MDP_FULL_BYPASS_WORD49 | ||
587 | #define PPP_ADDR_BG_YSTRIDE MDP_FULL_BYPASS_WORD51 | ||
588 | #define PPP_ADDR_BG_CFG MDP_FULL_BYPASS_WORD53 | ||
589 | #define PPP_ADDR_BG_PACK_PATTERN MDP_FULL_BYPASS_WORD54 | ||
590 | |||
591 | /* MDP_DMA_CONFIG / MDP_FULL_BYPASS_WORD32 */ | ||
592 | #define DMA_DSTC0G_6BITS (1<<1) | ||
593 | #define DMA_DSTC1B_6BITS (1<<3) | ||
594 | #define DMA_DSTC2R_6BITS (1<<5) | ||
595 | #define DMA_DSTC0G_5BITS (1<<0) | ||
596 | #define DMA_DSTC1B_5BITS (1<<2) | ||
597 | #define DMA_DSTC2R_5BITS (1<<4) | ||
598 | |||
599 | #define DMA_PACK_TIGHT (1<<6) | ||
600 | #define DMA_PACK_LOOSE 0 | ||
601 | #define DMA_PACK_ALIGN_LSB 0 | ||
602 | #define DMA_PACK_ALIGN_MSB (1<<7) | ||
603 | #define DMA_PACK_PATTERN_RGB \ | ||
604 | (MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 2)<<8) | ||
605 | |||
606 | #define DMA_OUT_SEL_AHB 0 | ||
607 | #define DMA_OUT_SEL_MDDI (1<<14) | ||
608 | #define DMA_AHBM_LCD_SEL_PRIMARY 0 | ||
609 | #define DMA_AHBM_LCD_SEL_SECONDARY (1<<15) | ||
610 | #define DMA_IBUF_C3ALPHA_EN (1<<16) | ||
611 | #define DMA_DITHER_EN (1<<17) | ||
612 | |||
613 | #define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0 | ||
614 | #define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY (1<<18) | ||
615 | #define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL (1<<19) | ||
616 | |||
617 | #define DMA_IBUF_FORMAT_RGB565 (1<<20) | ||
618 | #define DMA_IBUF_FORMAT_RGB888_OR_ARGB8888 0 | ||
619 | |||
620 | #define DMA_IBUF_NONCONTIGUOUS (1<<21) | ||
621 | |||
622 | /* MDDI REGISTER ? */ | ||
623 | #define MDDI_VDO_PACKET_DESC 0x5666 | ||
624 | #define MDDI_VDO_PACKET_PRIM 0xC3 | ||
625 | #define MDDI_VDO_PACKET_SECD 0xC0 | ||
626 | |||
627 | #endif | ||
diff --git a/drivers/video/fbdev/msm/mdp_ppp.c b/drivers/video/fbdev/msm/mdp_ppp.c deleted file mode 100644 index be6079cdfbb6..000000000000 --- a/drivers/video/fbdev/msm/mdp_ppp.c +++ /dev/null | |||
@@ -1,731 +0,0 @@ | |||
1 | /* drivers/video/msm/mdp_ppp.c | ||
2 | * | ||
3 | * Copyright (C) 2007 QUALCOMM Incorporated | ||
4 | * Copyright (C) 2007 Google Incorporated | ||
5 | * | ||
6 | * This software is licensed under the terms of the GNU General Public | ||
7 | * License version 2, as published by the Free Software Foundation, and | ||
8 | * may be copied, distributed, and modified under those terms. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | #include <linux/fb.h> | ||
16 | #include <linux/file.h> | ||
17 | #include <linux/delay.h> | ||
18 | #include <linux/msm_mdp.h> | ||
19 | #include <linux/platform_data/video-msm_fb.h> | ||
20 | |||
21 | #include "mdp_hw.h" | ||
22 | #include "mdp_scale_tables.h" | ||
23 | |||
24 | #define DLOG(x...) do {} while (0) | ||
25 | |||
26 | #define MDP_DOWNSCALE_BLUR (MDP_DOWNSCALE_MAX + 1) | ||
27 | static int downscale_y_table = MDP_DOWNSCALE_MAX; | ||
28 | static int downscale_x_table = MDP_DOWNSCALE_MAX; | ||
29 | |||
30 | struct mdp_regs { | ||
31 | uint32_t src0; | ||
32 | uint32_t src1; | ||
33 | uint32_t dst0; | ||
34 | uint32_t dst1; | ||
35 | uint32_t src_cfg; | ||
36 | uint32_t dst_cfg; | ||
37 | uint32_t src_pack; | ||
38 | uint32_t dst_pack; | ||
39 | uint32_t src_rect; | ||
40 | uint32_t dst_rect; | ||
41 | uint32_t src_ystride; | ||
42 | uint32_t dst_ystride; | ||
43 | uint32_t op; | ||
44 | uint32_t src_bpp; | ||
45 | uint32_t dst_bpp; | ||
46 | uint32_t edge; | ||
47 | uint32_t phasex_init; | ||
48 | uint32_t phasey_init; | ||
49 | uint32_t phasex_step; | ||
50 | uint32_t phasey_step; | ||
51 | }; | ||
52 | |||
53 | static uint32_t pack_pattern[] = { | ||
54 | PPP_ARRAY0(PACK_PATTERN) | ||
55 | }; | ||
56 | |||
57 | static uint32_t src_img_cfg[] = { | ||
58 | PPP_ARRAY1(CFG, SRC) | ||
59 | }; | ||
60 | |||
61 | static uint32_t dst_img_cfg[] = { | ||
62 | PPP_ARRAY1(CFG, DST) | ||
63 | }; | ||
64 | |||
65 | static uint32_t bytes_per_pixel[] = { | ||
66 | [MDP_RGB_565] = 2, | ||
67 | [MDP_RGB_888] = 3, | ||
68 | [MDP_XRGB_8888] = 4, | ||
69 | [MDP_ARGB_8888] = 4, | ||
70 | [MDP_RGBA_8888] = 4, | ||
71 | [MDP_BGRA_8888] = 4, | ||
72 | [MDP_RGBX_8888] = 4, | ||
73 | [MDP_Y_CBCR_H2V1] = 1, | ||
74 | [MDP_Y_CBCR_H2V2] = 1, | ||
75 | [MDP_Y_CRCB_H2V1] = 1, | ||
76 | [MDP_Y_CRCB_H2V2] = 1, | ||
77 | [MDP_YCRYCB_H2V1] = 2 | ||
78 | }; | ||
79 | |||
80 | static uint32_t dst_op_chroma[] = { | ||
81 | PPP_ARRAY1(CHROMA_SAMP, DST) | ||
82 | }; | ||
83 | |||
84 | static uint32_t src_op_chroma[] = { | ||
85 | PPP_ARRAY1(CHROMA_SAMP, SRC) | ||
86 | }; | ||
87 | |||
88 | static uint32_t bg_op_chroma[] = { | ||
89 | PPP_ARRAY1(CHROMA_SAMP, BG) | ||
90 | }; | ||
91 | |||
92 | static void rotate_dst_addr_x(struct mdp_blit_req *req, struct mdp_regs *regs) | ||
93 | { | ||
94 | regs->dst0 += (req->dst_rect.w - | ||
95 | min((uint32_t)16, req->dst_rect.w)) * regs->dst_bpp; | ||
96 | regs->dst1 += (req->dst_rect.w - | ||
97 | min((uint32_t)16, req->dst_rect.w)) * regs->dst_bpp; | ||
98 | } | ||
99 | |||
100 | static void rotate_dst_addr_y(struct mdp_blit_req *req, struct mdp_regs *regs) | ||
101 | { | ||
102 | regs->dst0 += (req->dst_rect.h - | ||
103 | min((uint32_t)16, req->dst_rect.h)) * | ||
104 | regs->dst_ystride; | ||
105 | regs->dst1 += (req->dst_rect.h - | ||
106 | min((uint32_t)16, req->dst_rect.h)) * | ||
107 | regs->dst_ystride; | ||
108 | } | ||
109 | |||
110 | static void blit_rotate(struct mdp_blit_req *req, | ||
111 | struct mdp_regs *regs) | ||
112 | { | ||
113 | if (req->flags == MDP_ROT_NOP) | ||
114 | return; | ||
115 | |||
116 | regs->op |= PPP_OP_ROT_ON; | ||
117 | if ((req->flags & MDP_ROT_90 || req->flags & MDP_FLIP_LR) && | ||
118 | !(req->flags & MDP_ROT_90 && req->flags & MDP_FLIP_LR)) | ||
119 | rotate_dst_addr_x(req, regs); | ||
120 | if (req->flags & MDP_ROT_90) | ||
121 | regs->op |= PPP_OP_ROT_90; | ||
122 | if (req->flags & MDP_FLIP_UD) { | ||
123 | regs->op |= PPP_OP_FLIP_UD; | ||
124 | rotate_dst_addr_y(req, regs); | ||
125 | } | ||
126 | if (req->flags & MDP_FLIP_LR) | ||
127 | regs->op |= PPP_OP_FLIP_LR; | ||
128 | } | ||
129 | |||
130 | static void blit_convert(struct mdp_blit_req *req, struct mdp_regs *regs) | ||
131 | { | ||
132 | if (req->src.format == req->dst.format) | ||
133 | return; | ||
134 | if (IS_RGB(req->src.format) && IS_YCRCB(req->dst.format)) { | ||
135 | regs->op |= PPP_OP_CONVERT_RGB2YCBCR | PPP_OP_CONVERT_ON; | ||
136 | } else if (IS_YCRCB(req->src.format) && IS_RGB(req->dst.format)) { | ||
137 | regs->op |= PPP_OP_CONVERT_YCBCR2RGB | PPP_OP_CONVERT_ON; | ||
138 | if (req->dst.format == MDP_RGB_565) | ||
139 | regs->op |= PPP_OP_CONVERT_MATRIX_SECONDARY; | ||
140 | } | ||
141 | } | ||
142 | |||
143 | #define GET_BIT_RANGE(value, high, low) \ | ||
144 | (((1 << (high - low + 1)) - 1) & (value >> low)) | ||
145 | static uint32_t transp_convert(struct mdp_blit_req *req) | ||
146 | { | ||
147 | uint32_t transp = 0; | ||
148 | if (req->src.format == MDP_RGB_565) { | ||
149 | /* pad each value to 8 bits by copying the high bits into the | ||
150 | * low end, convert RGB to RBG by switching low 2 components */ | ||
151 | transp |= ((GET_BIT_RANGE(req->transp_mask, 15, 11) << 3) | | ||
152 | (GET_BIT_RANGE(req->transp_mask, 15, 13))) << 16; | ||
153 | |||
154 | transp |= ((GET_BIT_RANGE(req->transp_mask, 4, 0) << 3) | | ||
155 | (GET_BIT_RANGE(req->transp_mask, 4, 2))) << 8; | ||
156 | |||
157 | transp |= (GET_BIT_RANGE(req->transp_mask, 10, 5) << 2) | | ||
158 | (GET_BIT_RANGE(req->transp_mask, 10, 9)); | ||
159 | } else { | ||
160 | /* convert RGB to RBG */ | ||
161 | transp |= (GET_BIT_RANGE(req->transp_mask, 15, 8)) | | ||
162 | (GET_BIT_RANGE(req->transp_mask, 23, 16) << 16) | | ||
163 | (GET_BIT_RANGE(req->transp_mask, 7, 0) << 8); | ||
164 | } | ||
165 | return transp; | ||
166 | } | ||
167 | #undef GET_BIT_RANGE | ||
168 | |||
169 | static void blit_blend(struct mdp_blit_req *req, struct mdp_regs *regs) | ||
170 | { | ||
171 | /* TRANSP BLEND */ | ||
172 | if (req->transp_mask != MDP_TRANSP_NOP) { | ||
173 | req->transp_mask = transp_convert(req); | ||
174 | if (req->alpha != MDP_ALPHA_NOP) { | ||
175 | /* use blended transparancy mode | ||
176 | * pixel = (src == transp) ? dst : blend | ||
177 | * blend is combo of blend_eq_sel and | ||
178 | * blend_alpha_sel */ | ||
179 | regs->op |= PPP_OP_ROT_ON | PPP_OP_BLEND_ON | | ||
180 | PPP_OP_BLEND_ALPHA_BLEND_NORMAL | | ||
181 | PPP_OP_BLEND_CONSTANT_ALPHA | | ||
182 | PPP_BLEND_ALPHA_TRANSP; | ||
183 | } else { | ||
184 | /* simple transparancy mode | ||
185 | * pixel = (src == transp) ? dst : src */ | ||
186 | regs->op |= PPP_OP_ROT_ON | PPP_OP_BLEND_ON | | ||
187 | PPP_OP_BLEND_SRCPIXEL_TRANSP; | ||
188 | } | ||
189 | } | ||
190 | |||
191 | req->alpha &= 0xff; | ||
192 | /* ALPHA BLEND */ | ||
193 | if (HAS_ALPHA(req->src.format)) { | ||
194 | regs->op |= PPP_OP_ROT_ON | PPP_OP_BLEND_ON | | ||
195 | PPP_OP_BLEND_SRCPIXEL_ALPHA; | ||
196 | } else if (req->alpha < MDP_ALPHA_NOP) { | ||
197 | /* just blend by alpha */ | ||
198 | regs->op |= PPP_OP_ROT_ON | PPP_OP_BLEND_ON | | ||
199 | PPP_OP_BLEND_ALPHA_BLEND_NORMAL | | ||
200 | PPP_OP_BLEND_CONSTANT_ALPHA; | ||
201 | } | ||
202 | |||
203 | regs->op |= bg_op_chroma[req->dst.format]; | ||
204 | } | ||
205 | |||
206 | #define ONE_HALF (1LL << 32) | ||
207 | #define ONE (1LL << 33) | ||
208 | #define TWO (2LL << 33) | ||
209 | #define THREE (3LL << 33) | ||
210 | #define FRAC_MASK (ONE - 1) | ||
211 | #define INT_MASK (~FRAC_MASK) | ||
212 | |||
213 | static int scale_params(uint32_t dim_in, uint32_t dim_out, uint32_t origin, | ||
214 | uint32_t *phase_init, uint32_t *phase_step) | ||
215 | { | ||
216 | /* to improve precicsion calculations are done in U31.33 and converted | ||
217 | * to U3.29 at the end */ | ||
218 | int64_t k1, k2, k3, k4, tmp; | ||
219 | uint64_t n, d, os, os_p, od, od_p, oreq; | ||
220 | unsigned rpa = 0; | ||
221 | int64_t ip64, delta; | ||
222 | |||
223 | if (dim_out % 3 == 0) | ||
224 | rpa = !(dim_in % (dim_out / 3)); | ||
225 | |||
226 | n = ((uint64_t)dim_out) << 34; | ||
227 | d = dim_in; | ||
228 | if (!d) | ||
229 | return -1; | ||
230 | do_div(n, d); | ||
231 | k3 = (n + 1) >> 1; | ||
232 | if ((k3 >> 4) < (1LL << 27) || (k3 >> 4) > (1LL << 31)) { | ||
233 | DLOG("crap bad scale\n"); | ||
234 | return -1; | ||
235 | } | ||
236 | n = ((uint64_t)dim_in) << 34; | ||
237 | d = (uint64_t)dim_out; | ||
238 | if (!d) | ||
239 | return -1; | ||
240 | do_div(n, d); | ||
241 | k1 = (n + 1) >> 1; | ||
242 | k2 = (k1 - ONE) >> 1; | ||
243 | |||
244 | *phase_init = (int)(k2 >> 4); | ||
245 | k4 = (k3 - ONE) >> 1; | ||
246 | |||
247 | if (rpa) { | ||
248 | os = ((uint64_t)origin << 33) - ONE_HALF; | ||
249 | tmp = (dim_out * os) + ONE_HALF; | ||
250 | if (!dim_in) | ||
251 | return -1; | ||
252 | do_div(tmp, dim_in); | ||
253 | od = tmp - ONE_HALF; | ||
254 | } else { | ||
255 | os = ((uint64_t)origin << 1) - 1; | ||
256 | od = (((k3 * os) >> 1) + k4); | ||
257 | } | ||
258 | |||
259 | od_p = od & INT_MASK; | ||
260 | if (od_p != od) | ||
261 | od_p += ONE; | ||
262 | |||
263 | if (rpa) { | ||
264 | tmp = (dim_in * od_p) + ONE_HALF; | ||
265 | if (!dim_in) | ||
266 | return -1; | ||
267 | do_div(tmp, dim_in); | ||
268 | os_p = tmp - ONE_HALF; | ||
269 | } else { | ||
270 | os_p = ((k1 * (od_p >> 33)) + k2); | ||
271 | } | ||
272 | |||
273 | oreq = (os_p & INT_MASK) - ONE; | ||
274 | |||
275 | ip64 = os_p - oreq; | ||
276 | delta = ((int64_t)(origin) << 33) - oreq; | ||
277 | ip64 -= delta; | ||
278 | /* limit to valid range before the left shift */ | ||
279 | delta = (ip64 & (1LL << 63)) ? 4 : -4; | ||
280 | delta <<= 33; | ||
281 | while (abs((int)(ip64 >> 33)) > 4) | ||
282 | ip64 += delta; | ||
283 | *phase_init = (int)(ip64 >> 4); | ||
284 | *phase_step = (uint32_t)(k1 >> 4); | ||
285 | return 0; | ||
286 | } | ||
287 | |||
288 | static void load_scale_table(const struct mdp_info *mdp, | ||
289 | struct mdp_table_entry *table, int len) | ||
290 | { | ||
291 | int i; | ||
292 | for (i = 0; i < len; i++) | ||
293 | mdp_writel(mdp, table[i].val, table[i].reg); | ||
294 | } | ||
295 | |||
296 | enum { | ||
297 | IMG_LEFT, | ||
298 | IMG_RIGHT, | ||
299 | IMG_TOP, | ||
300 | IMG_BOTTOM, | ||
301 | }; | ||
302 | |||
303 | static void get_edge_info(uint32_t src, uint32_t src_coord, uint32_t dst, | ||
304 | uint32_t *interp1, uint32_t *interp2, | ||
305 | uint32_t *repeat1, uint32_t *repeat2) { | ||
306 | if (src > 3 * dst) { | ||
307 | *interp1 = 0; | ||
308 | *interp2 = src - 1; | ||
309 | *repeat1 = 0; | ||
310 | *repeat2 = 0; | ||
311 | } else if (src == 3 * dst) { | ||
312 | *interp1 = 0; | ||
313 | *interp2 = src; | ||
314 | *repeat1 = 0; | ||
315 | *repeat2 = 1; | ||
316 | } else if (src > dst && src < 3 * dst) { | ||
317 | *interp1 = -1; | ||
318 | *interp2 = src; | ||
319 | *repeat1 = 1; | ||
320 | *repeat2 = 1; | ||
321 | } else if (src == dst) { | ||
322 | *interp1 = -1; | ||
323 | *interp2 = src + 1; | ||
324 | *repeat1 = 1; | ||
325 | *repeat2 = 2; | ||
326 | } else { | ||
327 | *interp1 = -2; | ||
328 | *interp2 = src + 1; | ||
329 | *repeat1 = 2; | ||
330 | *repeat2 = 2; | ||
331 | } | ||
332 | *interp1 += src_coord; | ||
333 | *interp2 += src_coord; | ||
334 | } | ||
335 | |||
336 | static int get_edge_cond(struct mdp_blit_req *req, struct mdp_regs *regs) | ||
337 | { | ||
338 | int32_t luma_interp[4]; | ||
339 | int32_t luma_repeat[4]; | ||
340 | int32_t chroma_interp[4]; | ||
341 | int32_t chroma_bound[4]; | ||
342 | int32_t chroma_repeat[4]; | ||
343 | uint32_t dst_w, dst_h; | ||
344 | |||
345 | memset(&luma_interp, 0, sizeof(int32_t) * 4); | ||
346 | memset(&luma_repeat, 0, sizeof(int32_t) * 4); | ||
347 | memset(&chroma_interp, 0, sizeof(int32_t) * 4); | ||
348 | memset(&chroma_bound, 0, sizeof(int32_t) * 4); | ||
349 | memset(&chroma_repeat, 0, sizeof(int32_t) * 4); | ||
350 | regs->edge = 0; | ||
351 | |||
352 | if (req->flags & MDP_ROT_90) { | ||
353 | dst_w = req->dst_rect.h; | ||
354 | dst_h = req->dst_rect.w; | ||
355 | } else { | ||
356 | dst_w = req->dst_rect.w; | ||
357 | dst_h = req->dst_rect.h; | ||
358 | } | ||
359 | |||
360 | if (regs->op & (PPP_OP_SCALE_Y_ON | PPP_OP_SCALE_X_ON)) { | ||
361 | get_edge_info(req->src_rect.h, req->src_rect.y, dst_h, | ||
362 | &luma_interp[IMG_TOP], &luma_interp[IMG_BOTTOM], | ||
363 | &luma_repeat[IMG_TOP], &luma_repeat[IMG_BOTTOM]); | ||
364 | get_edge_info(req->src_rect.w, req->src_rect.x, dst_w, | ||
365 | &luma_interp[IMG_LEFT], &luma_interp[IMG_RIGHT], | ||
366 | &luma_repeat[IMG_LEFT], &luma_repeat[IMG_RIGHT]); | ||
367 | } else { | ||
368 | luma_interp[IMG_LEFT] = req->src_rect.x; | ||
369 | luma_interp[IMG_RIGHT] = req->src_rect.x + req->src_rect.w - 1; | ||
370 | luma_interp[IMG_TOP] = req->src_rect.y; | ||
371 | luma_interp[IMG_BOTTOM] = req->src_rect.y + req->src_rect.h - 1; | ||
372 | luma_repeat[IMG_LEFT] = 0; | ||
373 | luma_repeat[IMG_TOP] = 0; | ||
374 | luma_repeat[IMG_RIGHT] = 0; | ||
375 | luma_repeat[IMG_BOTTOM] = 0; | ||
376 | } | ||
377 | |||
378 | chroma_interp[IMG_LEFT] = luma_interp[IMG_LEFT]; | ||
379 | chroma_interp[IMG_RIGHT] = luma_interp[IMG_RIGHT]; | ||
380 | chroma_interp[IMG_TOP] = luma_interp[IMG_TOP]; | ||
381 | chroma_interp[IMG_BOTTOM] = luma_interp[IMG_BOTTOM]; | ||
382 | |||
383 | chroma_bound[IMG_LEFT] = req->src_rect.x; | ||
384 | chroma_bound[IMG_RIGHT] = req->src_rect.x + req->src_rect.w - 1; | ||
385 | chroma_bound[IMG_TOP] = req->src_rect.y; | ||
386 | chroma_bound[IMG_BOTTOM] = req->src_rect.y + req->src_rect.h - 1; | ||
387 | |||
388 | if (IS_YCRCB(req->src.format)) { | ||
389 | chroma_interp[IMG_LEFT] = chroma_interp[IMG_LEFT] >> 1; | ||
390 | chroma_interp[IMG_RIGHT] = (chroma_interp[IMG_RIGHT] + 1) >> 1; | ||
391 | |||
392 | chroma_bound[IMG_LEFT] = chroma_bound[IMG_LEFT] >> 1; | ||
393 | chroma_bound[IMG_RIGHT] = chroma_bound[IMG_RIGHT] >> 1; | ||
394 | } | ||
395 | |||
396 | if (req->src.format == MDP_Y_CBCR_H2V2 || | ||
397 | req->src.format == MDP_Y_CRCB_H2V2) { | ||
398 | chroma_interp[IMG_TOP] = (chroma_interp[IMG_TOP] - 1) >> 1; | ||
399 | chroma_interp[IMG_BOTTOM] = (chroma_interp[IMG_BOTTOM] + 1) | ||
400 | >> 1; | ||
401 | chroma_bound[IMG_TOP] = (chroma_bound[IMG_TOP] + 1) >> 1; | ||
402 | chroma_bound[IMG_BOTTOM] = chroma_bound[IMG_BOTTOM] >> 1; | ||
403 | } | ||
404 | |||
405 | chroma_repeat[IMG_LEFT] = chroma_bound[IMG_LEFT] - | ||
406 | chroma_interp[IMG_LEFT]; | ||
407 | chroma_repeat[IMG_RIGHT] = chroma_interp[IMG_RIGHT] - | ||
408 | chroma_bound[IMG_RIGHT]; | ||
409 | chroma_repeat[IMG_TOP] = chroma_bound[IMG_TOP] - | ||
410 | chroma_interp[IMG_TOP]; | ||
411 | chroma_repeat[IMG_BOTTOM] = chroma_interp[IMG_BOTTOM] - | ||
412 | chroma_bound[IMG_BOTTOM]; | ||
413 | |||
414 | if (chroma_repeat[IMG_LEFT] < 0 || chroma_repeat[IMG_LEFT] > 3 || | ||
415 | chroma_repeat[IMG_RIGHT] < 0 || chroma_repeat[IMG_RIGHT] > 3 || | ||
416 | chroma_repeat[IMG_TOP] < 0 || chroma_repeat[IMG_TOP] > 3 || | ||
417 | chroma_repeat[IMG_BOTTOM] < 0 || chroma_repeat[IMG_BOTTOM] > 3 || | ||
418 | luma_repeat[IMG_LEFT] < 0 || luma_repeat[IMG_LEFT] > 3 || | ||
419 | luma_repeat[IMG_RIGHT] < 0 || luma_repeat[IMG_RIGHT] > 3 || | ||
420 | luma_repeat[IMG_TOP] < 0 || luma_repeat[IMG_TOP] > 3 || | ||
421 | luma_repeat[IMG_BOTTOM] < 0 || luma_repeat[IMG_BOTTOM] > 3) | ||
422 | return -1; | ||
423 | |||
424 | regs->edge |= (chroma_repeat[IMG_LEFT] & 3) << MDP_LEFT_CHROMA; | ||
425 | regs->edge |= (chroma_repeat[IMG_RIGHT] & 3) << MDP_RIGHT_CHROMA; | ||
426 | regs->edge |= (chroma_repeat[IMG_TOP] & 3) << MDP_TOP_CHROMA; | ||
427 | regs->edge |= (chroma_repeat[IMG_BOTTOM] & 3) << MDP_BOTTOM_CHROMA; | ||
428 | regs->edge |= (luma_repeat[IMG_LEFT] & 3) << MDP_LEFT_LUMA; | ||
429 | regs->edge |= (luma_repeat[IMG_RIGHT] & 3) << MDP_RIGHT_LUMA; | ||
430 | regs->edge |= (luma_repeat[IMG_TOP] & 3) << MDP_TOP_LUMA; | ||
431 | regs->edge |= (luma_repeat[IMG_BOTTOM] & 3) << MDP_BOTTOM_LUMA; | ||
432 | return 0; | ||
433 | } | ||
434 | |||
435 | static int blit_scale(const struct mdp_info *mdp, struct mdp_blit_req *req, | ||
436 | struct mdp_regs *regs) | ||
437 | { | ||
438 | uint32_t phase_init_x, phase_init_y, phase_step_x, phase_step_y; | ||
439 | uint32_t scale_factor_x, scale_factor_y; | ||
440 | uint32_t downscale; | ||
441 | uint32_t dst_w, dst_h; | ||
442 | |||
443 | if (req->flags & MDP_ROT_90) { | ||
444 | dst_w = req->dst_rect.h; | ||
445 | dst_h = req->dst_rect.w; | ||
446 | } else { | ||
447 | dst_w = req->dst_rect.w; | ||
448 | dst_h = req->dst_rect.h; | ||
449 | } | ||
450 | if ((req->src_rect.w == dst_w) && (req->src_rect.h == dst_h) && | ||
451 | !(req->flags & MDP_BLUR)) { | ||
452 | regs->phasex_init = 0; | ||
453 | regs->phasey_init = 0; | ||
454 | regs->phasex_step = 0; | ||
455 | regs->phasey_step = 0; | ||
456 | return 0; | ||
457 | } | ||
458 | |||
459 | if (scale_params(req->src_rect.w, dst_w, 1, &phase_init_x, | ||
460 | &phase_step_x) || | ||
461 | scale_params(req->src_rect.h, dst_h, 1, &phase_init_y, | ||
462 | &phase_step_y)) | ||
463 | return -1; | ||
464 | |||
465 | scale_factor_x = (dst_w * 10) / req->src_rect.w; | ||
466 | scale_factor_y = (dst_h * 10) / req->src_rect.h; | ||
467 | |||
468 | if (scale_factor_x > 8) | ||
469 | downscale = MDP_DOWNSCALE_PT8TO1; | ||
470 | else if (scale_factor_x > 6) | ||
471 | downscale = MDP_DOWNSCALE_PT6TOPT8; | ||
472 | else if (scale_factor_x > 4) | ||
473 | downscale = MDP_DOWNSCALE_PT4TOPT6; | ||
474 | else | ||
475 | downscale = MDP_DOWNSCALE_PT2TOPT4; | ||
476 | if (downscale != downscale_x_table) { | ||
477 | load_scale_table(mdp, mdp_downscale_x_table[downscale], 64); | ||
478 | downscale_x_table = downscale; | ||
479 | } | ||
480 | |||
481 | if (scale_factor_y > 8) | ||
482 | downscale = MDP_DOWNSCALE_PT8TO1; | ||
483 | else if (scale_factor_y > 6) | ||
484 | downscale = MDP_DOWNSCALE_PT6TOPT8; | ||
485 | else if (scale_factor_y > 4) | ||
486 | downscale = MDP_DOWNSCALE_PT4TOPT6; | ||
487 | else | ||
488 | downscale = MDP_DOWNSCALE_PT2TOPT4; | ||
489 | if (downscale != downscale_y_table) { | ||
490 | load_scale_table(mdp, mdp_downscale_y_table[downscale], 64); | ||
491 | downscale_y_table = downscale; | ||
492 | } | ||
493 | |||
494 | regs->phasex_init = phase_init_x; | ||
495 | regs->phasey_init = phase_init_y; | ||
496 | regs->phasex_step = phase_step_x; | ||
497 | regs->phasey_step = phase_step_y; | ||
498 | regs->op |= (PPP_OP_SCALE_Y_ON | PPP_OP_SCALE_X_ON); | ||
499 | return 0; | ||
500 | |||
501 | } | ||
502 | |||
503 | static void blit_blur(const struct mdp_info *mdp, struct mdp_blit_req *req, | ||
504 | struct mdp_regs *regs) | ||
505 | { | ||
506 | if (!(req->flags & MDP_BLUR)) | ||
507 | return; | ||
508 | |||
509 | if (!(downscale_x_table == MDP_DOWNSCALE_BLUR && | ||
510 | downscale_y_table == MDP_DOWNSCALE_BLUR)) { | ||
511 | load_scale_table(mdp, mdp_gaussian_blur_table, 128); | ||
512 | downscale_x_table = MDP_DOWNSCALE_BLUR; | ||
513 | downscale_y_table = MDP_DOWNSCALE_BLUR; | ||
514 | } | ||
515 | |||
516 | regs->op |= (PPP_OP_SCALE_Y_ON | PPP_OP_SCALE_X_ON); | ||
517 | } | ||
518 | |||
519 | |||
520 | #define IMG_LEN(rect_h, w, rect_w, bpp) (((rect_h) * w) * bpp) | ||
521 | |||
522 | #define Y_TO_CRCB_RATIO(format) \ | ||
523 | ((format == MDP_Y_CBCR_H2V2 || format == MDP_Y_CRCB_H2V2) ? 2 :\ | ||
524 | (format == MDP_Y_CBCR_H2V1 || format == MDP_Y_CRCB_H2V1) ? 1 : 1) | ||
525 | |||
526 | static void get_len(struct mdp_img *img, struct mdp_rect *rect, uint32_t bpp, | ||
527 | uint32_t *len0, uint32_t *len1) | ||
528 | { | ||
529 | *len0 = IMG_LEN(rect->h, img->width, rect->w, bpp); | ||
530 | if (IS_PSEUDOPLNR(img->format)) | ||
531 | *len1 = *len0/Y_TO_CRCB_RATIO(img->format); | ||
532 | else | ||
533 | *len1 = 0; | ||
534 | } | ||
535 | |||
536 | static int valid_src_dst(unsigned long src_start, unsigned long src_len, | ||
537 | unsigned long dst_start, unsigned long dst_len, | ||
538 | struct mdp_blit_req *req, struct mdp_regs *regs) | ||
539 | { | ||
540 | unsigned long src_min_ok = src_start; | ||
541 | unsigned long src_max_ok = src_start + src_len; | ||
542 | unsigned long dst_min_ok = dst_start; | ||
543 | unsigned long dst_max_ok = dst_start + dst_len; | ||
544 | uint32_t src0_len, src1_len, dst0_len, dst1_len; | ||
545 | get_len(&req->src, &req->src_rect, regs->src_bpp, &src0_len, | ||
546 | &src1_len); | ||
547 | get_len(&req->dst, &req->dst_rect, regs->dst_bpp, &dst0_len, | ||
548 | &dst1_len); | ||
549 | |||
550 | if (regs->src0 < src_min_ok || regs->src0 > src_max_ok || | ||
551 | regs->src0 + src0_len > src_max_ok) { | ||
552 | DLOG("invalid_src %x %x %lx %lx\n", regs->src0, | ||
553 | src0_len, src_min_ok, src_max_ok); | ||
554 | return 0; | ||
555 | } | ||
556 | if (regs->src_cfg & PPP_SRC_PLANE_PSEUDOPLNR) { | ||
557 | if (regs->src1 < src_min_ok || regs->src1 > src_max_ok || | ||
558 | regs->src1 + src1_len > src_max_ok) { | ||
559 | DLOG("invalid_src1"); | ||
560 | return 0; | ||
561 | } | ||
562 | } | ||
563 | if (regs->dst0 < dst_min_ok || regs->dst0 > dst_max_ok || | ||
564 | regs->dst0 + dst0_len > dst_max_ok) { | ||
565 | DLOG("invalid_dst"); | ||
566 | return 0; | ||
567 | } | ||
568 | if (regs->dst_cfg & PPP_SRC_PLANE_PSEUDOPLNR) { | ||
569 | if (regs->dst1 < dst_min_ok || regs->dst1 > dst_max_ok || | ||
570 | regs->dst1 + dst1_len > dst_max_ok) { | ||
571 | DLOG("invalid_dst1"); | ||
572 | return 0; | ||
573 | } | ||
574 | } | ||
575 | return 1; | ||
576 | } | ||
577 | |||
578 | |||
579 | static void flush_imgs(struct mdp_blit_req *req, struct mdp_regs *regs, | ||
580 | struct file *src_file, struct file *dst_file) | ||
581 | { | ||
582 | } | ||
583 | |||
584 | static void get_chroma_addr(struct mdp_img *img, struct mdp_rect *rect, | ||
585 | uint32_t base, uint32_t bpp, uint32_t cfg, | ||
586 | uint32_t *addr, uint32_t *ystride) | ||
587 | { | ||
588 | uint32_t compress_v = Y_TO_CRCB_RATIO(img->format); | ||
589 | uint32_t compress_h = 2; | ||
590 | uint32_t offset; | ||
591 | |||
592 | if (IS_PSEUDOPLNR(img->format)) { | ||
593 | offset = (rect->x / compress_h) * compress_h; | ||
594 | offset += rect->y == 0 ? 0 : | ||
595 | ((rect->y + 1) / compress_v) * img->width; | ||
596 | *addr = base + (img->width * img->height * bpp); | ||
597 | *addr += offset * bpp; | ||
598 | *ystride |= *ystride << 16; | ||
599 | } else { | ||
600 | *addr = 0; | ||
601 | } | ||
602 | } | ||
603 | |||
604 | static int send_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, | ||
605 | struct mdp_regs *regs, struct file *src_file, | ||
606 | struct file *dst_file) | ||
607 | { | ||
608 | mdp_writel(mdp, 1, 0x060); | ||
609 | mdp_writel(mdp, regs->src_rect, PPP_ADDR_SRC_ROI); | ||
610 | mdp_writel(mdp, regs->src0, PPP_ADDR_SRC0); | ||
611 | mdp_writel(mdp, regs->src1, PPP_ADDR_SRC1); | ||
612 | mdp_writel(mdp, regs->src_ystride, PPP_ADDR_SRC_YSTRIDE); | ||
613 | mdp_writel(mdp, regs->src_cfg, PPP_ADDR_SRC_CFG); | ||
614 | mdp_writel(mdp, regs->src_pack, PPP_ADDR_SRC_PACK_PATTERN); | ||
615 | |||
616 | mdp_writel(mdp, regs->op, PPP_ADDR_OPERATION); | ||
617 | mdp_writel(mdp, regs->phasex_init, PPP_ADDR_PHASEX_INIT); | ||
618 | mdp_writel(mdp, regs->phasey_init, PPP_ADDR_PHASEY_INIT); | ||
619 | mdp_writel(mdp, regs->phasex_step, PPP_ADDR_PHASEX_STEP); | ||
620 | mdp_writel(mdp, regs->phasey_step, PPP_ADDR_PHASEY_STEP); | ||
621 | |||
622 | mdp_writel(mdp, (req->alpha << 24) | (req->transp_mask & 0xffffff), | ||
623 | PPP_ADDR_ALPHA_TRANSP); | ||
624 | |||
625 | mdp_writel(mdp, regs->dst_cfg, PPP_ADDR_DST_CFG); | ||
626 | mdp_writel(mdp, regs->dst_pack, PPP_ADDR_DST_PACK_PATTERN); | ||
627 | mdp_writel(mdp, regs->dst_rect, PPP_ADDR_DST_ROI); | ||
628 | mdp_writel(mdp, regs->dst0, PPP_ADDR_DST0); | ||
629 | mdp_writel(mdp, regs->dst1, PPP_ADDR_DST1); | ||
630 | mdp_writel(mdp, regs->dst_ystride, PPP_ADDR_DST_YSTRIDE); | ||
631 | |||
632 | mdp_writel(mdp, regs->edge, PPP_ADDR_EDGE); | ||
633 | if (regs->op & PPP_OP_BLEND_ON) { | ||
634 | mdp_writel(mdp, regs->dst0, PPP_ADDR_BG0); | ||
635 | mdp_writel(mdp, regs->dst1, PPP_ADDR_BG1); | ||
636 | mdp_writel(mdp, regs->dst_ystride, PPP_ADDR_BG_YSTRIDE); | ||
637 | mdp_writel(mdp, src_img_cfg[req->dst.format], PPP_ADDR_BG_CFG); | ||
638 | mdp_writel(mdp, pack_pattern[req->dst.format], | ||
639 | PPP_ADDR_BG_PACK_PATTERN); | ||
640 | } | ||
641 | flush_imgs(req, regs, src_file, dst_file); | ||
642 | mdp_writel(mdp, 0x1000, MDP_DISPLAY0_START); | ||
643 | return 0; | ||
644 | } | ||
645 | |||
646 | int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, | ||
647 | struct file *src_file, unsigned long src_start, unsigned long src_len, | ||
648 | struct file *dst_file, unsigned long dst_start, unsigned long dst_len) | ||
649 | { | ||
650 | struct mdp_regs regs = {0}; | ||
651 | |||
652 | if (unlikely(req->src.format >= MDP_IMGTYPE_LIMIT || | ||
653 | req->dst.format >= MDP_IMGTYPE_LIMIT)) { | ||
654 | printk(KERN_ERR "mpd_ppp: img is of wrong format\n"); | ||
655 | return -EINVAL; | ||
656 | } | ||
657 | |||
658 | if (unlikely(req->src_rect.x > req->src.width || | ||
659 | req->src_rect.y > req->src.height || | ||
660 | req->dst_rect.x > req->dst.width || | ||
661 | req->dst_rect.y > req->dst.height)) { | ||
662 | printk(KERN_ERR "mpd_ppp: img rect is outside of img!\n"); | ||
663 | return -EINVAL; | ||
664 | } | ||
665 | |||
666 | /* set the src image configuration */ | ||
667 | regs.src_cfg = src_img_cfg[req->src.format]; | ||
668 | regs.src_cfg |= (req->src_rect.x & 0x1) ? PPP_SRC_BPP_ROI_ODD_X : 0; | ||
669 | regs.src_cfg |= (req->src_rect.y & 0x1) ? PPP_SRC_BPP_ROI_ODD_Y : 0; | ||
670 | regs.src_rect = (req->src_rect.h << 16) | req->src_rect.w; | ||
671 | regs.src_pack = pack_pattern[req->src.format]; | ||
672 | |||
673 | /* set the dest image configuration */ | ||
674 | regs.dst_cfg = dst_img_cfg[req->dst.format] | PPP_DST_OUT_SEL_AXI; | ||
675 | regs.dst_rect = (req->dst_rect.h << 16) | req->dst_rect.w; | ||
676 | regs.dst_pack = pack_pattern[req->dst.format]; | ||
677 | |||
678 | /* set src, bpp, start pixel and ystride */ | ||
679 | regs.src_bpp = bytes_per_pixel[req->src.format]; | ||
680 | regs.src0 = src_start + req->src.offset; | ||
681 | regs.src_ystride = req->src.width * regs.src_bpp; | ||
682 | get_chroma_addr(&req->src, &req->src_rect, regs.src0, regs.src_bpp, | ||
683 | regs.src_cfg, ®s.src1, ®s.src_ystride); | ||
684 | regs.src0 += (req->src_rect.x + (req->src_rect.y * req->src.width)) * | ||
685 | regs.src_bpp; | ||
686 | |||
687 | /* set dst, bpp, start pixel and ystride */ | ||
688 | regs.dst_bpp = bytes_per_pixel[req->dst.format]; | ||
689 | regs.dst0 = dst_start + req->dst.offset; | ||
690 | regs.dst_ystride = req->dst.width * regs.dst_bpp; | ||
691 | get_chroma_addr(&req->dst, &req->dst_rect, regs.dst0, regs.dst_bpp, | ||
692 | regs.dst_cfg, ®s.dst1, ®s.dst_ystride); | ||
693 | regs.dst0 += (req->dst_rect.x + (req->dst_rect.y * req->dst.width)) * | ||
694 | regs.dst_bpp; | ||
695 | |||
696 | if (!valid_src_dst(src_start, src_len, dst_start, dst_len, req, | ||
697 | ®s)) { | ||
698 | printk(KERN_ERR "mpd_ppp: final src or dst location is " | ||
699 | "invalid, are you trying to make an image too large " | ||
700 | "or to place it outside the screen?\n"); | ||
701 | return -EINVAL; | ||
702 | } | ||
703 | |||
704 | /* set up operation register */ | ||
705 | regs.op = 0; | ||
706 | blit_rotate(req, ®s); | ||
707 | blit_convert(req, ®s); | ||
708 | if (req->flags & MDP_DITHER) | ||
709 | regs.op |= PPP_OP_DITHER_EN; | ||
710 | blit_blend(req, ®s); | ||
711 | if (blit_scale(mdp, req, ®s)) { | ||
712 | printk(KERN_ERR "mpd_ppp: error computing scale for img.\n"); | ||
713 | return -EINVAL; | ||
714 | } | ||
715 | blit_blur(mdp, req, ®s); | ||
716 | regs.op |= dst_op_chroma[req->dst.format] | | ||
717 | src_op_chroma[req->src.format]; | ||
718 | |||
719 | /* if the image is YCRYCB, the x and w must be even */ | ||
720 | if (unlikely(req->src.format == MDP_YCRYCB_H2V1)) { | ||
721 | req->src_rect.x = req->src_rect.x & (~0x1); | ||
722 | req->src_rect.w = req->src_rect.w & (~0x1); | ||
723 | req->dst_rect.x = req->dst_rect.x & (~0x1); | ||
724 | req->dst_rect.w = req->dst_rect.w & (~0x1); | ||
725 | } | ||
726 | if (get_edge_cond(req, ®s)) | ||
727 | return -EINVAL; | ||
728 | |||
729 | send_blit(mdp, req, ®s, src_file, dst_file); | ||
730 | return 0; | ||
731 | } | ||
diff --git a/drivers/video/fbdev/msm/mdp_scale_tables.c b/drivers/video/fbdev/msm/mdp_scale_tables.c deleted file mode 100644 index 604783b2e17c..000000000000 --- a/drivers/video/fbdev/msm/mdp_scale_tables.c +++ /dev/null | |||
@@ -1,766 +0,0 @@ | |||
1 | /* drivers/video/msm_fb/mdp_scale_tables.c | ||
2 | * | ||
3 | * Copyright (C) 2007 QUALCOMM Incorporated | ||
4 | * Copyright (C) 2007 Google Incorporated | ||
5 | * | ||
6 | * This software is licensed under the terms of the GNU General Public | ||
7 | * License version 2, as published by the Free Software Foundation, and | ||
8 | * may be copied, distributed, and modified under those terms. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #include "mdp_scale_tables.h" | ||
17 | #include "mdp_hw.h" | ||
18 | |||
19 | struct mdp_table_entry mdp_upscale_table[] = { | ||
20 | { 0x5fffc, 0x0 }, | ||
21 | { 0x50200, 0x7fc00000 }, | ||
22 | { 0x5fffc, 0xff80000d }, | ||
23 | { 0x50204, 0x7ec003f9 }, | ||
24 | { 0x5fffc, 0xfec0001c }, | ||
25 | { 0x50208, 0x7d4003f3 }, | ||
26 | { 0x5fffc, 0xfe40002b }, | ||
27 | { 0x5020c, 0x7b8003ed }, | ||
28 | { 0x5fffc, 0xfd80003c }, | ||
29 | { 0x50210, 0x794003e8 }, | ||
30 | { 0x5fffc, 0xfcc0004d }, | ||
31 | { 0x50214, 0x76c003e4 }, | ||
32 | { 0x5fffc, 0xfc40005f }, | ||
33 | { 0x50218, 0x73c003e0 }, | ||
34 | { 0x5fffc, 0xfb800071 }, | ||
35 | { 0x5021c, 0x708003de }, | ||
36 | { 0x5fffc, 0xfac00085 }, | ||
37 | { 0x50220, 0x6d0003db }, | ||
38 | { 0x5fffc, 0xfa000098 }, | ||
39 | { 0x50224, 0x698003d9 }, | ||
40 | { 0x5fffc, 0xf98000ac }, | ||
41 | { 0x50228, 0x654003d8 }, | ||
42 | { 0x5fffc, 0xf8c000c1 }, | ||
43 | { 0x5022c, 0x610003d7 }, | ||
44 | { 0x5fffc, 0xf84000d5 }, | ||
45 | { 0x50230, 0x5c8003d7 }, | ||
46 | { 0x5fffc, 0xf7c000e9 }, | ||
47 | { 0x50234, 0x580003d7 }, | ||
48 | { 0x5fffc, 0xf74000fd }, | ||
49 | { 0x50238, 0x534003d8 }, | ||
50 | { 0x5fffc, 0xf6c00112 }, | ||
51 | { 0x5023c, 0x4e8003d8 }, | ||
52 | { 0x5fffc, 0xf6800126 }, | ||
53 | { 0x50240, 0x494003da }, | ||
54 | { 0x5fffc, 0xf600013a }, | ||
55 | { 0x50244, 0x448003db }, | ||
56 | { 0x5fffc, 0xf600014d }, | ||
57 | { 0x50248, 0x3f4003dd }, | ||
58 | { 0x5fffc, 0xf5c00160 }, | ||
59 | { 0x5024c, 0x3a4003df }, | ||
60 | { 0x5fffc, 0xf5c00172 }, | ||
61 | { 0x50250, 0x354003e1 }, | ||
62 | { 0x5fffc, 0xf5c00184 }, | ||
63 | { 0x50254, 0x304003e3 }, | ||
64 | { 0x5fffc, 0xf6000195 }, | ||
65 | { 0x50258, 0x2b0003e6 }, | ||
66 | { 0x5fffc, 0xf64001a6 }, | ||
67 | { 0x5025c, 0x260003e8 }, | ||
68 | { 0x5fffc, 0xf6c001b4 }, | ||
69 | { 0x50260, 0x214003eb }, | ||
70 | { 0x5fffc, 0xf78001c2 }, | ||
71 | { 0x50264, 0x1c4003ee }, | ||
72 | { 0x5fffc, 0xf80001cf }, | ||
73 | { 0x50268, 0x17c003f1 }, | ||
74 | { 0x5fffc, 0xf90001db }, | ||
75 | { 0x5026c, 0x134003f3 }, | ||
76 | { 0x5fffc, 0xfa0001e5 }, | ||
77 | { 0x50270, 0xf0003f6 }, | ||
78 | { 0x5fffc, 0xfb4001ee }, | ||
79 | { 0x50274, 0xac003f9 }, | ||
80 | { 0x5fffc, 0xfcc001f5 }, | ||
81 | { 0x50278, 0x70003fb }, | ||
82 | { 0x5fffc, 0xfe4001fb }, | ||
83 | { 0x5027c, 0x34003fe }, | ||
84 | }; | ||
85 | |||
86 | static struct mdp_table_entry mdp_downscale_x_table_PT2TOPT4[] = { | ||
87 | { 0x5fffc, 0x740008c }, | ||
88 | { 0x50280, 0x33800088 }, | ||
89 | { 0x5fffc, 0x800008e }, | ||
90 | { 0x50284, 0x33400084 }, | ||
91 | { 0x5fffc, 0x8400092 }, | ||
92 | { 0x50288, 0x33000080 }, | ||
93 | { 0x5fffc, 0x9000094 }, | ||
94 | { 0x5028c, 0x3300007b }, | ||
95 | { 0x5fffc, 0x9c00098 }, | ||
96 | { 0x50290, 0x32400077 }, | ||
97 | { 0x5fffc, 0xa40009b }, | ||
98 | { 0x50294, 0x32000073 }, | ||
99 | { 0x5fffc, 0xb00009d }, | ||
100 | { 0x50298, 0x31c0006f }, | ||
101 | { 0x5fffc, 0xbc000a0 }, | ||
102 | { 0x5029c, 0x3140006b }, | ||
103 | { 0x5fffc, 0xc8000a2 }, | ||
104 | { 0x502a0, 0x31000067 }, | ||
105 | { 0x5fffc, 0xd8000a5 }, | ||
106 | { 0x502a4, 0x30800062 }, | ||
107 | { 0x5fffc, 0xe4000a8 }, | ||
108 | { 0x502a8, 0x2fc0005f }, | ||
109 | { 0x5fffc, 0xec000aa }, | ||
110 | { 0x502ac, 0x2fc0005b }, | ||
111 | { 0x5fffc, 0xf8000ad }, | ||
112 | { 0x502b0, 0x2f400057 }, | ||
113 | { 0x5fffc, 0x108000b0 }, | ||
114 | { 0x502b4, 0x2e400054 }, | ||
115 | { 0x5fffc, 0x114000b2 }, | ||
116 | { 0x502b8, 0x2e000050 }, | ||
117 | { 0x5fffc, 0x124000b4 }, | ||
118 | { 0x502bc, 0x2d80004c }, | ||
119 | { 0x5fffc, 0x130000b6 }, | ||
120 | { 0x502c0, 0x2d000049 }, | ||
121 | { 0x5fffc, 0x140000b8 }, | ||
122 | { 0x502c4, 0x2c800045 }, | ||
123 | { 0x5fffc, 0x150000b9 }, | ||
124 | { 0x502c8, 0x2c000042 }, | ||
125 | { 0x5fffc, 0x15c000bd }, | ||
126 | { 0x502cc, 0x2b40003e }, | ||
127 | { 0x5fffc, 0x16c000bf }, | ||
128 | { 0x502d0, 0x2a80003b }, | ||
129 | { 0x5fffc, 0x17c000bf }, | ||
130 | { 0x502d4, 0x2a000039 }, | ||
131 | { 0x5fffc, 0x188000c2 }, | ||
132 | { 0x502d8, 0x29400036 }, | ||
133 | { 0x5fffc, 0x19c000c4 }, | ||
134 | { 0x502dc, 0x28800032 }, | ||
135 | { 0x5fffc, 0x1ac000c5 }, | ||
136 | { 0x502e0, 0x2800002f }, | ||
137 | { 0x5fffc, 0x1bc000c7 }, | ||
138 | { 0x502e4, 0x2740002c }, | ||
139 | { 0x5fffc, 0x1cc000c8 }, | ||
140 | { 0x502e8, 0x26c00029 }, | ||
141 | { 0x5fffc, 0x1dc000c9 }, | ||
142 | { 0x502ec, 0x26000027 }, | ||
143 | { 0x5fffc, 0x1ec000cc }, | ||
144 | { 0x502f0, 0x25000024 }, | ||
145 | { 0x5fffc, 0x200000cc }, | ||
146 | { 0x502f4, 0x24800021 }, | ||
147 | { 0x5fffc, 0x210000cd }, | ||
148 | { 0x502f8, 0x23800020 }, | ||
149 | { 0x5fffc, 0x220000ce }, | ||
150 | { 0x502fc, 0x2300001d }, | ||
151 | }; | ||
152 | |||
153 | static struct mdp_table_entry mdp_downscale_x_table_PT4TOPT6[] = { | ||
154 | { 0x5fffc, 0x740008c }, | ||
155 | { 0x50280, 0x33800088 }, | ||
156 | { 0x5fffc, 0x800008e }, | ||
157 | { 0x50284, 0x33400084 }, | ||
158 | { 0x5fffc, 0x8400092 }, | ||
159 | { 0x50288, 0x33000080 }, | ||
160 | { 0x5fffc, 0x9000094 }, | ||
161 | { 0x5028c, 0x3300007b }, | ||
162 | { 0x5fffc, 0x9c00098 }, | ||
163 | { 0x50290, 0x32400077 }, | ||
164 | { 0x5fffc, 0xa40009b }, | ||
165 | { 0x50294, 0x32000073 }, | ||
166 | { 0x5fffc, 0xb00009d }, | ||
167 | { 0x50298, 0x31c0006f }, | ||
168 | { 0x5fffc, 0xbc000a0 }, | ||
169 | { 0x5029c, 0x3140006b }, | ||
170 | { 0x5fffc, 0xc8000a2 }, | ||
171 | { 0x502a0, 0x31000067 }, | ||
172 | { 0x5fffc, 0xd8000a5 }, | ||
173 | { 0x502a4, 0x30800062 }, | ||
174 | { 0x5fffc, 0xe4000a8 }, | ||
175 | { 0x502a8, 0x2fc0005f }, | ||
176 | { 0x5fffc, 0xec000aa }, | ||
177 | { 0x502ac, 0x2fc0005b }, | ||
178 | { 0x5fffc, 0xf8000ad }, | ||
179 | { 0x502b0, 0x2f400057 }, | ||
180 | { 0x5fffc, 0x108000b0 }, | ||
181 | { 0x502b4, 0x2e400054 }, | ||
182 | { 0x5fffc, 0x114000b2 }, | ||
183 | { 0x502b8, 0x2e000050 }, | ||
184 | { 0x5fffc, 0x124000b4 }, | ||
185 | { 0x502bc, 0x2d80004c }, | ||
186 | { 0x5fffc, 0x130000b6 }, | ||
187 | { 0x502c0, 0x2d000049 }, | ||
188 | { 0x5fffc, 0x140000b8 }, | ||
189 | { 0x502c4, 0x2c800045 }, | ||
190 | { 0x5fffc, 0x150000b9 }, | ||
191 | { 0x502c8, 0x2c000042 }, | ||
192 | { 0x5fffc, 0x15c000bd }, | ||
193 | { 0x502cc, 0x2b40003e }, | ||
194 | { 0x5fffc, 0x16c000bf }, | ||
195 | { 0x502d0, 0x2a80003b }, | ||
196 | { 0x5fffc, 0x17c000bf }, | ||
197 | { 0x502d4, 0x2a000039 }, | ||
198 | { 0x5fffc, 0x188000c2 }, | ||
199 | { 0x502d8, 0x29400036 }, | ||
200 | { 0x5fffc, 0x19c000c4 }, | ||
201 | { 0x502dc, 0x28800032 }, | ||
202 | { 0x5fffc, 0x1ac000c5 }, | ||
203 | { 0x502e0, 0x2800002f }, | ||
204 | { 0x5fffc, 0x1bc000c7 }, | ||
205 | { 0x502e4, 0x2740002c }, | ||
206 | { 0x5fffc, 0x1cc000c8 }, | ||
207 | { 0x502e8, 0x26c00029 }, | ||
208 | { 0x5fffc, 0x1dc000c9 }, | ||
209 | { 0x502ec, 0x26000027 }, | ||
210 | { 0x5fffc, 0x1ec000cc }, | ||
211 | { 0x502f0, 0x25000024 }, | ||
212 | { 0x5fffc, 0x200000cc }, | ||
213 | { 0x502f4, 0x24800021 }, | ||
214 | { 0x5fffc, 0x210000cd }, | ||
215 | { 0x502f8, 0x23800020 }, | ||
216 | { 0x5fffc, 0x220000ce }, | ||
217 | { 0x502fc, 0x2300001d }, | ||
218 | }; | ||
219 | |||
220 | static struct mdp_table_entry mdp_downscale_x_table_PT6TOPT8[] = { | ||
221 | { 0x5fffc, 0xfe000070 }, | ||
222 | { 0x50280, 0x4bc00068 }, | ||
223 | { 0x5fffc, 0xfe000078 }, | ||
224 | { 0x50284, 0x4bc00060 }, | ||
225 | { 0x5fffc, 0xfe000080 }, | ||
226 | { 0x50288, 0x4b800059 }, | ||
227 | { 0x5fffc, 0xfe000089 }, | ||
228 | { 0x5028c, 0x4b000052 }, | ||
229 | { 0x5fffc, 0xfe400091 }, | ||
230 | { 0x50290, 0x4a80004b }, | ||
231 | { 0x5fffc, 0xfe40009a }, | ||
232 | { 0x50294, 0x4a000044 }, | ||
233 | { 0x5fffc, 0xfe8000a3 }, | ||
234 | { 0x50298, 0x4940003d }, | ||
235 | { 0x5fffc, 0xfec000ac }, | ||
236 | { 0x5029c, 0x48400037 }, | ||
237 | { 0x5fffc, 0xff0000b4 }, | ||
238 | { 0x502a0, 0x47800031 }, | ||
239 | { 0x5fffc, 0xff8000bd }, | ||
240 | { 0x502a4, 0x4640002b }, | ||
241 | { 0x5fffc, 0xc5 }, | ||
242 | { 0x502a8, 0x45000026 }, | ||
243 | { 0x5fffc, 0x8000ce }, | ||
244 | { 0x502ac, 0x43800021 }, | ||
245 | { 0x5fffc, 0x10000d6 }, | ||
246 | { 0x502b0, 0x4240001c }, | ||
247 | { 0x5fffc, 0x18000df }, | ||
248 | { 0x502b4, 0x40800018 }, | ||
249 | { 0x5fffc, 0x24000e6 }, | ||
250 | { 0x502b8, 0x3f000014 }, | ||
251 | { 0x5fffc, 0x30000ee }, | ||
252 | { 0x502bc, 0x3d400010 }, | ||
253 | { 0x5fffc, 0x40000f5 }, | ||
254 | { 0x502c0, 0x3b80000c }, | ||
255 | { 0x5fffc, 0x50000fc }, | ||
256 | { 0x502c4, 0x39800009 }, | ||
257 | { 0x5fffc, 0x6000102 }, | ||
258 | { 0x502c8, 0x37c00006 }, | ||
259 | { 0x5fffc, 0x7000109 }, | ||
260 | { 0x502cc, 0x35800004 }, | ||
261 | { 0x5fffc, 0x840010e }, | ||
262 | { 0x502d0, 0x33800002 }, | ||
263 | { 0x5fffc, 0x9800114 }, | ||
264 | { 0x502d4, 0x31400000 }, | ||
265 | { 0x5fffc, 0xac00119 }, | ||
266 | { 0x502d8, 0x2f4003fe }, | ||
267 | { 0x5fffc, 0xc40011e }, | ||
268 | { 0x502dc, 0x2d0003fc }, | ||
269 | { 0x5fffc, 0xdc00121 }, | ||
270 | { 0x502e0, 0x2b0003fb }, | ||
271 | { 0x5fffc, 0xf400125 }, | ||
272 | { 0x502e4, 0x28c003fa }, | ||
273 | { 0x5fffc, 0x11000128 }, | ||
274 | { 0x502e8, 0x268003f9 }, | ||
275 | { 0x5fffc, 0x12c0012a }, | ||
276 | { 0x502ec, 0x244003f9 }, | ||
277 | { 0x5fffc, 0x1480012c }, | ||
278 | { 0x502f0, 0x224003f8 }, | ||
279 | { 0x5fffc, 0x1640012e }, | ||
280 | { 0x502f4, 0x200003f8 }, | ||
281 | { 0x5fffc, 0x1800012f }, | ||
282 | { 0x502f8, 0x1e0003f8 }, | ||
283 | { 0x5fffc, 0x1a00012f }, | ||
284 | { 0x502fc, 0x1c0003f8 }, | ||
285 | }; | ||
286 | |||
287 | static struct mdp_table_entry mdp_downscale_x_table_PT8TO1[] = { | ||
288 | { 0x5fffc, 0x0 }, | ||
289 | { 0x50280, 0x7fc00000 }, | ||
290 | { 0x5fffc, 0xff80000d }, | ||
291 | { 0x50284, 0x7ec003f9 }, | ||
292 | { 0x5fffc, 0xfec0001c }, | ||
293 | { 0x50288, 0x7d4003f3 }, | ||
294 | { 0x5fffc, 0xfe40002b }, | ||
295 | { 0x5028c, 0x7b8003ed }, | ||
296 | { 0x5fffc, 0xfd80003c }, | ||
297 | { 0x50290, 0x794003e8 }, | ||
298 | { 0x5fffc, 0xfcc0004d }, | ||
299 | { 0x50294, 0x76c003e4 }, | ||
300 | { 0x5fffc, 0xfc40005f }, | ||
301 | { 0x50298, 0x73c003e0 }, | ||
302 | { 0x5fffc, 0xfb800071 }, | ||
303 | { 0x5029c, 0x708003de }, | ||
304 | { 0x5fffc, 0xfac00085 }, | ||
305 | { 0x502a0, 0x6d0003db }, | ||
306 | { 0x5fffc, 0xfa000098 }, | ||
307 | { 0x502a4, 0x698003d9 }, | ||
308 | { 0x5fffc, 0xf98000ac }, | ||
309 | { 0x502a8, 0x654003d8 }, | ||
310 | { 0x5fffc, 0xf8c000c1 }, | ||
311 | { 0x502ac, 0x610003d7 }, | ||
312 | { 0x5fffc, 0xf84000d5 }, | ||
313 | { 0x502b0, 0x5c8003d7 }, | ||
314 | { 0x5fffc, 0xf7c000e9 }, | ||
315 | { 0x502b4, 0x580003d7 }, | ||
316 | { 0x5fffc, 0xf74000fd }, | ||
317 | { 0x502b8, 0x534003d8 }, | ||
318 | { 0x5fffc, 0xf6c00112 }, | ||
319 | { 0x502bc, 0x4e8003d8 }, | ||
320 | { 0x5fffc, 0xf6800126 }, | ||
321 | { 0x502c0, 0x494003da }, | ||
322 | { 0x5fffc, 0xf600013a }, | ||
323 | { 0x502c4, 0x448003db }, | ||
324 | { 0x5fffc, 0xf600014d }, | ||
325 | { 0x502c8, 0x3f4003dd }, | ||
326 | { 0x5fffc, 0xf5c00160 }, | ||
327 | { 0x502cc, 0x3a4003df }, | ||
328 | { 0x5fffc, 0xf5c00172 }, | ||
329 | { 0x502d0, 0x354003e1 }, | ||
330 | { 0x5fffc, 0xf5c00184 }, | ||
331 | { 0x502d4, 0x304003e3 }, | ||
332 | { 0x5fffc, 0xf6000195 }, | ||
333 | { 0x502d8, 0x2b0003e6 }, | ||
334 | { 0x5fffc, 0xf64001a6 }, | ||
335 | { 0x502dc, 0x260003e8 }, | ||
336 | { 0x5fffc, 0xf6c001b4 }, | ||
337 | { 0x502e0, 0x214003eb }, | ||
338 | { 0x5fffc, 0xf78001c2 }, | ||
339 | { 0x502e4, 0x1c4003ee }, | ||
340 | { 0x5fffc, 0xf80001cf }, | ||
341 | { 0x502e8, 0x17c003f1 }, | ||
342 | { 0x5fffc, 0xf90001db }, | ||
343 | { 0x502ec, 0x134003f3 }, | ||
344 | { 0x5fffc, 0xfa0001e5 }, | ||
345 | { 0x502f0, 0xf0003f6 }, | ||
346 | { 0x5fffc, 0xfb4001ee }, | ||
347 | { 0x502f4, 0xac003f9 }, | ||
348 | { 0x5fffc, 0xfcc001f5 }, | ||
349 | { 0x502f8, 0x70003fb }, | ||
350 | { 0x5fffc, 0xfe4001fb }, | ||
351 | { 0x502fc, 0x34003fe }, | ||
352 | }; | ||
353 | |||
354 | struct mdp_table_entry *mdp_downscale_x_table[MDP_DOWNSCALE_MAX] = { | ||
355 | [MDP_DOWNSCALE_PT2TOPT4] = mdp_downscale_x_table_PT2TOPT4, | ||
356 | [MDP_DOWNSCALE_PT4TOPT6] = mdp_downscale_x_table_PT4TOPT6, | ||
357 | [MDP_DOWNSCALE_PT6TOPT8] = mdp_downscale_x_table_PT6TOPT8, | ||
358 | [MDP_DOWNSCALE_PT8TO1] = mdp_downscale_x_table_PT8TO1, | ||
359 | }; | ||
360 | |||
361 | static struct mdp_table_entry mdp_downscale_y_table_PT2TOPT4[] = { | ||
362 | { 0x5fffc, 0x740008c }, | ||
363 | { 0x50300, 0x33800088 }, | ||
364 | { 0x5fffc, 0x800008e }, | ||
365 | { 0x50304, 0x33400084 }, | ||
366 | { 0x5fffc, 0x8400092 }, | ||
367 | { 0x50308, 0x33000080 }, | ||
368 | { 0x5fffc, 0x9000094 }, | ||
369 | { 0x5030c, 0x3300007b }, | ||
370 | { 0x5fffc, 0x9c00098 }, | ||
371 | { 0x50310, 0x32400077 }, | ||
372 | { 0x5fffc, 0xa40009b }, | ||
373 | { 0x50314, 0x32000073 }, | ||
374 | { 0x5fffc, 0xb00009d }, | ||
375 | { 0x50318, 0x31c0006f }, | ||
376 | { 0x5fffc, 0xbc000a0 }, | ||
377 | { 0x5031c, 0x3140006b }, | ||
378 | { 0x5fffc, 0xc8000a2 }, | ||
379 | { 0x50320, 0x31000067 }, | ||
380 | { 0x5fffc, 0xd8000a5 }, | ||
381 | { 0x50324, 0x30800062 }, | ||
382 | { 0x5fffc, 0xe4000a8 }, | ||
383 | { 0x50328, 0x2fc0005f }, | ||
384 | { 0x5fffc, 0xec000aa }, | ||
385 | { 0x5032c, 0x2fc0005b }, | ||
386 | { 0x5fffc, 0xf8000ad }, | ||
387 | { 0x50330, 0x2f400057 }, | ||
388 | { 0x5fffc, 0x108000b0 }, | ||
389 | { 0x50334, 0x2e400054 }, | ||
390 | { 0x5fffc, 0x114000b2 }, | ||
391 | { 0x50338, 0x2e000050 }, | ||
392 | { 0x5fffc, 0x124000b4 }, | ||
393 | { 0x5033c, 0x2d80004c }, | ||
394 | { 0x5fffc, 0x130000b6 }, | ||
395 | { 0x50340, 0x2d000049 }, | ||
396 | { 0x5fffc, 0x140000b8 }, | ||
397 | { 0x50344, 0x2c800045 }, | ||
398 | { 0x5fffc, 0x150000b9 }, | ||
399 | { 0x50348, 0x2c000042 }, | ||
400 | { 0x5fffc, 0x15c000bd }, | ||
401 | { 0x5034c, 0x2b40003e }, | ||
402 | { 0x5fffc, 0x16c000bf }, | ||
403 | { 0x50350, 0x2a80003b }, | ||
404 | { 0x5fffc, 0x17c000bf }, | ||
405 | { 0x50354, 0x2a000039 }, | ||
406 | { 0x5fffc, 0x188000c2 }, | ||
407 | { 0x50358, 0x29400036 }, | ||
408 | { 0x5fffc, 0x19c000c4 }, | ||
409 | { 0x5035c, 0x28800032 }, | ||
410 | { 0x5fffc, 0x1ac000c5 }, | ||
411 | { 0x50360, 0x2800002f }, | ||
412 | { 0x5fffc, 0x1bc000c7 }, | ||
413 | { 0x50364, 0x2740002c }, | ||
414 | { 0x5fffc, 0x1cc000c8 }, | ||
415 | { 0x50368, 0x26c00029 }, | ||
416 | { 0x5fffc, 0x1dc000c9 }, | ||
417 | { 0x5036c, 0x26000027 }, | ||
418 | { 0x5fffc, 0x1ec000cc }, | ||
419 | { 0x50370, 0x25000024 }, | ||
420 | { 0x5fffc, 0x200000cc }, | ||
421 | { 0x50374, 0x24800021 }, | ||
422 | { 0x5fffc, 0x210000cd }, | ||
423 | { 0x50378, 0x23800020 }, | ||
424 | { 0x5fffc, 0x220000ce }, | ||
425 | { 0x5037c, 0x2300001d }, | ||
426 | }; | ||
427 | |||
428 | static struct mdp_table_entry mdp_downscale_y_table_PT4TOPT6[] = { | ||
429 | { 0x5fffc, 0x740008c }, | ||
430 | { 0x50300, 0x33800088 }, | ||
431 | { 0x5fffc, 0x800008e }, | ||
432 | { 0x50304, 0x33400084 }, | ||
433 | { 0x5fffc, 0x8400092 }, | ||
434 | { 0x50308, 0x33000080 }, | ||
435 | { 0x5fffc, 0x9000094 }, | ||
436 | { 0x5030c, 0x3300007b }, | ||
437 | { 0x5fffc, 0x9c00098 }, | ||
438 | { 0x50310, 0x32400077 }, | ||
439 | { 0x5fffc, 0xa40009b }, | ||
440 | { 0x50314, 0x32000073 }, | ||
441 | { 0x5fffc, 0xb00009d }, | ||
442 | { 0x50318, 0x31c0006f }, | ||
443 | { 0x5fffc, 0xbc000a0 }, | ||
444 | { 0x5031c, 0x3140006b }, | ||
445 | { 0x5fffc, 0xc8000a2 }, | ||
446 | { 0x50320, 0x31000067 }, | ||
447 | { 0x5fffc, 0xd8000a5 }, | ||
448 | { 0x50324, 0x30800062 }, | ||
449 | { 0x5fffc, 0xe4000a8 }, | ||
450 | { 0x50328, 0x2fc0005f }, | ||
451 | { 0x5fffc, 0xec000aa }, | ||
452 | { 0x5032c, 0x2fc0005b }, | ||
453 | { 0x5fffc, 0xf8000ad }, | ||
454 | { 0x50330, 0x2f400057 }, | ||
455 | { 0x5fffc, 0x108000b0 }, | ||
456 | { 0x50334, 0x2e400054 }, | ||
457 | { 0x5fffc, 0x114000b2 }, | ||
458 | { 0x50338, 0x2e000050 }, | ||
459 | { 0x5fffc, 0x124000b4 }, | ||
460 | { 0x5033c, 0x2d80004c }, | ||
461 | { 0x5fffc, 0x130000b6 }, | ||
462 | { 0x50340, 0x2d000049 }, | ||
463 | { 0x5fffc, 0x140000b8 }, | ||
464 | { 0x50344, 0x2c800045 }, | ||
465 | { 0x5fffc, 0x150000b9 }, | ||
466 | { 0x50348, 0x2c000042 }, | ||
467 | { 0x5fffc, 0x15c000bd }, | ||
468 | { 0x5034c, 0x2b40003e }, | ||
469 | { 0x5fffc, 0x16c000bf }, | ||
470 | { 0x50350, 0x2a80003b }, | ||
471 | { 0x5fffc, 0x17c000bf }, | ||
472 | { 0x50354, 0x2a000039 }, | ||
473 | { 0x5fffc, 0x188000c2 }, | ||
474 | { 0x50358, 0x29400036 }, | ||
475 | { 0x5fffc, 0x19c000c4 }, | ||
476 | { 0x5035c, 0x28800032 }, | ||
477 | { 0x5fffc, 0x1ac000c5 }, | ||
478 | { 0x50360, 0x2800002f }, | ||
479 | { 0x5fffc, 0x1bc000c7 }, | ||
480 | { 0x50364, 0x2740002c }, | ||
481 | { 0x5fffc, 0x1cc000c8 }, | ||
482 | { 0x50368, 0x26c00029 }, | ||
483 | { 0x5fffc, 0x1dc000c9 }, | ||
484 | { 0x5036c, 0x26000027 }, | ||
485 | { 0x5fffc, 0x1ec000cc }, | ||
486 | { 0x50370, 0x25000024 }, | ||
487 | { 0x5fffc, 0x200000cc }, | ||
488 | { 0x50374, 0x24800021 }, | ||
489 | { 0x5fffc, 0x210000cd }, | ||
490 | { 0x50378, 0x23800020 }, | ||
491 | { 0x5fffc, 0x220000ce }, | ||
492 | { 0x5037c, 0x2300001d }, | ||
493 | }; | ||
494 | |||
495 | static struct mdp_table_entry mdp_downscale_y_table_PT6TOPT8[] = { | ||
496 | { 0x5fffc, 0xfe000070 }, | ||
497 | { 0x50300, 0x4bc00068 }, | ||
498 | { 0x5fffc, 0xfe000078 }, | ||
499 | { 0x50304, 0x4bc00060 }, | ||
500 | { 0x5fffc, 0xfe000080 }, | ||
501 | { 0x50308, 0x4b800059 }, | ||
502 | { 0x5fffc, 0xfe000089 }, | ||
503 | { 0x5030c, 0x4b000052 }, | ||
504 | { 0x5fffc, 0xfe400091 }, | ||
505 | { 0x50310, 0x4a80004b }, | ||
506 | { 0x5fffc, 0xfe40009a }, | ||
507 | { 0x50314, 0x4a000044 }, | ||
508 | { 0x5fffc, 0xfe8000a3 }, | ||
509 | { 0x50318, 0x4940003d }, | ||
510 | { 0x5fffc, 0xfec000ac }, | ||
511 | { 0x5031c, 0x48400037 }, | ||
512 | { 0x5fffc, 0xff0000b4 }, | ||
513 | { 0x50320, 0x47800031 }, | ||
514 | { 0x5fffc, 0xff8000bd }, | ||
515 | { 0x50324, 0x4640002b }, | ||
516 | { 0x5fffc, 0xc5 }, | ||
517 | { 0x50328, 0x45000026 }, | ||
518 | { 0x5fffc, 0x8000ce }, | ||
519 | { 0x5032c, 0x43800021 }, | ||
520 | { 0x5fffc, 0x10000d6 }, | ||
521 | { 0x50330, 0x4240001c }, | ||
522 | { 0x5fffc, 0x18000df }, | ||
523 | { 0x50334, 0x40800018 }, | ||
524 | { 0x5fffc, 0x24000e6 }, | ||
525 | { 0x50338, 0x3f000014 }, | ||
526 | { 0x5fffc, 0x30000ee }, | ||
527 | { 0x5033c, 0x3d400010 }, | ||
528 | { 0x5fffc, 0x40000f5 }, | ||
529 | { 0x50340, 0x3b80000c }, | ||
530 | { 0x5fffc, 0x50000fc }, | ||
531 | { 0x50344, 0x39800009 }, | ||
532 | { 0x5fffc, 0x6000102 }, | ||
533 | { 0x50348, 0x37c00006 }, | ||
534 | { 0x5fffc, 0x7000109 }, | ||
535 | { 0x5034c, 0x35800004 }, | ||
536 | { 0x5fffc, 0x840010e }, | ||
537 | { 0x50350, 0x33800002 }, | ||
538 | { 0x5fffc, 0x9800114 }, | ||
539 | { 0x50354, 0x31400000 }, | ||
540 | { 0x5fffc, 0xac00119 }, | ||
541 | { 0x50358, 0x2f4003fe }, | ||
542 | { 0x5fffc, 0xc40011e }, | ||
543 | { 0x5035c, 0x2d0003fc }, | ||
544 | { 0x5fffc, 0xdc00121 }, | ||
545 | { 0x50360, 0x2b0003fb }, | ||
546 | { 0x5fffc, 0xf400125 }, | ||
547 | { 0x50364, 0x28c003fa }, | ||
548 | { 0x5fffc, 0x11000128 }, | ||
549 | { 0x50368, 0x268003f9 }, | ||
550 | { 0x5fffc, 0x12c0012a }, | ||
551 | { 0x5036c, 0x244003f9 }, | ||
552 | { 0x5fffc, 0x1480012c }, | ||
553 | { 0x50370, 0x224003f8 }, | ||
554 | { 0x5fffc, 0x1640012e }, | ||
555 | { 0x50374, 0x200003f8 }, | ||
556 | { 0x5fffc, 0x1800012f }, | ||
557 | { 0x50378, 0x1e0003f8 }, | ||
558 | { 0x5fffc, 0x1a00012f }, | ||
559 | { 0x5037c, 0x1c0003f8 }, | ||
560 | }; | ||
561 | |||
562 | static struct mdp_table_entry mdp_downscale_y_table_PT8TO1[] = { | ||
563 | { 0x5fffc, 0x0 }, | ||
564 | { 0x50300, 0x7fc00000 }, | ||
565 | { 0x5fffc, 0xff80000d }, | ||
566 | { 0x50304, 0x7ec003f9 }, | ||
567 | { 0x5fffc, 0xfec0001c }, | ||
568 | { 0x50308, 0x7d4003f3 }, | ||
569 | { 0x5fffc, 0xfe40002b }, | ||
570 | { 0x5030c, 0x7b8003ed }, | ||
571 | { 0x5fffc, 0xfd80003c }, | ||
572 | { 0x50310, 0x794003e8 }, | ||
573 | { 0x5fffc, 0xfcc0004d }, | ||
574 | { 0x50314, 0x76c003e4 }, | ||
575 | { 0x5fffc, 0xfc40005f }, | ||
576 | { 0x50318, 0x73c003e0 }, | ||
577 | { 0x5fffc, 0xfb800071 }, | ||
578 | { 0x5031c, 0x708003de }, | ||
579 | { 0x5fffc, 0xfac00085 }, | ||
580 | { 0x50320, 0x6d0003db }, | ||
581 | { 0x5fffc, 0xfa000098 }, | ||
582 | { 0x50324, 0x698003d9 }, | ||
583 | { 0x5fffc, 0xf98000ac }, | ||
584 | { 0x50328, 0x654003d8 }, | ||
585 | { 0x5fffc, 0xf8c000c1 }, | ||
586 | { 0x5032c, 0x610003d7 }, | ||
587 | { 0x5fffc, 0xf84000d5 }, | ||
588 | { 0x50330, 0x5c8003d7 }, | ||
589 | { 0x5fffc, 0xf7c000e9 }, | ||
590 | { 0x50334, 0x580003d7 }, | ||
591 | { 0x5fffc, 0xf74000fd }, | ||
592 | { 0x50338, 0x534003d8 }, | ||
593 | { 0x5fffc, 0xf6c00112 }, | ||
594 | { 0x5033c, 0x4e8003d8 }, | ||
595 | { 0x5fffc, 0xf6800126 }, | ||
596 | { 0x50340, 0x494003da }, | ||
597 | { 0x5fffc, 0xf600013a }, | ||
598 | { 0x50344, 0x448003db }, | ||
599 | { 0x5fffc, 0xf600014d }, | ||
600 | { 0x50348, 0x3f4003dd }, | ||
601 | { 0x5fffc, 0xf5c00160 }, | ||
602 | { 0x5034c, 0x3a4003df }, | ||
603 | { 0x5fffc, 0xf5c00172 }, | ||
604 | { 0x50350, 0x354003e1 }, | ||
605 | { 0x5fffc, 0xf5c00184 }, | ||
606 | { 0x50354, 0x304003e3 }, | ||
607 | { 0x5fffc, 0xf6000195 }, | ||
608 | { 0x50358, 0x2b0003e6 }, | ||
609 | { 0x5fffc, 0xf64001a6 }, | ||
610 | { 0x5035c, 0x260003e8 }, | ||
611 | { 0x5fffc, 0xf6c001b4 }, | ||
612 | { 0x50360, 0x214003eb }, | ||
613 | { 0x5fffc, 0xf78001c2 }, | ||
614 | { 0x50364, 0x1c4003ee }, | ||
615 | { 0x5fffc, 0xf80001cf }, | ||
616 | { 0x50368, 0x17c003f1 }, | ||
617 | { 0x5fffc, 0xf90001db }, | ||
618 | { 0x5036c, 0x134003f3 }, | ||
619 | { 0x5fffc, 0xfa0001e5 }, | ||
620 | { 0x50370, 0xf0003f6 }, | ||
621 | { 0x5fffc, 0xfb4001ee }, | ||
622 | { 0x50374, 0xac003f9 }, | ||
623 | { 0x5fffc, 0xfcc001f5 }, | ||
624 | { 0x50378, 0x70003fb }, | ||
625 | { 0x5fffc, 0xfe4001fb }, | ||
626 | { 0x5037c, 0x34003fe }, | ||
627 | }; | ||
628 | |||
629 | struct mdp_table_entry *mdp_downscale_y_table[MDP_DOWNSCALE_MAX] = { | ||
630 | [MDP_DOWNSCALE_PT2TOPT4] = mdp_downscale_y_table_PT2TOPT4, | ||
631 | [MDP_DOWNSCALE_PT4TOPT6] = mdp_downscale_y_table_PT4TOPT6, | ||
632 | [MDP_DOWNSCALE_PT6TOPT8] = mdp_downscale_y_table_PT6TOPT8, | ||
633 | [MDP_DOWNSCALE_PT8TO1] = mdp_downscale_y_table_PT8TO1, | ||
634 | }; | ||
635 | |||
636 | struct mdp_table_entry mdp_gaussian_blur_table[] = { | ||
637 | /* max variance */ | ||
638 | { 0x5fffc, 0x20000080 }, | ||
639 | { 0x50280, 0x20000080 }, | ||
640 | { 0x5fffc, 0x20000080 }, | ||
641 | { 0x50284, 0x20000080 }, | ||
642 | { 0x5fffc, 0x20000080 }, | ||
643 | { 0x50288, 0x20000080 }, | ||
644 | { 0x5fffc, 0x20000080 }, | ||
645 | { 0x5028c, 0x20000080 }, | ||
646 | { 0x5fffc, 0x20000080 }, | ||
647 | { 0x50290, 0x20000080 }, | ||
648 | { 0x5fffc, 0x20000080 }, | ||
649 | { 0x50294, 0x20000080 }, | ||
650 | { 0x5fffc, 0x20000080 }, | ||
651 | { 0x50298, 0x20000080 }, | ||
652 | { 0x5fffc, 0x20000080 }, | ||
653 | { 0x5029c, 0x20000080 }, | ||
654 | { 0x5fffc, 0x20000080 }, | ||
655 | { 0x502a0, 0x20000080 }, | ||
656 | { 0x5fffc, 0x20000080 }, | ||
657 | { 0x502a4, 0x20000080 }, | ||
658 | { 0x5fffc, 0x20000080 }, | ||
659 | { 0x502a8, 0x20000080 }, | ||
660 | { 0x5fffc, 0x20000080 }, | ||
661 | { 0x502ac, 0x20000080 }, | ||
662 | { 0x5fffc, 0x20000080 }, | ||
663 | { 0x502b0, 0x20000080 }, | ||
664 | { 0x5fffc, 0x20000080 }, | ||
665 | { 0x502b4, 0x20000080 }, | ||
666 | { 0x5fffc, 0x20000080 }, | ||
667 | { 0x502b8, 0x20000080 }, | ||
668 | { 0x5fffc, 0x20000080 }, | ||
669 | { 0x502bc, 0x20000080 }, | ||
670 | { 0x5fffc, 0x20000080 }, | ||
671 | { 0x502c0, 0x20000080 }, | ||
672 | { 0x5fffc, 0x20000080 }, | ||
673 | { 0x502c4, 0x20000080 }, | ||
674 | { 0x5fffc, 0x20000080 }, | ||
675 | { 0x502c8, 0x20000080 }, | ||
676 | { 0x5fffc, 0x20000080 }, | ||
677 | { 0x502cc, 0x20000080 }, | ||
678 | { 0x5fffc, 0x20000080 }, | ||
679 | { 0x502d0, 0x20000080 }, | ||
680 | { 0x5fffc, 0x20000080 }, | ||
681 | { 0x502d4, 0x20000080 }, | ||
682 | { 0x5fffc, 0x20000080 }, | ||
683 | { 0x502d8, 0x20000080 }, | ||
684 | { 0x5fffc, 0x20000080 }, | ||
685 | { 0x502dc, 0x20000080 }, | ||
686 | { 0x5fffc, 0x20000080 }, | ||
687 | { 0x502e0, 0x20000080 }, | ||
688 | { 0x5fffc, 0x20000080 }, | ||
689 | { 0x502e4, 0x20000080 }, | ||
690 | { 0x5fffc, 0x20000080 }, | ||
691 | { 0x502e8, 0x20000080 }, | ||
692 | { 0x5fffc, 0x20000080 }, | ||
693 | { 0x502ec, 0x20000080 }, | ||
694 | { 0x5fffc, 0x20000080 }, | ||
695 | { 0x502f0, 0x20000080 }, | ||
696 | { 0x5fffc, 0x20000080 }, | ||
697 | { 0x502f4, 0x20000080 }, | ||
698 | { 0x5fffc, 0x20000080 }, | ||
699 | { 0x502f8, 0x20000080 }, | ||
700 | { 0x5fffc, 0x20000080 }, | ||
701 | { 0x502fc, 0x20000080 }, | ||
702 | { 0x5fffc, 0x20000080 }, | ||
703 | { 0x50300, 0x20000080 }, | ||
704 | { 0x5fffc, 0x20000080 }, | ||
705 | { 0x50304, 0x20000080 }, | ||
706 | { 0x5fffc, 0x20000080 }, | ||
707 | { 0x50308, 0x20000080 }, | ||
708 | { 0x5fffc, 0x20000080 }, | ||
709 | { 0x5030c, 0x20000080 }, | ||
710 | { 0x5fffc, 0x20000080 }, | ||
711 | { 0x50310, 0x20000080 }, | ||
712 | { 0x5fffc, 0x20000080 }, | ||
713 | { 0x50314, 0x20000080 }, | ||
714 | { 0x5fffc, 0x20000080 }, | ||
715 | { 0x50318, 0x20000080 }, | ||
716 | { 0x5fffc, 0x20000080 }, | ||
717 | { 0x5031c, 0x20000080 }, | ||
718 | { 0x5fffc, 0x20000080 }, | ||
719 | { 0x50320, 0x20000080 }, | ||
720 | { 0x5fffc, 0x20000080 }, | ||
721 | { 0x50324, 0x20000080 }, | ||
722 | { 0x5fffc, 0x20000080 }, | ||
723 | { 0x50328, 0x20000080 }, | ||
724 | { 0x5fffc, 0x20000080 }, | ||
725 | { 0x5032c, 0x20000080 }, | ||
726 | { 0x5fffc, 0x20000080 }, | ||
727 | { 0x50330, 0x20000080 }, | ||
728 | { 0x5fffc, 0x20000080 }, | ||
729 | { 0x50334, 0x20000080 }, | ||
730 | { 0x5fffc, 0x20000080 }, | ||
731 | { 0x50338, 0x20000080 }, | ||
732 | { 0x5fffc, 0x20000080 }, | ||
733 | { 0x5033c, 0x20000080 }, | ||
734 | { 0x5fffc, 0x20000080 }, | ||
735 | { 0x50340, 0x20000080 }, | ||
736 | { 0x5fffc, 0x20000080 }, | ||
737 | { 0x50344, 0x20000080 }, | ||
738 | { 0x5fffc, 0x20000080 }, | ||
739 | { 0x50348, 0x20000080 }, | ||
740 | { 0x5fffc, 0x20000080 }, | ||
741 | { 0x5034c, 0x20000080 }, | ||
742 | { 0x5fffc, 0x20000080 }, | ||
743 | { 0x50350, 0x20000080 }, | ||
744 | { 0x5fffc, 0x20000080 }, | ||
745 | { 0x50354, 0x20000080 }, | ||
746 | { 0x5fffc, 0x20000080 }, | ||
747 | { 0x50358, 0x20000080 }, | ||
748 | { 0x5fffc, 0x20000080 }, | ||
749 | { 0x5035c, 0x20000080 }, | ||
750 | { 0x5fffc, 0x20000080 }, | ||
751 | { 0x50360, 0x20000080 }, | ||
752 | { 0x5fffc, 0x20000080 }, | ||
753 | { 0x50364, 0x20000080 }, | ||
754 | { 0x5fffc, 0x20000080 }, | ||
755 | { 0x50368, 0x20000080 }, | ||
756 | { 0x5fffc, 0x20000080 }, | ||
757 | { 0x5036c, 0x20000080 }, | ||
758 | { 0x5fffc, 0x20000080 }, | ||
759 | { 0x50370, 0x20000080 }, | ||
760 | { 0x5fffc, 0x20000080 }, | ||
761 | { 0x50374, 0x20000080 }, | ||
762 | { 0x5fffc, 0x20000080 }, | ||
763 | { 0x50378, 0x20000080 }, | ||
764 | { 0x5fffc, 0x20000080 }, | ||
765 | { 0x5037c, 0x20000080 }, | ||
766 | }; | ||
diff --git a/drivers/video/fbdev/msm/mdp_scale_tables.h b/drivers/video/fbdev/msm/mdp_scale_tables.h deleted file mode 100644 index 34077b1af603..000000000000 --- a/drivers/video/fbdev/msm/mdp_scale_tables.h +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* drivers/video/msm_fb/mdp_scale_tables.h | ||
2 | * | ||
3 | * Copyright (C) 2007 QUALCOMM Incorporated | ||
4 | * Copyright (C) 2007 Google Incorporated | ||
5 | * | ||
6 | * This software is licensed under the terms of the GNU General Public | ||
7 | * License version 2, as published by the Free Software Foundation, and | ||
8 | * may be copied, distributed, and modified under those terms. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | #ifndef _MDP_SCALE_TABLES_H_ | ||
16 | #define _MDP_SCALE_TABLES_H_ | ||
17 | |||
18 | #include <linux/types.h> | ||
19 | struct mdp_table_entry { | ||
20 | uint32_t reg; | ||
21 | uint32_t val; | ||
22 | }; | ||
23 | |||
24 | extern struct mdp_table_entry mdp_upscale_table[64]; | ||
25 | |||
26 | enum { | ||
27 | MDP_DOWNSCALE_PT2TOPT4, | ||
28 | MDP_DOWNSCALE_PT4TOPT6, | ||
29 | MDP_DOWNSCALE_PT6TOPT8, | ||
30 | MDP_DOWNSCALE_PT8TO1, | ||
31 | MDP_DOWNSCALE_MAX, | ||
32 | }; | ||
33 | |||
34 | extern struct mdp_table_entry *mdp_downscale_x_table[MDP_DOWNSCALE_MAX]; | ||
35 | extern struct mdp_table_entry *mdp_downscale_y_table[MDP_DOWNSCALE_MAX]; | ||
36 | extern struct mdp_table_entry mdp_gaussian_blur_table[]; | ||
37 | |||
38 | #endif | ||
diff --git a/drivers/video/fbdev/msm/msm_fb.c b/drivers/video/fbdev/msm/msm_fb.c deleted file mode 100644 index 2979d7e72126..000000000000 --- a/drivers/video/fbdev/msm/msm_fb.c +++ /dev/null | |||
@@ -1,659 +0,0 @@ | |||
1 | /* drivers/video/msm/msm_fb.c | ||
2 | * | ||
3 | * Core MSM framebuffer driver. | ||
4 | * | ||
5 | * Copyright (C) 2007 Google Incorporated | ||
6 | * | ||
7 | * This software is licensed under the terms of the GNU General Public | ||
8 | * License version 2, as published by the Free Software Foundation, and | ||
9 | * may be copied, distributed, and modified under those terms. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #include <linux/platform_device.h> | ||
18 | #include <linux/module.h> | ||
19 | #include <linux/fb.h> | ||
20 | #include <linux/slab.h> | ||
21 | #include <linux/delay.h> | ||
22 | |||
23 | #include <linux/freezer.h> | ||
24 | #include <linux/wait.h> | ||
25 | #include <linux/msm_mdp.h> | ||
26 | #include <linux/io.h> | ||
27 | #include <linux/uaccess.h> | ||
28 | #include <linux/platform_data/video-msm_fb.h> | ||
29 | #include <linux/workqueue.h> | ||
30 | #include <linux/clk.h> | ||
31 | #include <linux/debugfs.h> | ||
32 | #include <linux/dma-mapping.h> | ||
33 | |||
34 | #define PRINT_FPS 0 | ||
35 | #define PRINT_BLIT_TIME 0 | ||
36 | |||
37 | #define SLEEPING 0x4 | ||
38 | #define UPDATING 0x3 | ||
39 | #define FULL_UPDATE_DONE 0x2 | ||
40 | #define WAKING 0x1 | ||
41 | #define AWAKE 0x0 | ||
42 | |||
43 | #define NONE 0 | ||
44 | #define SUSPEND_RESUME 0x1 | ||
45 | #define FPS 0x2 | ||
46 | #define BLIT_TIME 0x4 | ||
47 | #define SHOW_UPDATES 0x8 | ||
48 | |||
49 | #define DLOG(mask, fmt, args...) \ | ||
50 | do { \ | ||
51 | if (msmfb_debug_mask & mask) \ | ||
52 | printk(KERN_INFO "msmfb: "fmt, ##args); \ | ||
53 | } while (0) | ||
54 | |||
55 | static int msmfb_debug_mask; | ||
56 | module_param_named(msmfb_debug_mask, msmfb_debug_mask, int, | ||
57 | S_IRUGO | S_IWUSR | S_IWGRP); | ||
58 | |||
59 | struct mdp_device *mdp; | ||
60 | |||
61 | struct msmfb_info { | ||
62 | struct fb_info *fb; | ||
63 | struct msm_panel_data *panel; | ||
64 | int xres; | ||
65 | int yres; | ||
66 | unsigned output_format; | ||
67 | unsigned yoffset; | ||
68 | unsigned frame_requested; | ||
69 | unsigned frame_done; | ||
70 | int sleeping; | ||
71 | unsigned update_frame; | ||
72 | struct { | ||
73 | int left; | ||
74 | int top; | ||
75 | int eright; /* exclusive */ | ||
76 | int ebottom; /* exclusive */ | ||
77 | } update_info; | ||
78 | char *black; | ||
79 | |||
80 | spinlock_t update_lock; | ||
81 | struct mutex panel_init_lock; | ||
82 | wait_queue_head_t frame_wq; | ||
83 | struct work_struct resume_work; | ||
84 | struct msmfb_callback dma_callback; | ||
85 | struct msmfb_callback vsync_callback; | ||
86 | struct hrtimer fake_vsync; | ||
87 | ktime_t vsync_request_time; | ||
88 | }; | ||
89 | |||
90 | static int msmfb_open(struct fb_info *info, int user) | ||
91 | { | ||
92 | return 0; | ||
93 | } | ||
94 | |||
95 | static int msmfb_release(struct fb_info *info, int user) | ||
96 | { | ||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | /* Called from dma interrupt handler, must not sleep */ | ||
101 | static void msmfb_handle_dma_interrupt(struct msmfb_callback *callback) | ||
102 | { | ||
103 | unsigned long irq_flags; | ||
104 | struct msmfb_info *msmfb = container_of(callback, struct msmfb_info, | ||
105 | dma_callback); | ||
106 | |||
107 | spin_lock_irqsave(&msmfb->update_lock, irq_flags); | ||
108 | msmfb->frame_done = msmfb->frame_requested; | ||
109 | if (msmfb->sleeping == UPDATING && | ||
110 | msmfb->frame_done == msmfb->update_frame) { | ||
111 | DLOG(SUSPEND_RESUME, "full update completed\n"); | ||
112 | schedule_work(&msmfb->resume_work); | ||
113 | } | ||
114 | spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); | ||
115 | wake_up(&msmfb->frame_wq); | ||
116 | } | ||
117 | |||
118 | static int msmfb_start_dma(struct msmfb_info *msmfb) | ||
119 | { | ||
120 | uint32_t x, y, w, h; | ||
121 | unsigned addr; | ||
122 | unsigned long irq_flags; | ||
123 | uint32_t yoffset; | ||
124 | s64 time_since_request; | ||
125 | struct msm_panel_data *panel = msmfb->panel; | ||
126 | |||
127 | spin_lock_irqsave(&msmfb->update_lock, irq_flags); | ||
128 | time_since_request = ktime_to_ns(ktime_sub(ktime_get(), | ||
129 | msmfb->vsync_request_time)); | ||
130 | if (time_since_request > 20 * NSEC_PER_MSEC) { | ||
131 | uint32_t us; | ||
132 | us = do_div(time_since_request, NSEC_PER_MSEC) / NSEC_PER_USEC; | ||
133 | printk(KERN_WARNING "msmfb_start_dma %lld.%03u ms after vsync " | ||
134 | "request\n", time_since_request, us); | ||
135 | } | ||
136 | if (msmfb->frame_done == msmfb->frame_requested) { | ||
137 | spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); | ||
138 | return -1; | ||
139 | } | ||
140 | if (msmfb->sleeping == SLEEPING) { | ||
141 | DLOG(SUSPEND_RESUME, "tried to start dma while asleep\n"); | ||
142 | spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); | ||
143 | return -1; | ||
144 | } | ||
145 | x = msmfb->update_info.left; | ||
146 | y = msmfb->update_info.top; | ||
147 | w = msmfb->update_info.eright - x; | ||
148 | h = msmfb->update_info.ebottom - y; | ||
149 | yoffset = msmfb->yoffset; | ||
150 | msmfb->update_info.left = msmfb->xres + 1; | ||
151 | msmfb->update_info.top = msmfb->yres + 1; | ||
152 | msmfb->update_info.eright = 0; | ||
153 | msmfb->update_info.ebottom = 0; | ||
154 | if (unlikely(w > msmfb->xres || h > msmfb->yres || | ||
155 | w == 0 || h == 0)) { | ||
156 | printk(KERN_INFO "invalid update: %d %d %d " | ||
157 | "%d\n", x, y, w, h); | ||
158 | msmfb->frame_done = msmfb->frame_requested; | ||
159 | goto error; | ||
160 | } | ||
161 | spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); | ||
162 | |||
163 | addr = ((msmfb->xres * (yoffset + y) + x) * 2); | ||
164 | mdp->dma(mdp, addr + msmfb->fb->fix.smem_start, | ||
165 | msmfb->xres * 2, w, h, x, y, &msmfb->dma_callback, | ||
166 | panel->interface_type); | ||
167 | return 0; | ||
168 | error: | ||
169 | spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); | ||
170 | /* some clients need to clear their vsync interrupt */ | ||
171 | if (panel->clear_vsync) | ||
172 | panel->clear_vsync(panel); | ||
173 | wake_up(&msmfb->frame_wq); | ||
174 | return 0; | ||
175 | } | ||
176 | |||
177 | /* Called from esync interrupt handler, must not sleep */ | ||
178 | static void msmfb_handle_vsync_interrupt(struct msmfb_callback *callback) | ||
179 | { | ||
180 | struct msmfb_info *msmfb = container_of(callback, struct msmfb_info, | ||
181 | vsync_callback); | ||
182 | msmfb_start_dma(msmfb); | ||
183 | } | ||
184 | |||
185 | static enum hrtimer_restart msmfb_fake_vsync(struct hrtimer *timer) | ||
186 | { | ||
187 | struct msmfb_info *msmfb = container_of(timer, struct msmfb_info, | ||
188 | fake_vsync); | ||
189 | msmfb_start_dma(msmfb); | ||
190 | return HRTIMER_NORESTART; | ||
191 | } | ||
192 | |||
193 | static void msmfb_pan_update(struct fb_info *info, uint32_t left, uint32_t top, | ||
194 | uint32_t eright, uint32_t ebottom, | ||
195 | uint32_t yoffset, int pan_display) | ||
196 | { | ||
197 | struct msmfb_info *msmfb = info->par; | ||
198 | struct msm_panel_data *panel = msmfb->panel; | ||
199 | unsigned long irq_flags; | ||
200 | int sleeping; | ||
201 | int retry = 1; | ||
202 | |||
203 | DLOG(SHOW_UPDATES, "update %d %d %d %d %d %d\n", | ||
204 | left, top, eright, ebottom, yoffset, pan_display); | ||
205 | restart: | ||
206 | spin_lock_irqsave(&msmfb->update_lock, irq_flags); | ||
207 | |||
208 | /* if we are sleeping, on a pan_display wait 10ms (to throttle back | ||
209 | * drawing otherwise return */ | ||
210 | if (msmfb->sleeping == SLEEPING) { | ||
211 | DLOG(SUSPEND_RESUME, "drawing while asleep\n"); | ||
212 | spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); | ||
213 | if (pan_display) | ||
214 | wait_event_interruptible_timeout(msmfb->frame_wq, | ||
215 | msmfb->sleeping != SLEEPING, HZ/10); | ||
216 | return; | ||
217 | } | ||
218 | |||
219 | sleeping = msmfb->sleeping; | ||
220 | /* on a full update, if the last frame has not completed, wait for it */ | ||
221 | if ((pan_display && msmfb->frame_requested != msmfb->frame_done) || | ||
222 | sleeping == UPDATING) { | ||
223 | int ret; | ||
224 | spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); | ||
225 | ret = wait_event_interruptible_timeout(msmfb->frame_wq, | ||
226 | msmfb->frame_done == msmfb->frame_requested && | ||
227 | msmfb->sleeping != UPDATING, 5 * HZ); | ||
228 | if (ret <= 0 && (msmfb->frame_requested != msmfb->frame_done || | ||
229 | msmfb->sleeping == UPDATING)) { | ||
230 | if (retry && panel->request_vsync && | ||
231 | (sleeping == AWAKE)) { | ||
232 | panel->request_vsync(panel, | ||
233 | &msmfb->vsync_callback); | ||
234 | retry = 0; | ||
235 | printk(KERN_WARNING "msmfb_pan_display timeout " | ||
236 | "rerequest vsync\n"); | ||
237 | } else { | ||
238 | printk(KERN_WARNING "msmfb_pan_display timeout " | ||
239 | "waiting for frame start, %d %d\n", | ||
240 | msmfb->frame_requested, | ||
241 | msmfb->frame_done); | ||
242 | return; | ||
243 | } | ||
244 | } | ||
245 | goto restart; | ||
246 | } | ||
247 | |||
248 | |||
249 | msmfb->frame_requested++; | ||
250 | /* if necessary, update the y offset, if this is the | ||
251 | * first full update on resume, set the sleeping state */ | ||
252 | if (pan_display) { | ||
253 | msmfb->yoffset = yoffset; | ||
254 | if (left == 0 && top == 0 && eright == info->var.xres && | ||
255 | ebottom == info->var.yres) { | ||
256 | if (sleeping == WAKING) { | ||
257 | msmfb->update_frame = msmfb->frame_requested; | ||
258 | DLOG(SUSPEND_RESUME, "full update starting\n"); | ||
259 | msmfb->sleeping = UPDATING; | ||
260 | } | ||
261 | } | ||
262 | } | ||
263 | |||
264 | /* set the update request */ | ||
265 | if (left < msmfb->update_info.left) | ||
266 | msmfb->update_info.left = left; | ||
267 | if (top < msmfb->update_info.top) | ||
268 | msmfb->update_info.top = top; | ||
269 | if (eright > msmfb->update_info.eright) | ||
270 | msmfb->update_info.eright = eright; | ||
271 | if (ebottom > msmfb->update_info.ebottom) | ||
272 | msmfb->update_info.ebottom = ebottom; | ||
273 | DLOG(SHOW_UPDATES, "update queued %d %d %d %d %d\n", | ||
274 | msmfb->update_info.left, msmfb->update_info.top, | ||
275 | msmfb->update_info.eright, msmfb->update_info.ebottom, | ||
276 | msmfb->yoffset); | ||
277 | spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); | ||
278 | |||
279 | /* if the panel is all the way on wait for vsync, otherwise sleep | ||
280 | * for 16 ms (long enough for the dma to panel) and then begin dma */ | ||
281 | msmfb->vsync_request_time = ktime_get(); | ||
282 | if (panel->request_vsync && (sleeping == AWAKE)) { | ||
283 | panel->request_vsync(panel, &msmfb->vsync_callback); | ||
284 | } else { | ||
285 | if (!hrtimer_active(&msmfb->fake_vsync)) { | ||
286 | hrtimer_start(&msmfb->fake_vsync, | ||
287 | ktime_set(0, NSEC_PER_SEC/60), | ||
288 | HRTIMER_MODE_REL); | ||
289 | } | ||
290 | } | ||
291 | } | ||
292 | |||
293 | static void msmfb_update(struct fb_info *info, uint32_t left, uint32_t top, | ||
294 | uint32_t eright, uint32_t ebottom) | ||
295 | { | ||
296 | msmfb_pan_update(info, left, top, eright, ebottom, 0, 0); | ||
297 | } | ||
298 | |||
299 | static void power_on_panel(struct work_struct *work) | ||
300 | { | ||
301 | struct msmfb_info *msmfb = | ||
302 | container_of(work, struct msmfb_info, resume_work); | ||
303 | struct msm_panel_data *panel = msmfb->panel; | ||
304 | unsigned long irq_flags; | ||
305 | |||
306 | mutex_lock(&msmfb->panel_init_lock); | ||
307 | DLOG(SUSPEND_RESUME, "turning on panel\n"); | ||
308 | if (msmfb->sleeping == UPDATING) { | ||
309 | if (panel->unblank(panel)) { | ||
310 | printk(KERN_INFO "msmfb: panel unblank failed," | ||
311 | "not starting drawing\n"); | ||
312 | goto error; | ||
313 | } | ||
314 | spin_lock_irqsave(&msmfb->update_lock, irq_flags); | ||
315 | msmfb->sleeping = AWAKE; | ||
316 | wake_up(&msmfb->frame_wq); | ||
317 | spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); | ||
318 | } | ||
319 | error: | ||
320 | mutex_unlock(&msmfb->panel_init_lock); | ||
321 | } | ||
322 | |||
323 | |||
324 | static int msmfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | ||
325 | { | ||
326 | if ((var->xres != info->var.xres) || | ||
327 | (var->yres != info->var.yres) || | ||
328 | (var->xres_virtual != info->var.xres_virtual) || | ||
329 | (var->yres_virtual != info->var.yres_virtual) || | ||
330 | (var->xoffset != info->var.xoffset) || | ||
331 | (var->bits_per_pixel != info->var.bits_per_pixel) || | ||
332 | (var->grayscale != info->var.grayscale)) | ||
333 | return -EINVAL; | ||
334 | return 0; | ||
335 | } | ||
336 | |||
337 | int msmfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | ||
338 | { | ||
339 | struct msmfb_info *msmfb = info->par; | ||
340 | struct msm_panel_data *panel = msmfb->panel; | ||
341 | |||
342 | /* "UPDT" */ | ||
343 | if ((panel->caps & MSMFB_CAP_PARTIAL_UPDATES) && | ||
344 | (var->reserved[0] == 0x54445055)) { | ||
345 | msmfb_pan_update(info, var->reserved[1] & 0xffff, | ||
346 | var->reserved[1] >> 16, | ||
347 | var->reserved[2] & 0xffff, | ||
348 | var->reserved[2] >> 16, var->yoffset, 1); | ||
349 | } else { | ||
350 | msmfb_pan_update(info, 0, 0, info->var.xres, info->var.yres, | ||
351 | var->yoffset, 1); | ||
352 | } | ||
353 | return 0; | ||
354 | } | ||
355 | |||
356 | static void msmfb_fillrect(struct fb_info *p, const struct fb_fillrect *rect) | ||
357 | { | ||
358 | cfb_fillrect(p, rect); | ||
359 | msmfb_update(p, rect->dx, rect->dy, rect->dx + rect->width, | ||
360 | rect->dy + rect->height); | ||
361 | } | ||
362 | |||
363 | static void msmfb_copyarea(struct fb_info *p, const struct fb_copyarea *area) | ||
364 | { | ||
365 | cfb_copyarea(p, area); | ||
366 | msmfb_update(p, area->dx, area->dy, area->dx + area->width, | ||
367 | area->dy + area->height); | ||
368 | } | ||
369 | |||
370 | static void msmfb_imageblit(struct fb_info *p, const struct fb_image *image) | ||
371 | { | ||
372 | cfb_imageblit(p, image); | ||
373 | msmfb_update(p, image->dx, image->dy, image->dx + image->width, | ||
374 | image->dy + image->height); | ||
375 | } | ||
376 | |||
377 | |||
378 | static int msmfb_blit(struct fb_info *info, | ||
379 | void __user *p) | ||
380 | { | ||
381 | struct mdp_blit_req req; | ||
382 | struct mdp_blit_req_list req_list; | ||
383 | int i; | ||
384 | int ret; | ||
385 | |||
386 | if (copy_from_user(&req_list, p, sizeof(req_list))) | ||
387 | return -EFAULT; | ||
388 | |||
389 | for (i = 0; i < req_list.count; i++) { | ||
390 | struct mdp_blit_req_list *list = | ||
391 | (struct mdp_blit_req_list *)p; | ||
392 | if (copy_from_user(&req, &list->req[i], sizeof(req))) | ||
393 | return -EFAULT; | ||
394 | ret = mdp->blit(mdp, info, &req); | ||
395 | if (ret) | ||
396 | return ret; | ||
397 | } | ||
398 | return 0; | ||
399 | } | ||
400 | |||
401 | |||
402 | DEFINE_MUTEX(mdp_ppp_lock); | ||
403 | |||
404 | static int msmfb_ioctl(struct fb_info *p, unsigned int cmd, unsigned long arg) | ||
405 | { | ||
406 | void __user *argp = (void __user *)arg; | ||
407 | int ret; | ||
408 | |||
409 | switch (cmd) { | ||
410 | case MSMFB_GRP_DISP: | ||
411 | mdp->set_grp_disp(mdp, arg); | ||
412 | break; | ||
413 | case MSMFB_BLIT: | ||
414 | ret = msmfb_blit(p, argp); | ||
415 | if (ret) | ||
416 | return ret; | ||
417 | break; | ||
418 | default: | ||
419 | printk(KERN_INFO "msmfb unknown ioctl: %d\n", cmd); | ||
420 | return -EINVAL; | ||
421 | } | ||
422 | return 0; | ||
423 | } | ||
424 | |||
425 | static struct fb_ops msmfb_ops = { | ||
426 | .owner = THIS_MODULE, | ||
427 | .fb_open = msmfb_open, | ||
428 | .fb_release = msmfb_release, | ||
429 | .fb_check_var = msmfb_check_var, | ||
430 | .fb_pan_display = msmfb_pan_display, | ||
431 | .fb_fillrect = msmfb_fillrect, | ||
432 | .fb_copyarea = msmfb_copyarea, | ||
433 | .fb_imageblit = msmfb_imageblit, | ||
434 | .fb_ioctl = msmfb_ioctl, | ||
435 | }; | ||
436 | |||
437 | static unsigned PP[16]; | ||
438 | |||
439 | |||
440 | |||
441 | #define BITS_PER_PIXEL 16 | ||
442 | |||
443 | static void setup_fb_info(struct msmfb_info *msmfb) | ||
444 | { | ||
445 | struct fb_info *fb_info = msmfb->fb; | ||
446 | int r; | ||
447 | |||
448 | /* finish setting up the fb_info struct */ | ||
449 | strncpy(fb_info->fix.id, "msmfb", 16); | ||
450 | fb_info->fix.ypanstep = 1; | ||
451 | |||
452 | fb_info->fbops = &msmfb_ops; | ||
453 | fb_info->flags = FBINFO_DEFAULT; | ||
454 | |||
455 | fb_info->fix.type = FB_TYPE_PACKED_PIXELS; | ||
456 | fb_info->fix.visual = FB_VISUAL_TRUECOLOR; | ||
457 | fb_info->fix.line_length = msmfb->xres * 2; | ||
458 | |||
459 | fb_info->var.xres = msmfb->xres; | ||
460 | fb_info->var.yres = msmfb->yres; | ||
461 | fb_info->var.width = msmfb->panel->fb_data->width; | ||
462 | fb_info->var.height = msmfb->panel->fb_data->height; | ||
463 | fb_info->var.xres_virtual = msmfb->xres; | ||
464 | fb_info->var.yres_virtual = msmfb->yres * 2; | ||
465 | fb_info->var.bits_per_pixel = BITS_PER_PIXEL; | ||
466 | fb_info->var.accel_flags = 0; | ||
467 | |||
468 | fb_info->var.yoffset = 0; | ||
469 | |||
470 | if (msmfb->panel->caps & MSMFB_CAP_PARTIAL_UPDATES) { | ||
471 | /* | ||
472 | * Set the param in the fixed screen, so userspace can't | ||
473 | * change it. This will be used to check for the | ||
474 | * capability. | ||
475 | */ | ||
476 | fb_info->fix.reserved[0] = 0x5444; | ||
477 | fb_info->fix.reserved[1] = 0x5055; | ||
478 | |||
479 | /* | ||
480 | * This preloads the value so that if userspace doesn't | ||
481 | * change it, it will be a full update | ||
482 | */ | ||
483 | fb_info->var.reserved[0] = 0x54445055; | ||
484 | fb_info->var.reserved[1] = 0; | ||
485 | fb_info->var.reserved[2] = (uint16_t)msmfb->xres | | ||
486 | ((uint32_t)msmfb->yres << 16); | ||
487 | } | ||
488 | |||
489 | fb_info->var.red.offset = 11; | ||
490 | fb_info->var.red.length = 5; | ||
491 | fb_info->var.red.msb_right = 0; | ||
492 | fb_info->var.green.offset = 5; | ||
493 | fb_info->var.green.length = 6; | ||
494 | fb_info->var.green.msb_right = 0; | ||
495 | fb_info->var.blue.offset = 0; | ||
496 | fb_info->var.blue.length = 5; | ||
497 | fb_info->var.blue.msb_right = 0; | ||
498 | |||
499 | r = fb_alloc_cmap(&fb_info->cmap, 16, 0); | ||
500 | fb_info->pseudo_palette = PP; | ||
501 | |||
502 | PP[0] = 0; | ||
503 | for (r = 1; r < 16; r++) | ||
504 | PP[r] = 0xffffffff; | ||
505 | } | ||
506 | |||
507 | static int setup_fbmem(struct msmfb_info *msmfb, struct platform_device *pdev) | ||
508 | { | ||
509 | struct fb_info *fb = msmfb->fb; | ||
510 | struct resource *resource; | ||
511 | unsigned long size = msmfb->xres * msmfb->yres * | ||
512 | (BITS_PER_PIXEL >> 3) * 2; | ||
513 | unsigned char *fbram; | ||
514 | |||
515 | /* board file might have attached a resource describing an fb */ | ||
516 | resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
517 | if (!resource) | ||
518 | return -EINVAL; | ||
519 | |||
520 | /* check the resource is large enough to fit the fb */ | ||
521 | if (resource->end - resource->start < size) { | ||
522 | printk(KERN_ERR "allocated resource is too small for " | ||
523 | "fb\n"); | ||
524 | return -ENOMEM; | ||
525 | } | ||
526 | fb->fix.smem_start = resource->start; | ||
527 | fb->fix.smem_len = resource_size(resource); | ||
528 | fbram = ioremap(resource->start, resource_size(resource)); | ||
529 | if (fbram == NULL) { | ||
530 | printk(KERN_ERR "msmfb: cannot allocate fbram!\n"); | ||
531 | return -ENOMEM; | ||
532 | } | ||
533 | fb->screen_base = fbram; | ||
534 | return 0; | ||
535 | } | ||
536 | |||
537 | static int msmfb_probe(struct platform_device *pdev) | ||
538 | { | ||
539 | struct fb_info *fb; | ||
540 | struct msmfb_info *msmfb; | ||
541 | struct msm_panel_data *panel = pdev->dev.platform_data; | ||
542 | int ret; | ||
543 | |||
544 | if (!panel) { | ||
545 | pr_err("msmfb_probe: no platform data\n"); | ||
546 | return -EINVAL; | ||
547 | } | ||
548 | if (!panel->fb_data) { | ||
549 | pr_err("msmfb_probe: no fb_data\n"); | ||
550 | return -EINVAL; | ||
551 | } | ||
552 | |||
553 | fb = framebuffer_alloc(sizeof(struct msmfb_info), &pdev->dev); | ||
554 | if (!fb) | ||
555 | return -ENOMEM; | ||
556 | msmfb = fb->par; | ||
557 | msmfb->fb = fb; | ||
558 | msmfb->panel = panel; | ||
559 | msmfb->xres = panel->fb_data->xres; | ||
560 | msmfb->yres = panel->fb_data->yres; | ||
561 | |||
562 | ret = setup_fbmem(msmfb, pdev); | ||
563 | if (ret) | ||
564 | goto error_setup_fbmem; | ||
565 | |||
566 | setup_fb_info(msmfb); | ||
567 | |||
568 | spin_lock_init(&msmfb->update_lock); | ||
569 | mutex_init(&msmfb->panel_init_lock); | ||
570 | init_waitqueue_head(&msmfb->frame_wq); | ||
571 | INIT_WORK(&msmfb->resume_work, power_on_panel); | ||
572 | msmfb->black = devm_kzalloc(&pdev->dev, | ||
573 | msmfb->fb->var.bits_per_pixel*msmfb->xres, | ||
574 | GFP_KERNEL); | ||
575 | if (!msmfb->black) { | ||
576 | ret = -ENOMEM; | ||
577 | goto error_register_framebuffer; | ||
578 | } | ||
579 | |||
580 | printk(KERN_INFO "msmfb_probe() installing %d x %d panel\n", | ||
581 | msmfb->xres, msmfb->yres); | ||
582 | |||
583 | msmfb->dma_callback.func = msmfb_handle_dma_interrupt; | ||
584 | msmfb->vsync_callback.func = msmfb_handle_vsync_interrupt; | ||
585 | hrtimer_init(&msmfb->fake_vsync, CLOCK_MONOTONIC, | ||
586 | HRTIMER_MODE_REL); | ||
587 | |||
588 | |||
589 | msmfb->fake_vsync.function = msmfb_fake_vsync; | ||
590 | |||
591 | ret = register_framebuffer(fb); | ||
592 | if (ret) | ||
593 | goto error_register_framebuffer; | ||
594 | |||
595 | msmfb->sleeping = WAKING; | ||
596 | |||
597 | platform_set_drvdata(pdev, msmfb); | ||
598 | |||
599 | return 0; | ||
600 | |||
601 | error_register_framebuffer: | ||
602 | iounmap(fb->screen_base); | ||
603 | error_setup_fbmem: | ||
604 | framebuffer_release(msmfb->fb); | ||
605 | return ret; | ||
606 | } | ||
607 | |||
608 | static int msmfb_remove(struct platform_device *pdev) | ||
609 | { | ||
610 | struct msmfb_info *msmfb; | ||
611 | |||
612 | msmfb = platform_get_drvdata(pdev); | ||
613 | |||
614 | unregister_framebuffer(msmfb->fb); | ||
615 | iounmap(msmfb->fb->screen_base); | ||
616 | framebuffer_release(msmfb->fb); | ||
617 | |||
618 | return 0; | ||
619 | } | ||
620 | |||
621 | static struct platform_driver msm_panel_driver = { | ||
622 | /* need to write remove */ | ||
623 | .probe = msmfb_probe, | ||
624 | .remove = msmfb_remove, | ||
625 | .driver = {.name = "msm_panel"}, | ||
626 | }; | ||
627 | |||
628 | |||
629 | static int msmfb_add_mdp_device(struct device *dev, | ||
630 | struct class_interface *class_intf) | ||
631 | { | ||
632 | /* might need locking if mulitple mdp devices */ | ||
633 | if (mdp) | ||
634 | return 0; | ||
635 | mdp = container_of(dev, struct mdp_device, dev); | ||
636 | return platform_driver_register(&msm_panel_driver); | ||
637 | } | ||
638 | |||
639 | static void msmfb_remove_mdp_device(struct device *dev, | ||
640 | struct class_interface *class_intf) | ||
641 | { | ||
642 | /* might need locking if mulitple mdp devices */ | ||
643 | if (dev != &mdp->dev) | ||
644 | return; | ||
645 | platform_driver_unregister(&msm_panel_driver); | ||
646 | mdp = NULL; | ||
647 | } | ||
648 | |||
649 | static struct class_interface msm_fb_interface = { | ||
650 | .add_dev = &msmfb_add_mdp_device, | ||
651 | .remove_dev = &msmfb_remove_mdp_device, | ||
652 | }; | ||
653 | |||
654 | static int __init msmfb_init(void) | ||
655 | { | ||
656 | return register_mdp_client(&msm_fb_interface); | ||
657 | } | ||
658 | |||
659 | module_init(msmfb_init); | ||
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c index f8ac4a452f26..4e6608ceac09 100644 --- a/drivers/video/fbdev/mxsfb.c +++ b/drivers/video/fbdev/mxsfb.c | |||
@@ -316,6 +316,18 @@ static int mxsfb_check_var(struct fb_var_screeninfo *var, | |||
316 | return 0; | 316 | return 0; |
317 | } | 317 | } |
318 | 318 | ||
319 | static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host) | ||
320 | { | ||
321 | if (host->clk_axi) | ||
322 | clk_prepare_enable(host->clk_axi); | ||
323 | } | ||
324 | |||
325 | static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host) | ||
326 | { | ||
327 | if (host->clk_axi) | ||
328 | clk_disable_unprepare(host->clk_axi); | ||
329 | } | ||
330 | |||
319 | static void mxsfb_enable_controller(struct fb_info *fb_info) | 331 | static void mxsfb_enable_controller(struct fb_info *fb_info) |
320 | { | 332 | { |
321 | struct mxsfb_info *host = to_imxfb_host(fb_info); | 333 | struct mxsfb_info *host = to_imxfb_host(fb_info); |
@@ -333,14 +345,13 @@ static void mxsfb_enable_controller(struct fb_info *fb_info) | |||
333 | } | 345 | } |
334 | } | 346 | } |
335 | 347 | ||
336 | if (host->clk_axi) | ||
337 | clk_prepare_enable(host->clk_axi); | ||
338 | |||
339 | if (host->clk_disp_axi) | 348 | if (host->clk_disp_axi) |
340 | clk_prepare_enable(host->clk_disp_axi); | 349 | clk_prepare_enable(host->clk_disp_axi); |
341 | clk_prepare_enable(host->clk); | 350 | clk_prepare_enable(host->clk); |
342 | clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U); | 351 | clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U); |
343 | 352 | ||
353 | mxsfb_enable_axi_clk(host); | ||
354 | |||
344 | /* if it was disabled, re-enable the mode again */ | 355 | /* if it was disabled, re-enable the mode again */ |
345 | writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); | 356 | writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); |
346 | 357 | ||
@@ -380,11 +391,11 @@ static void mxsfb_disable_controller(struct fb_info *fb_info) | |||
380 | reg = readl(host->base + LCDC_VDCTRL4); | 391 | reg = readl(host->base + LCDC_VDCTRL4); |
381 | writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4); | 392 | writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4); |
382 | 393 | ||
394 | mxsfb_disable_axi_clk(host); | ||
395 | |||
383 | clk_disable_unprepare(host->clk); | 396 | clk_disable_unprepare(host->clk); |
384 | if (host->clk_disp_axi) | 397 | if (host->clk_disp_axi) |
385 | clk_disable_unprepare(host->clk_disp_axi); | 398 | clk_disable_unprepare(host->clk_disp_axi); |
386 | if (host->clk_axi) | ||
387 | clk_disable_unprepare(host->clk_axi); | ||
388 | 399 | ||
389 | host->enabled = 0; | 400 | host->enabled = 0; |
390 | 401 | ||
@@ -421,6 +432,8 @@ static int mxsfb_set_par(struct fb_info *fb_info) | |||
421 | mxsfb_disable_controller(fb_info); | 432 | mxsfb_disable_controller(fb_info); |
422 | } | 433 | } |
423 | 434 | ||
435 | mxsfb_enable_axi_clk(host); | ||
436 | |||
424 | /* clear the FIFOs */ | 437 | /* clear the FIFOs */ |
425 | writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); | 438 | writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); |
426 | 439 | ||
@@ -438,6 +451,7 @@ static int mxsfb_set_par(struct fb_info *fb_info) | |||
438 | ctrl |= CTRL_SET_WORD_LENGTH(3); | 451 | ctrl |= CTRL_SET_WORD_LENGTH(3); |
439 | switch (host->ld_intf_width) { | 452 | switch (host->ld_intf_width) { |
440 | case STMLCDIF_8BIT: | 453 | case STMLCDIF_8BIT: |
454 | mxsfb_disable_axi_clk(host); | ||
441 | dev_err(&host->pdev->dev, | 455 | dev_err(&host->pdev->dev, |
442 | "Unsupported LCD bus width mapping\n"); | 456 | "Unsupported LCD bus width mapping\n"); |
443 | return -EINVAL; | 457 | return -EINVAL; |
@@ -451,6 +465,7 @@ static int mxsfb_set_par(struct fb_info *fb_info) | |||
451 | writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); | 465 | writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); |
452 | break; | 466 | break; |
453 | default: | 467 | default: |
468 | mxsfb_disable_axi_clk(host); | ||
454 | dev_err(&host->pdev->dev, "Unhandled color depth of %u\n", | 469 | dev_err(&host->pdev->dev, "Unhandled color depth of %u\n", |
455 | fb_info->var.bits_per_pixel); | 470 | fb_info->var.bits_per_pixel); |
456 | return -EINVAL; | 471 | return -EINVAL; |
@@ -504,6 +519,8 @@ static int mxsfb_set_par(struct fb_info *fb_info) | |||
504 | fb_info->fix.line_length * fb_info->var.yoffset, | 519 | fb_info->fix.line_length * fb_info->var.yoffset, |
505 | host->base + host->devdata->next_buf); | 520 | host->base + host->devdata->next_buf); |
506 | 521 | ||
522 | mxsfb_disable_axi_clk(host); | ||
523 | |||
507 | if (reenable) | 524 | if (reenable) |
508 | mxsfb_enable_controller(fb_info); | 525 | mxsfb_enable_controller(fb_info); |
509 | 526 | ||
@@ -582,10 +599,14 @@ static int mxsfb_pan_display(struct fb_var_screeninfo *var, | |||
582 | 599 | ||
583 | offset = fb_info->fix.line_length * var->yoffset; | 600 | offset = fb_info->fix.line_length * var->yoffset; |
584 | 601 | ||
602 | mxsfb_enable_axi_clk(host); | ||
603 | |||
585 | /* update on next VSYNC */ | 604 | /* update on next VSYNC */ |
586 | writel(fb_info->fix.smem_start + offset, | 605 | writel(fb_info->fix.smem_start + offset, |
587 | host->base + host->devdata->next_buf); | 606 | host->base + host->devdata->next_buf); |
588 | 607 | ||
608 | mxsfb_disable_axi_clk(host); | ||
609 | |||
589 | return 0; | 610 | return 0; |
590 | } | 611 | } |
591 | 612 | ||
@@ -608,13 +629,17 @@ static int mxsfb_restore_mode(struct mxsfb_info *host, | |||
608 | unsigned line_count; | 629 | unsigned line_count; |
609 | unsigned period; | 630 | unsigned period; |
610 | unsigned long pa, fbsize; | 631 | unsigned long pa, fbsize; |
611 | int bits_per_pixel, ofs; | 632 | int bits_per_pixel, ofs, ret = 0; |
612 | u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; | 633 | u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; |
613 | 634 | ||
635 | mxsfb_enable_axi_clk(host); | ||
636 | |||
614 | /* Only restore the mode when the controller is running */ | 637 | /* Only restore the mode when the controller is running */ |
615 | ctrl = readl(host->base + LCDC_CTRL); | 638 | ctrl = readl(host->base + LCDC_CTRL); |
616 | if (!(ctrl & CTRL_RUN)) | 639 | if (!(ctrl & CTRL_RUN)) { |
617 | return -EINVAL; | 640 | ret = -EINVAL; |
641 | goto err; | ||
642 | } | ||
618 | 643 | ||
619 | vdctrl0 = readl(host->base + LCDC_VDCTRL0); | 644 | vdctrl0 = readl(host->base + LCDC_VDCTRL0); |
620 | vdctrl2 = readl(host->base + LCDC_VDCTRL2); | 645 | vdctrl2 = readl(host->base + LCDC_VDCTRL2); |
@@ -635,7 +660,8 @@ static int mxsfb_restore_mode(struct mxsfb_info *host, | |||
635 | break; | 660 | break; |
636 | case 1: | 661 | case 1: |
637 | default: | 662 | default: |
638 | return -EINVAL; | 663 | ret = -EINVAL; |
664 | goto err; | ||
639 | } | 665 | } |
640 | 666 | ||
641 | fb_info->var.bits_per_pixel = bits_per_pixel; | 667 | fb_info->var.bits_per_pixel = bits_per_pixel; |
@@ -673,10 +699,14 @@ static int mxsfb_restore_mode(struct mxsfb_info *host, | |||
673 | 699 | ||
674 | pa = readl(host->base + host->devdata->cur_buf); | 700 | pa = readl(host->base + host->devdata->cur_buf); |
675 | fbsize = fb_info->fix.line_length * vmode->yres; | 701 | fbsize = fb_info->fix.line_length * vmode->yres; |
676 | if (pa < fb_info->fix.smem_start) | 702 | if (pa < fb_info->fix.smem_start) { |
677 | return -EINVAL; | 703 | ret = -EINVAL; |
678 | if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) | 704 | goto err; |
679 | return -EINVAL; | 705 | } |
706 | if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) { | ||
707 | ret = -EINVAL; | ||
708 | goto err; | ||
709 | } | ||
680 | ofs = pa - fb_info->fix.smem_start; | 710 | ofs = pa - fb_info->fix.smem_start; |
681 | if (ofs) { | 711 | if (ofs) { |
682 | memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize); | 712 | memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize); |
@@ -689,7 +719,11 @@ static int mxsfb_restore_mode(struct mxsfb_info *host, | |||
689 | clk_prepare_enable(host->clk); | 719 | clk_prepare_enable(host->clk); |
690 | host->enabled = 1; | 720 | host->enabled = 1; |
691 | 721 | ||
692 | return 0; | 722 | err: |
723 | if (ret) | ||
724 | mxsfb_disable_axi_clk(host); | ||
725 | |||
726 | return ret; | ||
693 | } | 727 | } |
694 | 728 | ||
695 | static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host, | 729 | static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host, |
@@ -814,7 +848,7 @@ static void mxsfb_free_videomem(struct mxsfb_info *host) | |||
814 | free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len); | 848 | free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len); |
815 | } | 849 | } |
816 | 850 | ||
817 | static struct platform_device_id mxsfb_devtype[] = { | 851 | static const struct platform_device_id mxsfb_devtype[] = { |
818 | { | 852 | { |
819 | .name = "imx23-fb", | 853 | .name = "imx23-fb", |
820 | .driver_data = MXSFB_V3, | 854 | .driver_data = MXSFB_V3, |
@@ -915,7 +949,9 @@ static int mxsfb_probe(struct platform_device *pdev) | |||
915 | } | 949 | } |
916 | 950 | ||
917 | if (!host->enabled) { | 951 | if (!host->enabled) { |
952 | mxsfb_enable_axi_clk(host); | ||
918 | writel(0, host->base + LCDC_CTRL); | 953 | writel(0, host->base + LCDC_CTRL); |
954 | mxsfb_disable_axi_clk(host); | ||
919 | mxsfb_set_par(fb_info); | 955 | mxsfb_set_par(fb_info); |
920 | mxsfb_enable_controller(fb_info); | 956 | mxsfb_enable_controller(fb_info); |
921 | } | 957 | } |
@@ -954,11 +990,15 @@ static void mxsfb_shutdown(struct platform_device *pdev) | |||
954 | struct fb_info *fb_info = platform_get_drvdata(pdev); | 990 | struct fb_info *fb_info = platform_get_drvdata(pdev); |
955 | struct mxsfb_info *host = to_imxfb_host(fb_info); | 991 | struct mxsfb_info *host = to_imxfb_host(fb_info); |
956 | 992 | ||
993 | mxsfb_enable_axi_clk(host); | ||
994 | |||
957 | /* | 995 | /* |
958 | * Force stop the LCD controller as keeping it running during reboot | 996 | * Force stop the LCD controller as keeping it running during reboot |
959 | * might interfere with the BootROM's boot mode pads sampling. | 997 | * might interfere with the BootROM's boot mode pads sampling. |
960 | */ | 998 | */ |
961 | writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR); | 999 | writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR); |
1000 | |||
1001 | mxsfb_disable_axi_clk(host); | ||
962 | } | 1002 | } |
963 | 1003 | ||
964 | static struct platform_driver mxsfb_driver = { | 1004 | static struct platform_driver mxsfb_driver = { |
diff --git a/drivers/video/fbdev/neofb.c b/drivers/video/fbdev/neofb.c index 44f99a60bb9b..db023a97d1ea 100644 --- a/drivers/video/fbdev/neofb.c +++ b/drivers/video/fbdev/neofb.c | |||
@@ -71,11 +71,6 @@ | |||
71 | #include <asm/io.h> | 71 | #include <asm/io.h> |
72 | #include <asm/irq.h> | 72 | #include <asm/irq.h> |
73 | #include <asm/pgtable.h> | 73 | #include <asm/pgtable.h> |
74 | |||
75 | #ifdef CONFIG_MTRR | ||
76 | #include <asm/mtrr.h> | ||
77 | #endif | ||
78 | |||
79 | #include <video/vga.h> | 74 | #include <video/vga.h> |
80 | #include <video/neomagic.h> | 75 | #include <video/neomagic.h> |
81 | 76 | ||
@@ -1710,6 +1705,7 @@ static int neo_map_video(struct fb_info *info, struct pci_dev *dev, | |||
1710 | int video_len) | 1705 | int video_len) |
1711 | { | 1706 | { |
1712 | //unsigned long addr; | 1707 | //unsigned long addr; |
1708 | struct neofb_par *par = info->par; | ||
1713 | 1709 | ||
1714 | DBG("neo_map_video"); | 1710 | DBG("neo_map_video"); |
1715 | 1711 | ||
@@ -1723,7 +1719,7 @@ static int neo_map_video(struct fb_info *info, struct pci_dev *dev, | |||
1723 | } | 1719 | } |
1724 | 1720 | ||
1725 | info->screen_base = | 1721 | info->screen_base = |
1726 | ioremap(info->fix.smem_start, info->fix.smem_len); | 1722 | ioremap_wc(info->fix.smem_start, info->fix.smem_len); |
1727 | if (!info->screen_base) { | 1723 | if (!info->screen_base) { |
1728 | printk("neofb: unable to map screen memory\n"); | 1724 | printk("neofb: unable to map screen memory\n"); |
1729 | release_mem_region(info->fix.smem_start, | 1725 | release_mem_region(info->fix.smem_start, |
@@ -1733,11 +1729,8 @@ static int neo_map_video(struct fb_info *info, struct pci_dev *dev, | |||
1733 | printk(KERN_INFO "neofb: mapped framebuffer at %p\n", | 1729 | printk(KERN_INFO "neofb: mapped framebuffer at %p\n", |
1734 | info->screen_base); | 1730 | info->screen_base); |
1735 | 1731 | ||
1736 | #ifdef CONFIG_MTRR | 1732 | par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, |
1737 | ((struct neofb_par *)(info->par))->mtrr = | 1733 | pci_resource_len(dev, 0)); |
1738 | mtrr_add(info->fix.smem_start, pci_resource_len(dev, 0), | ||
1739 | MTRR_TYPE_WRCOMB, 1); | ||
1740 | #endif | ||
1741 | 1734 | ||
1742 | /* Clear framebuffer, it's all white in memory after boot */ | 1735 | /* Clear framebuffer, it's all white in memory after boot */ |
1743 | memset_io(info->screen_base, 0, info->fix.smem_len); | 1736 | memset_io(info->screen_base, 0, info->fix.smem_len); |
@@ -1754,16 +1747,11 @@ static int neo_map_video(struct fb_info *info, struct pci_dev *dev, | |||
1754 | 1747 | ||
1755 | static void neo_unmap_video(struct fb_info *info) | 1748 | static void neo_unmap_video(struct fb_info *info) |
1756 | { | 1749 | { |
1757 | DBG("neo_unmap_video"); | 1750 | struct neofb_par *par = info->par; |
1758 | 1751 | ||
1759 | #ifdef CONFIG_MTRR | 1752 | DBG("neo_unmap_video"); |
1760 | { | ||
1761 | struct neofb_par *par = info->par; | ||
1762 | 1753 | ||
1763 | mtrr_del(par->mtrr, info->fix.smem_start, | 1754 | arch_phys_wc_del(par->wc_cookie); |
1764 | info->fix.smem_len); | ||
1765 | } | ||
1766 | #endif | ||
1767 | iounmap(info->screen_base); | 1755 | iounmap(info->screen_base); |
1768 | info->screen_base = NULL; | 1756 | info->screen_base = NULL; |
1769 | 1757 | ||
diff --git a/drivers/video/fbdev/nvidia/nv_type.h b/drivers/video/fbdev/nvidia/nv_type.h index c03f7f55c76d..6ff321a36813 100644 --- a/drivers/video/fbdev/nvidia/nv_type.h +++ b/drivers/video/fbdev/nvidia/nv_type.h | |||
@@ -148,12 +148,7 @@ struct nvidia_par { | |||
148 | u32 forceCRTC; | 148 | u32 forceCRTC; |
149 | u32 open_count; | 149 | u32 open_count; |
150 | u8 DDCBase; | 150 | u8 DDCBase; |
151 | #ifdef CONFIG_MTRR | 151 | int wc_cookie; |
152 | struct { | ||
153 | int vram; | ||
154 | int vram_valid; | ||
155 | } mtrr; | ||
156 | #endif | ||
157 | struct nvidia_i2c_chan chan[3]; | 152 | struct nvidia_i2c_chan chan[3]; |
158 | 153 | ||
159 | volatile u32 __iomem *REGS; | 154 | volatile u32 __iomem *REGS; |
diff --git a/drivers/video/fbdev/nvidia/nvidia.c b/drivers/video/fbdev/nvidia/nvidia.c index 4273c6ee8cf6..ce7dab7299fe 100644 --- a/drivers/video/fbdev/nvidia/nvidia.c +++ b/drivers/video/fbdev/nvidia/nvidia.c | |||
@@ -21,9 +21,6 @@ | |||
21 | #include <linux/pci.h> | 21 | #include <linux/pci.h> |
22 | #include <linux/console.h> | 22 | #include <linux/console.h> |
23 | #include <linux/backlight.h> | 23 | #include <linux/backlight.h> |
24 | #ifdef CONFIG_MTRR | ||
25 | #include <asm/mtrr.h> | ||
26 | #endif | ||
27 | #ifdef CONFIG_BOOTX_TEXT | 24 | #ifdef CONFIG_BOOTX_TEXT |
28 | #include <asm/btext.h> | 25 | #include <asm/btext.h> |
29 | #endif | 26 | #endif |
@@ -76,9 +73,7 @@ static int paneltweak = 0; | |||
76 | static int vram = 0; | 73 | static int vram = 0; |
77 | static int bpp = 8; | 74 | static int bpp = 8; |
78 | static int reverse_i2c; | 75 | static int reverse_i2c; |
79 | #ifdef CONFIG_MTRR | ||
80 | static bool nomtrr = false; | 76 | static bool nomtrr = false; |
81 | #endif | ||
82 | #ifdef CONFIG_PMAC_BACKLIGHT | 77 | #ifdef CONFIG_PMAC_BACKLIGHT |
83 | static int backlight = 1; | 78 | static int backlight = 1; |
84 | #else | 79 | #else |
@@ -1361,7 +1356,8 @@ static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) | |||
1361 | par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; | 1356 | par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; |
1362 | par->CursorStart = par->FbUsableSize + (32 * 1024); | 1357 | par->CursorStart = par->FbUsableSize + (32 * 1024); |
1363 | 1358 | ||
1364 | info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize); | 1359 | info->screen_base = ioremap_wc(nvidiafb_fix.smem_start, |
1360 | par->FbMapSize); | ||
1365 | info->screen_size = par->FbUsableSize; | 1361 | info->screen_size = par->FbUsableSize; |
1366 | nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; | 1362 | nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; |
1367 | 1363 | ||
@@ -1372,20 +1368,9 @@ static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) | |||
1372 | 1368 | ||
1373 | par->FbStart = info->screen_base; | 1369 | par->FbStart = info->screen_base; |
1374 | 1370 | ||
1375 | #ifdef CONFIG_MTRR | 1371 | if (!nomtrr) |
1376 | if (!nomtrr) { | 1372 | par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start, |
1377 | par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start, | 1373 | par->RamAmountKBytes * 1024); |
1378 | par->RamAmountKBytes * 1024, | ||
1379 | MTRR_TYPE_WRCOMB, 1); | ||
1380 | if (par->mtrr.vram < 0) { | ||
1381 | printk(KERN_ERR PFX "unable to setup MTRR\n"); | ||
1382 | } else { | ||
1383 | par->mtrr.vram_valid = 1; | ||
1384 | /* let there be speed */ | ||
1385 | printk(KERN_INFO PFX "MTRR set to ON\n"); | ||
1386 | } | ||
1387 | } | ||
1388 | #endif /* CONFIG_MTRR */ | ||
1389 | 1374 | ||
1390 | info->fbops = &nvidia_fb_ops; | 1375 | info->fbops = &nvidia_fb_ops; |
1391 | info->fix = nvidiafb_fix; | 1376 | info->fix = nvidiafb_fix; |
@@ -1443,13 +1428,7 @@ static void nvidiafb_remove(struct pci_dev *pd) | |||
1443 | unregister_framebuffer(info); | 1428 | unregister_framebuffer(info); |
1444 | 1429 | ||
1445 | nvidia_bl_exit(par); | 1430 | nvidia_bl_exit(par); |
1446 | 1431 | arch_phys_wc_del(par->wc_cookie); | |
1447 | #ifdef CONFIG_MTRR | ||
1448 | if (par->mtrr.vram_valid) | ||
1449 | mtrr_del(par->mtrr.vram, info->fix.smem_start, | ||
1450 | info->fix.smem_len); | ||
1451 | #endif /* CONFIG_MTRR */ | ||
1452 | |||
1453 | iounmap(info->screen_base); | 1432 | iounmap(info->screen_base); |
1454 | fb_destroy_modedb(info->monspecs.modedb); | 1433 | fb_destroy_modedb(info->monspecs.modedb); |
1455 | nvidia_delete_i2c_busses(par); | 1434 | nvidia_delete_i2c_busses(par); |
@@ -1501,10 +1480,8 @@ static int nvidiafb_setup(char *options) | |||
1501 | vram = simple_strtoul(this_opt+5, NULL, 0); | 1480 | vram = simple_strtoul(this_opt+5, NULL, 0); |
1502 | } else if (!strncmp(this_opt, "backlight:", 10)) { | 1481 | } else if (!strncmp(this_opt, "backlight:", 10)) { |
1503 | backlight = simple_strtoul(this_opt+10, NULL, 0); | 1482 | backlight = simple_strtoul(this_opt+10, NULL, 0); |
1504 | #ifdef CONFIG_MTRR | ||
1505 | } else if (!strncmp(this_opt, "nomtrr", 6)) { | 1483 | } else if (!strncmp(this_opt, "nomtrr", 6)) { |
1506 | nomtrr = true; | 1484 | nomtrr = true; |
1507 | #endif | ||
1508 | } else if (!strncmp(this_opt, "fpdither:", 9)) { | 1485 | } else if (!strncmp(this_opt, "fpdither:", 9)) { |
1509 | fpdither = simple_strtol(this_opt+9, NULL, 0); | 1486 | fpdither = simple_strtol(this_opt+9, NULL, 0); |
1510 | } else if (!strncmp(this_opt, "bpp:", 4)) { | 1487 | } else if (!strncmp(this_opt, "bpp:", 4)) { |
@@ -1592,11 +1569,9 @@ MODULE_PARM_DESC(bpp, "pixel width in bits" | |||
1592 | "(default=8)"); | 1569 | "(default=8)"); |
1593 | module_param(reverse_i2c, int, 0); | 1570 | module_param(reverse_i2c, int, 0); |
1594 | MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus"); | 1571 | MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus"); |
1595 | #ifdef CONFIG_MTRR | ||
1596 | module_param(nomtrr, bool, false); | 1572 | module_param(nomtrr, bool, false); |
1597 | MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) " | 1573 | MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) " |
1598 | "(default=0)"); | 1574 | "(default=0)"); |
1599 | #endif | ||
1600 | 1575 | ||
1601 | MODULE_AUTHOR("Antonino Daplas"); | 1576 | MODULE_AUTHOR("Antonino Daplas"); |
1602 | MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset"); | 1577 | MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset"); |
diff --git a/drivers/video/fbdev/omap/Kconfig b/drivers/video/fbdev/omap/Kconfig index 18c4cb0d5690..29d250da8a3e 100644 --- a/drivers/video/fbdev/omap/Kconfig +++ b/drivers/video/fbdev/omap/Kconfig | |||
@@ -42,7 +42,7 @@ config FB_OMAP_LCD_MIPID | |||
42 | config FB_OMAP_LCD_H3 | 42 | config FB_OMAP_LCD_H3 |
43 | bool "TPS65010 LCD controller on OMAP-H3" | 43 | bool "TPS65010 LCD controller on OMAP-H3" |
44 | depends on MACH_OMAP_H3 | 44 | depends on MACH_OMAP_H3 |
45 | depends on TPS65010 | 45 | depends on TPS65010=y |
46 | default y | 46 | default y |
47 | help | 47 | help |
48 | Say Y here if you want to have support for the LCD on the | 48 | Say Y here if you want to have support for the LCD on the |
diff --git a/drivers/video/fbdev/omap2/displays-new/encoder-opa362.c b/drivers/video/fbdev/omap2/displays-new/encoder-opa362.c index 84a6b3367124..a14d993f719d 100644 --- a/drivers/video/fbdev/omap2/displays-new/encoder-opa362.c +++ b/drivers/video/fbdev/omap2/displays-new/encoder-opa362.c | |||
@@ -201,15 +201,9 @@ static int opa362_probe(struct platform_device *pdev) | |||
201 | 201 | ||
202 | platform_set_drvdata(pdev, ddata); | 202 | platform_set_drvdata(pdev, ddata); |
203 | 203 | ||
204 | gpio = devm_gpiod_get(&pdev->dev, "enable"); | 204 | gpio = devm_gpiod_get_optional(&pdev->dev, "enable", GPIOD_OUT_LOW); |
205 | if (IS_ERR(gpio)) { | 205 | if (IS_ERR(gpio)) |
206 | if (PTR_ERR(gpio) != -ENOENT) | 206 | return PTR_ERR(gpio); |
207 | return PTR_ERR(gpio); | ||
208 | |||
209 | gpio = NULL; | ||
210 | } else { | ||
211 | gpiod_direction_output(gpio, 0); | ||
212 | } | ||
213 | 207 | ||
214 | ddata->enable_gpio = gpio; | 208 | ddata->enable_gpio = gpio; |
215 | 209 | ||
diff --git a/drivers/video/fbdev/omap2/displays-new/panel-dpi.c b/drivers/video/fbdev/omap2/displays-new/panel-dpi.c index eb8fd8140ad0..f7be3489f744 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-dpi.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-dpi.c | |||
@@ -209,16 +209,9 @@ static int panel_dpi_probe_of(struct platform_device *pdev) | |||
209 | struct videomode vm; | 209 | struct videomode vm; |
210 | struct gpio_desc *gpio; | 210 | struct gpio_desc *gpio; |
211 | 211 | ||
212 | gpio = devm_gpiod_get(&pdev->dev, "enable"); | 212 | gpio = devm_gpiod_get_optional(&pdev->dev, "enable", GPIOD_OUT_LOW); |
213 | 213 | if (IS_ERR(gpio)) | |
214 | if (IS_ERR(gpio)) { | 214 | return PTR_ERR(gpio); |
215 | if (PTR_ERR(gpio) != -ENOENT) | ||
216 | return PTR_ERR(gpio); | ||
217 | else | ||
218 | gpio = NULL; | ||
219 | } else { | ||
220 | gpiod_direction_output(gpio, 0); | ||
221 | } | ||
222 | 215 | ||
223 | ddata->enable_gpio = gpio; | 216 | ddata->enable_gpio = gpio; |
224 | 217 | ||
diff --git a/drivers/video/fbdev/omap2/displays-new/panel-lgphilips-lb035q02.c b/drivers/video/fbdev/omap2/displays-new/panel-lgphilips-lb035q02.c index 9974a37a11af..6a1b6a89a928 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-lgphilips-lb035q02.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-lgphilips-lb035q02.c | |||
@@ -285,15 +285,14 @@ static int lb035q02_probe_of(struct spi_device *spi) | |||
285 | struct omap_dss_device *in; | 285 | struct omap_dss_device *in; |
286 | struct gpio_desc *gpio; | 286 | struct gpio_desc *gpio; |
287 | 287 | ||
288 | gpio = devm_gpiod_get(&spi->dev, "enable"); | 288 | gpio = devm_gpiod_get(&spi->dev, "enable", GPIOD_OUT_LOW); |
289 | if (IS_ERR(gpio)) { | 289 | if (IS_ERR(gpio)) { |
290 | dev_err(&spi->dev, "failed to parse enable gpio\n"); | 290 | dev_err(&spi->dev, "failed to parse enable gpio\n"); |
291 | return PTR_ERR(gpio); | 291 | return PTR_ERR(gpio); |
292 | } else { | ||
293 | gpiod_direction_output(gpio, 0); | ||
294 | ddata->enable_gpio = gpio; | ||
295 | } | 292 | } |
296 | 293 | ||
294 | ddata->enable_gpio = gpio; | ||
295 | |||
297 | ddata->backlight_gpio = -ENOENT; | 296 | ddata->backlight_gpio = -ENOENT; |
298 | 297 | ||
299 | in = omapdss_of_find_source_for_first_ep(node); | 298 | in = omapdss_of_find_source_for_first_ep(node); |
diff --git a/drivers/video/fbdev/omap2/displays-new/panel-sharp-ls037v7dw01.c b/drivers/video/fbdev/omap2/displays-new/panel-sharp-ls037v7dw01.c index eae263702964..abfd1f6e3327 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-sharp-ls037v7dw01.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-sharp-ls037v7dw01.c | |||
@@ -268,17 +268,12 @@ static int sharp_ls_get_gpio_of(struct device *dev, int index, int val, | |||
268 | const char *desc, struct gpio_desc **gpiod) | 268 | const char *desc, struct gpio_desc **gpiod) |
269 | { | 269 | { |
270 | struct gpio_desc *gd; | 270 | struct gpio_desc *gd; |
271 | int r; | ||
272 | 271 | ||
273 | *gpiod = NULL; | 272 | *gpiod = NULL; |
274 | 273 | ||
275 | gd = devm_gpiod_get_index(dev, desc, index); | 274 | gd = devm_gpiod_get_index(dev, desc, index, GPIOD_OUT_LOW); |
276 | if (IS_ERR(gd)) | 275 | if (IS_ERR(gd)) |
277 | return PTR_ERR(gd) == -ENOENT ? 0 : PTR_ERR(gd); | 276 | return PTR_ERR(gd); |
278 | |||
279 | r = gpiod_direction_output(gd, val); | ||
280 | if (r) | ||
281 | return r; | ||
282 | 277 | ||
283 | *gpiod = gd; | 278 | *gpiod = gd; |
284 | return 0; | 279 | return 0; |
diff --git a/drivers/video/fbdev/omap2/dss/core.c b/drivers/video/fbdev/omap2/dss/core.c index 16751755d433..54eeb507f9b3 100644 --- a/drivers/video/fbdev/omap2/dss/core.c +++ b/drivers/video/fbdev/omap2/dss/core.c | |||
@@ -50,8 +50,6 @@ static char *def_disp_name; | |||
50 | module_param_named(def_disp, def_disp_name, charp, 0); | 50 | module_param_named(def_disp, def_disp_name, charp, 0); |
51 | MODULE_PARM_DESC(def_disp, "default display name"); | 51 | MODULE_PARM_DESC(def_disp, "default display name"); |
52 | 52 | ||
53 | static bool dss_initialized; | ||
54 | |||
55 | const char *omapdss_get_default_display_name(void) | 53 | const char *omapdss_get_default_display_name(void) |
56 | { | 54 | { |
57 | return core.default_display_name; | 55 | return core.default_display_name; |
@@ -65,12 +63,6 @@ enum omapdss_version omapdss_get_version(void) | |||
65 | } | 63 | } |
66 | EXPORT_SYMBOL(omapdss_get_version); | 64 | EXPORT_SYMBOL(omapdss_get_version); |
67 | 65 | ||
68 | bool omapdss_is_initialized(void) | ||
69 | { | ||
70 | return dss_initialized; | ||
71 | } | ||
72 | EXPORT_SYMBOL(omapdss_is_initialized); | ||
73 | |||
74 | struct platform_device *dss_get_core_pdev(void) | 66 | struct platform_device *dss_get_core_pdev(void) |
75 | { | 67 | { |
76 | return core.pdev; | 68 | return core.pdev; |
@@ -253,6 +245,8 @@ static struct platform_driver omap_dss_driver = { | |||
253 | 245 | ||
254 | /* INIT */ | 246 | /* INIT */ |
255 | static int (*dss_output_drv_reg_funcs[])(void) __initdata = { | 247 | static int (*dss_output_drv_reg_funcs[])(void) __initdata = { |
248 | dss_init_platform_driver, | ||
249 | dispc_init_platform_driver, | ||
256 | #ifdef CONFIG_OMAP2_DSS_DSI | 250 | #ifdef CONFIG_OMAP2_DSS_DSI |
257 | dsi_init_platform_driver, | 251 | dsi_init_platform_driver, |
258 | #endif | 252 | #endif |
@@ -276,32 +270,32 @@ static int (*dss_output_drv_reg_funcs[])(void) __initdata = { | |||
276 | #endif | 270 | #endif |
277 | }; | 271 | }; |
278 | 272 | ||
279 | static void (*dss_output_drv_unreg_funcs[])(void) __exitdata = { | 273 | static void (*dss_output_drv_unreg_funcs[])(void) = { |
280 | #ifdef CONFIG_OMAP2_DSS_DSI | 274 | #ifdef CONFIG_OMAP5_DSS_HDMI |
281 | dsi_uninit_platform_driver, | 275 | hdmi5_uninit_platform_driver, |
282 | #endif | 276 | #endif |
283 | #ifdef CONFIG_OMAP2_DSS_DPI | 277 | #ifdef CONFIG_OMAP4_DSS_HDMI |
284 | dpi_uninit_platform_driver, | 278 | hdmi4_uninit_platform_driver, |
285 | #endif | 279 | #endif |
286 | #ifdef CONFIG_OMAP2_DSS_SDI | 280 | #ifdef CONFIG_OMAP2_DSS_VENC |
287 | sdi_uninit_platform_driver, | 281 | venc_uninit_platform_driver, |
288 | #endif | 282 | #endif |
289 | #ifdef CONFIG_OMAP2_DSS_RFBI | 283 | #ifdef CONFIG_OMAP2_DSS_RFBI |
290 | rfbi_uninit_platform_driver, | 284 | rfbi_uninit_platform_driver, |
291 | #endif | 285 | #endif |
292 | #ifdef CONFIG_OMAP2_DSS_VENC | 286 | #ifdef CONFIG_OMAP2_DSS_SDI |
293 | venc_uninit_platform_driver, | 287 | sdi_uninit_platform_driver, |
294 | #endif | 288 | #endif |
295 | #ifdef CONFIG_OMAP4_DSS_HDMI | 289 | #ifdef CONFIG_OMAP2_DSS_DPI |
296 | hdmi4_uninit_platform_driver, | 290 | dpi_uninit_platform_driver, |
297 | #endif | 291 | #endif |
298 | #ifdef CONFIG_OMAP5_DSS_HDMI | 292 | #ifdef CONFIG_OMAP2_DSS_DSI |
299 | hdmi5_uninit_platform_driver, | 293 | dsi_uninit_platform_driver, |
300 | #endif | 294 | #endif |
295 | dispc_uninit_platform_driver, | ||
296 | dss_uninit_platform_driver, | ||
301 | }; | 297 | }; |
302 | 298 | ||
303 | static bool dss_output_drv_loaded[ARRAY_SIZE(dss_output_drv_reg_funcs)]; | ||
304 | |||
305 | static int __init omap_dss_init(void) | 299 | static int __init omap_dss_init(void) |
306 | { | 300 | { |
307 | int r; | 301 | int r; |
@@ -311,35 +305,20 @@ static int __init omap_dss_init(void) | |||
311 | if (r) | 305 | if (r) |
312 | return r; | 306 | return r; |
313 | 307 | ||
314 | r = dss_init_platform_driver(); | ||
315 | if (r) { | ||
316 | DSSERR("Failed to initialize DSS platform driver\n"); | ||
317 | goto err_dss; | ||
318 | } | ||
319 | |||
320 | r = dispc_init_platform_driver(); | ||
321 | if (r) { | ||
322 | DSSERR("Failed to initialize dispc platform driver\n"); | ||
323 | goto err_dispc; | ||
324 | } | ||
325 | |||
326 | /* | ||
327 | * It's ok if the output-driver register fails. It happens, for example, | ||
328 | * when there is no output-device (e.g. SDI for OMAP4). | ||
329 | */ | ||
330 | for (i = 0; i < ARRAY_SIZE(dss_output_drv_reg_funcs); ++i) { | 308 | for (i = 0; i < ARRAY_SIZE(dss_output_drv_reg_funcs); ++i) { |
331 | r = dss_output_drv_reg_funcs[i](); | 309 | r = dss_output_drv_reg_funcs[i](); |
332 | if (r == 0) | 310 | if (r) |
333 | dss_output_drv_loaded[i] = true; | 311 | goto err_reg; |
334 | } | 312 | } |
335 | 313 | ||
336 | dss_initialized = true; | ||
337 | |||
338 | return 0; | 314 | return 0; |
339 | 315 | ||
340 | err_dispc: | 316 | err_reg: |
341 | dss_uninit_platform_driver(); | 317 | for (i = ARRAY_SIZE(dss_output_drv_reg_funcs) - i; |
342 | err_dss: | 318 | i < ARRAY_SIZE(dss_output_drv_reg_funcs); |
319 | ++i) | ||
320 | dss_output_drv_unreg_funcs[i](); | ||
321 | |||
343 | platform_driver_unregister(&omap_dss_driver); | 322 | platform_driver_unregister(&omap_dss_driver); |
344 | 323 | ||
345 | return r; | 324 | return r; |
@@ -349,13 +328,8 @@ static void __exit omap_dss_exit(void) | |||
349 | { | 328 | { |
350 | int i; | 329 | int i; |
351 | 330 | ||
352 | for (i = 0; i < ARRAY_SIZE(dss_output_drv_unreg_funcs); ++i) { | 331 | for (i = 0; i < ARRAY_SIZE(dss_output_drv_unreg_funcs); ++i) |
353 | if (dss_output_drv_loaded[i]) | 332 | dss_output_drv_unreg_funcs[i](); |
354 | dss_output_drv_unreg_funcs[i](); | ||
355 | } | ||
356 | |||
357 | dispc_uninit_platform_driver(); | ||
358 | dss_uninit_platform_driver(); | ||
359 | 333 | ||
360 | platform_driver_unregister(&omap_dss_driver); | 334 | platform_driver_unregister(&omap_dss_driver); |
361 | } | 335 | } |
diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c index f4fc77d9d3bf..be716c9ffb88 100644 --- a/drivers/video/fbdev/omap2/dss/dispc.c +++ b/drivers/video/fbdev/omap2/dss/dispc.c | |||
@@ -39,6 +39,7 @@ | |||
39 | #include <linux/mfd/syscon.h> | 39 | #include <linux/mfd/syscon.h> |
40 | #include <linux/regmap.h> | 40 | #include <linux/regmap.h> |
41 | #include <linux/of.h> | 41 | #include <linux/of.h> |
42 | #include <linux/component.h> | ||
42 | 43 | ||
43 | #include <video/omapdss.h> | 44 | #include <video/omapdss.h> |
44 | 45 | ||
@@ -95,6 +96,9 @@ struct dispc_features { | |||
95 | bool mstandby_workaround:1; | 96 | bool mstandby_workaround:1; |
96 | 97 | ||
97 | bool set_max_preload:1; | 98 | bool set_max_preload:1; |
99 | |||
100 | /* PIXEL_INC is not added to the last pixel of a line */ | ||
101 | bool last_pixel_inc_missing:1; | ||
98 | }; | 102 | }; |
99 | 103 | ||
100 | #define DISPC_MAX_NR_FIFOS 5 | 104 | #define DISPC_MAX_NR_FIFOS 5 |
@@ -1741,6 +1745,15 @@ static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, | |||
1741 | row_repeat = false; | 1745 | row_repeat = false; |
1742 | } | 1746 | } |
1743 | 1747 | ||
1748 | /* | ||
1749 | * OMAP4/5 Errata i631: | ||
1750 | * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra | ||
1751 | * rows beyond the framebuffer, which may cause OCP error. | ||
1752 | */ | ||
1753 | if (color_mode == OMAP_DSS_COLOR_NV12 && | ||
1754 | rotation_type != OMAP_DSS_ROT_TILER) | ||
1755 | vidrot = 1; | ||
1756 | |||
1744 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); | 1757 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); |
1745 | if (dss_has_feature(FEAT_ROWREPEATENABLE)) | 1758 | if (dss_has_feature(FEAT_ROWREPEATENABLE)) |
1746 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), | 1759 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), |
@@ -2154,7 +2167,7 @@ static unsigned long calc_core_clk_five_taps(unsigned long pclk, | |||
2154 | if (height > out_height) { | 2167 | if (height > out_height) { |
2155 | unsigned int ppl = mgr_timings->x_res; | 2168 | unsigned int ppl = mgr_timings->x_res; |
2156 | 2169 | ||
2157 | tmp = pclk * height * out_width; | 2170 | tmp = (u64)pclk * height * out_width; |
2158 | do_div(tmp, 2 * out_height * ppl); | 2171 | do_div(tmp, 2 * out_height * ppl); |
2159 | core_clk = tmp; | 2172 | core_clk = tmp; |
2160 | 2173 | ||
@@ -2162,14 +2175,14 @@ static unsigned long calc_core_clk_five_taps(unsigned long pclk, | |||
2162 | if (ppl == out_width) | 2175 | if (ppl == out_width) |
2163 | return 0; | 2176 | return 0; |
2164 | 2177 | ||
2165 | tmp = pclk * (height - 2 * out_height) * out_width; | 2178 | tmp = (u64)pclk * (height - 2 * out_height) * out_width; |
2166 | do_div(tmp, 2 * out_height * (ppl - out_width)); | 2179 | do_div(tmp, 2 * out_height * (ppl - out_width)); |
2167 | core_clk = max_t(u32, core_clk, tmp); | 2180 | core_clk = max_t(u32, core_clk, tmp); |
2168 | } | 2181 | } |
2169 | } | 2182 | } |
2170 | 2183 | ||
2171 | if (width > out_width) { | 2184 | if (width > out_width) { |
2172 | tmp = pclk * width; | 2185 | tmp = (u64)pclk * width; |
2173 | do_div(tmp, out_width); | 2186 | do_div(tmp, out_width); |
2174 | core_clk = max_t(u32, core_clk, tmp); | 2187 | core_clk = max_t(u32, core_clk, tmp); |
2175 | 2188 | ||
@@ -2267,6 +2280,11 @@ static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, | |||
2267 | } | 2280 | } |
2268 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); | 2281 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); |
2269 | 2282 | ||
2283 | if (error) { | ||
2284 | DSSERR("failed to find scaling settings\n"); | ||
2285 | return -EINVAL; | ||
2286 | } | ||
2287 | |||
2270 | if (in_width > maxsinglelinewidth) { | 2288 | if (in_width > maxsinglelinewidth) { |
2271 | DSSERR("Cannot scale max input width exceeded"); | 2289 | DSSERR("Cannot scale max input width exceeded"); |
2272 | return -EINVAL; | 2290 | return -EINVAL; |
@@ -2283,7 +2301,6 @@ static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, | |||
2283 | { | 2301 | { |
2284 | int error; | 2302 | int error; |
2285 | u16 in_width, in_height; | 2303 | u16 in_width, in_height; |
2286 | int min_factor = min(*decim_x, *decim_y); | ||
2287 | const int maxsinglelinewidth = | 2304 | const int maxsinglelinewidth = |
2288 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | 2305 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); |
2289 | 2306 | ||
@@ -2317,20 +2334,32 @@ again: | |||
2317 | error = (error || in_width > maxsinglelinewidth * 2 || | 2334 | error = (error || in_width > maxsinglelinewidth * 2 || |
2318 | (in_width > maxsinglelinewidth && *five_taps) || | 2335 | (in_width > maxsinglelinewidth && *five_taps) || |
2319 | !*core_clk || *core_clk > dispc_core_clk_rate()); | 2336 | !*core_clk || *core_clk > dispc_core_clk_rate()); |
2320 | if (error) { | 2337 | |
2321 | if (*decim_x == *decim_y) { | 2338 | if (!error) { |
2322 | *decim_x = min_factor; | 2339 | /* verify that we're inside the limits of scaler */ |
2323 | ++*decim_y; | 2340 | if (in_width / 4 > out_width) |
2341 | error = 1; | ||
2342 | |||
2343 | if (*five_taps) { | ||
2344 | if (in_height / 4 > out_height) | ||
2345 | error = 1; | ||
2324 | } else { | 2346 | } else { |
2325 | swap(*decim_x, *decim_y); | 2347 | if (in_height / 2 > out_height) |
2326 | if (*decim_x < *decim_y) | 2348 | error = 1; |
2327 | ++*decim_x; | ||
2328 | } | 2349 | } |
2329 | } | 2350 | } |
2351 | |||
2352 | if (error) | ||
2353 | ++*decim_y; | ||
2330 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); | 2354 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); |
2331 | 2355 | ||
2332 | if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width, | 2356 | if (error) { |
2333 | height, out_width, out_height, *five_taps)) { | 2357 | DSSERR("failed to find scaling settings\n"); |
2358 | return -EINVAL; | ||
2359 | } | ||
2360 | |||
2361 | if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width, | ||
2362 | in_height, out_width, out_height, *five_taps)) { | ||
2334 | DSSERR("horizontal timing too tight\n"); | 2363 | DSSERR("horizontal timing too tight\n"); |
2335 | return -EINVAL; | 2364 | return -EINVAL; |
2336 | } | 2365 | } |
@@ -2390,6 +2419,9 @@ static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, | |||
2390 | return 0; | 2419 | return 0; |
2391 | } | 2420 | } |
2392 | 2421 | ||
2422 | #define DIV_FRAC(dividend, divisor) \ | ||
2423 | ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) | ||
2424 | |||
2393 | static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, | 2425 | static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, |
2394 | enum omap_overlay_caps caps, | 2426 | enum omap_overlay_caps caps, |
2395 | const struct omap_video_timings *mgr_timings, | 2427 | const struct omap_video_timings *mgr_timings, |
@@ -2449,8 +2481,19 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, | |||
2449 | if (ret) | 2481 | if (ret) |
2450 | return ret; | 2482 | return ret; |
2451 | 2483 | ||
2452 | DSSDBG("required core clk rate = %lu Hz\n", core_clk); | 2484 | DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n", |
2453 | DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate()); | 2485 | width, height, |
2486 | out_width, out_height, | ||
2487 | out_width / width, DIV_FRAC(out_width, width), | ||
2488 | out_height / height, DIV_FRAC(out_height, height), | ||
2489 | |||
2490 | decim_x, decim_y, | ||
2491 | width / decim_x, height / decim_y, | ||
2492 | out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), | ||
2493 | out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), | ||
2494 | |||
2495 | *five_taps ? 5 : 3, | ||
2496 | core_clk, dispc_core_clk_rate()); | ||
2454 | 2497 | ||
2455 | if (!core_clk || core_clk > dispc_core_clk_rate()) { | 2498 | if (!core_clk || core_clk > dispc_core_clk_rate()) { |
2456 | DSSERR("failed to set up scaling, " | 2499 | DSSERR("failed to set up scaling, " |
@@ -2533,6 +2576,21 @@ static int dispc_ovl_setup_common(enum omap_plane plane, | |||
2533 | if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) | 2576 | if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) |
2534 | return -EINVAL; | 2577 | return -EINVAL; |
2535 | 2578 | ||
2579 | switch (color_mode) { | ||
2580 | case OMAP_DSS_COLOR_YUV2: | ||
2581 | case OMAP_DSS_COLOR_UYVY: | ||
2582 | case OMAP_DSS_COLOR_NV12: | ||
2583 | if (in_width & 1) { | ||
2584 | DSSERR("input width %d is not even for YUV format\n", | ||
2585 | in_width); | ||
2586 | return -EINVAL; | ||
2587 | } | ||
2588 | break; | ||
2589 | |||
2590 | default: | ||
2591 | break; | ||
2592 | } | ||
2593 | |||
2536 | out_width = out_width == 0 ? width : out_width; | 2594 | out_width = out_width == 0 ? width : out_width; |
2537 | out_height = out_height == 0 ? height : out_height; | 2595 | out_height = out_height == 0 ? height : out_height; |
2538 | 2596 | ||
@@ -2563,6 +2621,27 @@ static int dispc_ovl_setup_common(enum omap_plane plane, | |||
2563 | in_width = in_width / x_predecim; | 2621 | in_width = in_width / x_predecim; |
2564 | in_height = in_height / y_predecim; | 2622 | in_height = in_height / y_predecim; |
2565 | 2623 | ||
2624 | if (x_predecim > 1 || y_predecim > 1) | ||
2625 | DSSDBG("predecimation %d x %x, new input size %d x %d\n", | ||
2626 | x_predecim, y_predecim, in_width, in_height); | ||
2627 | |||
2628 | switch (color_mode) { | ||
2629 | case OMAP_DSS_COLOR_YUV2: | ||
2630 | case OMAP_DSS_COLOR_UYVY: | ||
2631 | case OMAP_DSS_COLOR_NV12: | ||
2632 | if (in_width & 1) { | ||
2633 | DSSDBG("predecimated input width is not even for YUV format\n"); | ||
2634 | DSSDBG("adjusting input width %d -> %d\n", | ||
2635 | in_width, in_width & ~1); | ||
2636 | |||
2637 | in_width &= ~1; | ||
2638 | } | ||
2639 | break; | ||
2640 | |||
2641 | default: | ||
2642 | break; | ||
2643 | } | ||
2644 | |||
2566 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | 2645 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
2567 | color_mode == OMAP_DSS_COLOR_UYVY || | 2646 | color_mode == OMAP_DSS_COLOR_UYVY || |
2568 | color_mode == OMAP_DSS_COLOR_NV12) | 2647 | color_mode == OMAP_DSS_COLOR_NV12) |
@@ -2632,6 +2711,9 @@ static int dispc_ovl_setup_common(enum omap_plane plane, | |||
2632 | dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); | 2711 | dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); |
2633 | } | 2712 | } |
2634 | 2713 | ||
2714 | if (dispc.feat->last_pixel_inc_missing) | ||
2715 | row_inc += pix_inc - 1; | ||
2716 | |||
2635 | dispc_ovl_set_row_inc(plane, row_inc); | 2717 | dispc_ovl_set_row_inc(plane, row_inc); |
2636 | dispc_ovl_set_pix_inc(plane, pix_inc); | 2718 | dispc_ovl_set_pix_inc(plane, pix_inc); |
2637 | 2719 | ||
@@ -3692,7 +3774,7 @@ static void _omap_dispc_initial_config(void) | |||
3692 | dispc_init_mflag(); | 3774 | dispc_init_mflag(); |
3693 | } | 3775 | } |
3694 | 3776 | ||
3695 | static const struct dispc_features omap24xx_dispc_feats __initconst = { | 3777 | static const struct dispc_features omap24xx_dispc_feats = { |
3696 | .sw_start = 5, | 3778 | .sw_start = 5, |
3697 | .fp_start = 15, | 3779 | .fp_start = 15, |
3698 | .bp_start = 27, | 3780 | .bp_start = 27, |
@@ -3709,9 +3791,10 @@ static const struct dispc_features omap24xx_dispc_feats __initconst = { | |||
3709 | .num_fifos = 3, | 3791 | .num_fifos = 3, |
3710 | .no_framedone_tv = true, | 3792 | .no_framedone_tv = true, |
3711 | .set_max_preload = false, | 3793 | .set_max_preload = false, |
3794 | .last_pixel_inc_missing = true, | ||
3712 | }; | 3795 | }; |
3713 | 3796 | ||
3714 | static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = { | 3797 | static const struct dispc_features omap34xx_rev1_0_dispc_feats = { |
3715 | .sw_start = 5, | 3798 | .sw_start = 5, |
3716 | .fp_start = 15, | 3799 | .fp_start = 15, |
3717 | .bp_start = 27, | 3800 | .bp_start = 27, |
@@ -3729,9 +3812,10 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = { | |||
3729 | .num_fifos = 3, | 3812 | .num_fifos = 3, |
3730 | .no_framedone_tv = true, | 3813 | .no_framedone_tv = true, |
3731 | .set_max_preload = false, | 3814 | .set_max_preload = false, |
3815 | .last_pixel_inc_missing = true, | ||
3732 | }; | 3816 | }; |
3733 | 3817 | ||
3734 | static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = { | 3818 | static const struct dispc_features omap34xx_rev3_0_dispc_feats = { |
3735 | .sw_start = 7, | 3819 | .sw_start = 7, |
3736 | .fp_start = 19, | 3820 | .fp_start = 19, |
3737 | .bp_start = 31, | 3821 | .bp_start = 31, |
@@ -3749,9 +3833,10 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = { | |||
3749 | .num_fifos = 3, | 3833 | .num_fifos = 3, |
3750 | .no_framedone_tv = true, | 3834 | .no_framedone_tv = true, |
3751 | .set_max_preload = false, | 3835 | .set_max_preload = false, |
3836 | .last_pixel_inc_missing = true, | ||
3752 | }; | 3837 | }; |
3753 | 3838 | ||
3754 | static const struct dispc_features omap44xx_dispc_feats __initconst = { | 3839 | static const struct dispc_features omap44xx_dispc_feats = { |
3755 | .sw_start = 7, | 3840 | .sw_start = 7, |
3756 | .fp_start = 19, | 3841 | .fp_start = 19, |
3757 | .bp_start = 31, | 3842 | .bp_start = 31, |
@@ -3771,7 +3856,7 @@ static const struct dispc_features omap44xx_dispc_feats __initconst = { | |||
3771 | .set_max_preload = true, | 3856 | .set_max_preload = true, |
3772 | }; | 3857 | }; |
3773 | 3858 | ||
3774 | static const struct dispc_features omap54xx_dispc_feats __initconst = { | 3859 | static const struct dispc_features omap54xx_dispc_feats = { |
3775 | .sw_start = 7, | 3860 | .sw_start = 7, |
3776 | .fp_start = 19, | 3861 | .fp_start = 19, |
3777 | .bp_start = 31, | 3862 | .bp_start = 31, |
@@ -3792,7 +3877,7 @@ static const struct dispc_features omap54xx_dispc_feats __initconst = { | |||
3792 | .set_max_preload = true, | 3877 | .set_max_preload = true, |
3793 | }; | 3878 | }; |
3794 | 3879 | ||
3795 | static int __init dispc_init_features(struct platform_device *pdev) | 3880 | static int dispc_init_features(struct platform_device *pdev) |
3796 | { | 3881 | { |
3797 | const struct dispc_features *src; | 3882 | const struct dispc_features *src; |
3798 | struct dispc_features *dst; | 3883 | struct dispc_features *dst; |
@@ -3882,8 +3967,9 @@ void dispc_free_irq(void *dev_id) | |||
3882 | EXPORT_SYMBOL(dispc_free_irq); | 3967 | EXPORT_SYMBOL(dispc_free_irq); |
3883 | 3968 | ||
3884 | /* DISPC HW IP initialisation */ | 3969 | /* DISPC HW IP initialisation */ |
3885 | static int __init omap_dispchw_probe(struct platform_device *pdev) | 3970 | static int dispc_bind(struct device *dev, struct device *master, void *data) |
3886 | { | 3971 | { |
3972 | struct platform_device *pdev = to_platform_device(dev); | ||
3887 | u32 rev; | 3973 | u32 rev; |
3888 | int r = 0; | 3974 | int r = 0; |
3889 | struct resource *dispc_mem; | 3975 | struct resource *dispc_mem; |
@@ -3955,12 +4041,27 @@ err_runtime_get: | |||
3955 | return r; | 4041 | return r; |
3956 | } | 4042 | } |
3957 | 4043 | ||
3958 | static int __exit omap_dispchw_remove(struct platform_device *pdev) | 4044 | static void dispc_unbind(struct device *dev, struct device *master, |
4045 | void *data) | ||
3959 | { | 4046 | { |
3960 | pm_runtime_disable(&pdev->dev); | 4047 | pm_runtime_disable(dev); |
3961 | 4048 | ||
3962 | dss_uninit_overlay_managers(); | 4049 | dss_uninit_overlay_managers(); |
4050 | } | ||
4051 | |||
4052 | static const struct component_ops dispc_component_ops = { | ||
4053 | .bind = dispc_bind, | ||
4054 | .unbind = dispc_unbind, | ||
4055 | }; | ||
3963 | 4056 | ||
4057 | static int dispc_probe(struct platform_device *pdev) | ||
4058 | { | ||
4059 | return component_add(&pdev->dev, &dispc_component_ops); | ||
4060 | } | ||
4061 | |||
4062 | static int dispc_remove(struct platform_device *pdev) | ||
4063 | { | ||
4064 | component_del(&pdev->dev, &dispc_component_ops); | ||
3964 | return 0; | 4065 | return 0; |
3965 | } | 4066 | } |
3966 | 4067 | ||
@@ -4013,7 +4114,8 @@ static const struct of_device_id dispc_of_match[] = { | |||
4013 | }; | 4114 | }; |
4014 | 4115 | ||
4015 | static struct platform_driver omap_dispchw_driver = { | 4116 | static struct platform_driver omap_dispchw_driver = { |
4016 | .remove = __exit_p(omap_dispchw_remove), | 4117 | .probe = dispc_probe, |
4118 | .remove = dispc_remove, | ||
4017 | .driver = { | 4119 | .driver = { |
4018 | .name = "omapdss_dispc", | 4120 | .name = "omapdss_dispc", |
4019 | .pm = &dispc_pm_ops, | 4121 | .pm = &dispc_pm_ops, |
@@ -4024,10 +4126,10 @@ static struct platform_driver omap_dispchw_driver = { | |||
4024 | 4126 | ||
4025 | int __init dispc_init_platform_driver(void) | 4127 | int __init dispc_init_platform_driver(void) |
4026 | { | 4128 | { |
4027 | return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe); | 4129 | return platform_driver_register(&omap_dispchw_driver); |
4028 | } | 4130 | } |
4029 | 4131 | ||
4030 | void __exit dispc_uninit_platform_driver(void) | 4132 | void dispc_uninit_platform_driver(void) |
4031 | { | 4133 | { |
4032 | platform_driver_unregister(&omap_dispchw_driver); | 4134 | platform_driver_unregister(&omap_dispchw_driver); |
4033 | } | 4135 | } |
diff --git a/drivers/video/fbdev/omap2/dss/display-sysfs.c b/drivers/video/fbdev/omap2/dss/display-sysfs.c index 12186557a9d4..6ad0991f8259 100644 --- a/drivers/video/fbdev/omap2/dss/display-sysfs.c +++ b/drivers/video/fbdev/omap2/dss/display-sysfs.c | |||
@@ -324,7 +324,7 @@ int display_init_sysfs(struct platform_device *pdev) | |||
324 | 324 | ||
325 | for_each_dss_dev(dssdev) { | 325 | for_each_dss_dev(dssdev) { |
326 | r = kobject_init_and_add(&dssdev->kobj, &display_ktype, | 326 | r = kobject_init_and_add(&dssdev->kobj, &display_ktype, |
327 | &pdev->dev.kobj, dssdev->alias); | 327 | &pdev->dev.kobj, "%s", dssdev->alias); |
328 | if (r) { | 328 | if (r) { |
329 | DSSERR("failed to create sysfs files\n"); | 329 | DSSERR("failed to create sysfs files\n"); |
330 | omap_dss_put_device(dssdev); | 330 | omap_dss_put_device(dssdev); |
diff --git a/drivers/video/fbdev/omap2/dss/dpi.c b/drivers/video/fbdev/omap2/dss/dpi.c index f83e7b030249..fb45b6432968 100644 --- a/drivers/video/fbdev/omap2/dss/dpi.c +++ b/drivers/video/fbdev/omap2/dss/dpi.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include <linux/string.h> | 32 | #include <linux/string.h> |
33 | #include <linux/of.h> | 33 | #include <linux/of.h> |
34 | #include <linux/clk.h> | 34 | #include <linux/clk.h> |
35 | #include <linux/component.h> | ||
35 | 36 | ||
36 | #include <video/omapdss.h> | 37 | #include <video/omapdss.h> |
37 | 38 | ||
@@ -731,7 +732,7 @@ static void dpi_init_output(struct platform_device *pdev) | |||
731 | omapdss_register_output(out); | 732 | omapdss_register_output(out); |
732 | } | 733 | } |
733 | 734 | ||
734 | static void __exit dpi_uninit_output(struct platform_device *pdev) | 735 | static void dpi_uninit_output(struct platform_device *pdev) |
735 | { | 736 | { |
736 | struct dpi_data *dpi = dpi_get_data_from_pdev(pdev); | 737 | struct dpi_data *dpi = dpi_get_data_from_pdev(pdev); |
737 | struct omap_dss_device *out = &dpi->output; | 738 | struct omap_dss_device *out = &dpi->output; |
@@ -775,7 +776,7 @@ static void dpi_init_output_port(struct platform_device *pdev, | |||
775 | omapdss_register_output(out); | 776 | omapdss_register_output(out); |
776 | } | 777 | } |
777 | 778 | ||
778 | static void __exit dpi_uninit_output_port(struct device_node *port) | 779 | static void dpi_uninit_output_port(struct device_node *port) |
779 | { | 780 | { |
780 | struct dpi_data *dpi = port->data; | 781 | struct dpi_data *dpi = port->data; |
781 | struct omap_dss_device *out = &dpi->output; | 782 | struct omap_dss_device *out = &dpi->output; |
@@ -783,8 +784,9 @@ static void __exit dpi_uninit_output_port(struct device_node *port) | |||
783 | omapdss_unregister_output(out); | 784 | omapdss_unregister_output(out); |
784 | } | 785 | } |
785 | 786 | ||
786 | static int omap_dpi_probe(struct platform_device *pdev) | 787 | static int dpi_bind(struct device *dev, struct device *master, void *data) |
787 | { | 788 | { |
789 | struct platform_device *pdev = to_platform_device(dev); | ||
788 | struct dpi_data *dpi; | 790 | struct dpi_data *dpi; |
789 | 791 | ||
790 | dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL); | 792 | dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL); |
@@ -802,16 +804,32 @@ static int omap_dpi_probe(struct platform_device *pdev) | |||
802 | return 0; | 804 | return 0; |
803 | } | 805 | } |
804 | 806 | ||
805 | static int __exit omap_dpi_remove(struct platform_device *pdev) | 807 | static void dpi_unbind(struct device *dev, struct device *master, void *data) |
806 | { | 808 | { |
809 | struct platform_device *pdev = to_platform_device(dev); | ||
810 | |||
807 | dpi_uninit_output(pdev); | 811 | dpi_uninit_output(pdev); |
812 | } | ||
813 | |||
814 | static const struct component_ops dpi_component_ops = { | ||
815 | .bind = dpi_bind, | ||
816 | .unbind = dpi_unbind, | ||
817 | }; | ||
808 | 818 | ||
819 | static int dpi_probe(struct platform_device *pdev) | ||
820 | { | ||
821 | return component_add(&pdev->dev, &dpi_component_ops); | ||
822 | } | ||
823 | |||
824 | static int dpi_remove(struct platform_device *pdev) | ||
825 | { | ||
826 | component_del(&pdev->dev, &dpi_component_ops); | ||
809 | return 0; | 827 | return 0; |
810 | } | 828 | } |
811 | 829 | ||
812 | static struct platform_driver omap_dpi_driver = { | 830 | static struct platform_driver omap_dpi_driver = { |
813 | .probe = omap_dpi_probe, | 831 | .probe = dpi_probe, |
814 | .remove = __exit_p(omap_dpi_remove), | 832 | .remove = dpi_remove, |
815 | .driver = { | 833 | .driver = { |
816 | .name = "omapdss_dpi", | 834 | .name = "omapdss_dpi", |
817 | .suppress_bind_attrs = true, | 835 | .suppress_bind_attrs = true, |
@@ -823,12 +841,12 @@ int __init dpi_init_platform_driver(void) | |||
823 | return platform_driver_register(&omap_dpi_driver); | 841 | return platform_driver_register(&omap_dpi_driver); |
824 | } | 842 | } |
825 | 843 | ||
826 | void __exit dpi_uninit_platform_driver(void) | 844 | void dpi_uninit_platform_driver(void) |
827 | { | 845 | { |
828 | platform_driver_unregister(&omap_dpi_driver); | 846 | platform_driver_unregister(&omap_dpi_driver); |
829 | } | 847 | } |
830 | 848 | ||
831 | int __init dpi_init_port(struct platform_device *pdev, struct device_node *port) | 849 | int dpi_init_port(struct platform_device *pdev, struct device_node *port) |
832 | { | 850 | { |
833 | struct dpi_data *dpi; | 851 | struct dpi_data *dpi; |
834 | struct device_node *ep; | 852 | struct device_node *ep; |
@@ -870,7 +888,7 @@ err_datalines: | |||
870 | return r; | 888 | return r; |
871 | } | 889 | } |
872 | 890 | ||
873 | void __exit dpi_uninit_port(struct device_node *port) | 891 | void dpi_uninit_port(struct device_node *port) |
874 | { | 892 | { |
875 | struct dpi_data *dpi = port->data; | 893 | struct dpi_data *dpi = port->data; |
876 | 894 | ||
diff --git a/drivers/video/fbdev/omap2/dss/dsi.c b/drivers/video/fbdev/omap2/dss/dsi.c index 28b0bc11669d..b3606def5b7b 100644 --- a/drivers/video/fbdev/omap2/dss/dsi.c +++ b/drivers/video/fbdev/omap2/dss/dsi.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include <linux/pm_runtime.h> | 40 | #include <linux/pm_runtime.h> |
41 | #include <linux/of.h> | 41 | #include <linux/of.h> |
42 | #include <linux/of_platform.h> | 42 | #include <linux/of_platform.h> |
43 | #include <linux/component.h> | ||
43 | 44 | ||
44 | #include <video/omapdss.h> | 45 | #include <video/omapdss.h> |
45 | #include <video/mipi_display.h> | 46 | #include <video/mipi_display.h> |
@@ -5274,8 +5275,9 @@ static int dsi_init_pll_data(struct platform_device *dsidev) | |||
5274 | } | 5275 | } |
5275 | 5276 | ||
5276 | /* DSI1 HW IP initialisation */ | 5277 | /* DSI1 HW IP initialisation */ |
5277 | static int omap_dsihw_probe(struct platform_device *dsidev) | 5278 | static int dsi_bind(struct device *dev, struct device *master, void *data) |
5278 | { | 5279 | { |
5280 | struct platform_device *dsidev = to_platform_device(dev); | ||
5279 | u32 rev; | 5281 | u32 rev; |
5280 | int r, i; | 5282 | int r, i; |
5281 | struct dsi_data *dsi; | 5283 | struct dsi_data *dsi; |
@@ -5484,8 +5486,9 @@ err_runtime_get: | |||
5484 | return r; | 5486 | return r; |
5485 | } | 5487 | } |
5486 | 5488 | ||
5487 | static int __exit omap_dsihw_remove(struct platform_device *dsidev) | 5489 | static void dsi_unbind(struct device *dev, struct device *master, void *data) |
5488 | { | 5490 | { |
5491 | struct platform_device *dsidev = to_platform_device(dev); | ||
5489 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | 5492 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
5490 | 5493 | ||
5491 | of_platform_depopulate(&dsidev->dev); | 5494 | of_platform_depopulate(&dsidev->dev); |
@@ -5502,7 +5505,21 @@ static int __exit omap_dsihw_remove(struct platform_device *dsidev) | |||
5502 | regulator_disable(dsi->vdds_dsi_reg); | 5505 | regulator_disable(dsi->vdds_dsi_reg); |
5503 | dsi->vdds_dsi_enabled = false; | 5506 | dsi->vdds_dsi_enabled = false; |
5504 | } | 5507 | } |
5508 | } | ||
5509 | |||
5510 | static const struct component_ops dsi_component_ops = { | ||
5511 | .bind = dsi_bind, | ||
5512 | .unbind = dsi_unbind, | ||
5513 | }; | ||
5505 | 5514 | ||
5515 | static int dsi_probe(struct platform_device *pdev) | ||
5516 | { | ||
5517 | return component_add(&pdev->dev, &dsi_component_ops); | ||
5518 | } | ||
5519 | |||
5520 | static int dsi_remove(struct platform_device *pdev) | ||
5521 | { | ||
5522 | component_del(&pdev->dev, &dsi_component_ops); | ||
5506 | return 0; | 5523 | return 0; |
5507 | } | 5524 | } |
5508 | 5525 | ||
@@ -5569,8 +5586,8 @@ static const struct of_device_id dsi_of_match[] = { | |||
5569 | }; | 5586 | }; |
5570 | 5587 | ||
5571 | static struct platform_driver omap_dsihw_driver = { | 5588 | static struct platform_driver omap_dsihw_driver = { |
5572 | .probe = omap_dsihw_probe, | 5589 | .probe = dsi_probe, |
5573 | .remove = __exit_p(omap_dsihw_remove), | 5590 | .remove = dsi_remove, |
5574 | .driver = { | 5591 | .driver = { |
5575 | .name = "omapdss_dsi", | 5592 | .name = "omapdss_dsi", |
5576 | .pm = &dsi_pm_ops, | 5593 | .pm = &dsi_pm_ops, |
@@ -5584,7 +5601,7 @@ int __init dsi_init_platform_driver(void) | |||
5584 | return platform_driver_register(&omap_dsihw_driver); | 5601 | return platform_driver_register(&omap_dsihw_driver); |
5585 | } | 5602 | } |
5586 | 5603 | ||
5587 | void __exit dsi_uninit_platform_driver(void) | 5604 | void dsi_uninit_platform_driver(void) |
5588 | { | 5605 | { |
5589 | platform_driver_unregister(&omap_dsihw_driver); | 5606 | platform_driver_unregister(&omap_dsihw_driver); |
5590 | } | 5607 | } |
diff --git a/drivers/video/fbdev/omap2/dss/dss.c b/drivers/video/fbdev/omap2/dss/dss.c index 7f978b6a34e8..612b093831d5 100644 --- a/drivers/video/fbdev/omap2/dss/dss.c +++ b/drivers/video/fbdev/omap2/dss/dss.c | |||
@@ -39,6 +39,7 @@ | |||
39 | #include <linux/of.h> | 39 | #include <linux/of.h> |
40 | #include <linux/regulator/consumer.h> | 40 | #include <linux/regulator/consumer.h> |
41 | #include <linux/suspend.h> | 41 | #include <linux/suspend.h> |
42 | #include <linux/component.h> | ||
42 | 43 | ||
43 | #include <video/omapdss.h> | 44 | #include <video/omapdss.h> |
44 | 45 | ||
@@ -111,6 +112,14 @@ static const char * const dss_generic_clk_source_names[] = { | |||
111 | [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DSI_PLL2_HSDIV_DSI", | 112 | [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DSI_PLL2_HSDIV_DSI", |
112 | }; | 113 | }; |
113 | 114 | ||
115 | static bool dss_initialized; | ||
116 | |||
117 | bool omapdss_is_initialized(void) | ||
118 | { | ||
119 | return dss_initialized; | ||
120 | } | ||
121 | EXPORT_SYMBOL(omapdss_is_initialized); | ||
122 | |||
114 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) | 123 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) |
115 | { | 124 | { |
116 | __raw_writel(val, dss.base + idx.idx); | 125 | __raw_writel(val, dss.base + idx.idx); |
@@ -811,7 +820,7 @@ static const enum omap_display_type dra7xx_ports[] = { | |||
811 | OMAP_DISPLAY_TYPE_DPI, | 820 | OMAP_DISPLAY_TYPE_DPI, |
812 | }; | 821 | }; |
813 | 822 | ||
814 | static const struct dss_features omap24xx_dss_feats __initconst = { | 823 | static const struct dss_features omap24xx_dss_feats = { |
815 | /* | 824 | /* |
816 | * fck div max is really 16, but the divider range has gaps. The range | 825 | * fck div max is really 16, but the divider range has gaps. The range |
817 | * from 1 to 6 has no gaps, so let's use that as a max. | 826 | * from 1 to 6 has no gaps, so let's use that as a max. |
@@ -824,7 +833,7 @@ static const struct dss_features omap24xx_dss_feats __initconst = { | |||
824 | .num_ports = ARRAY_SIZE(omap2plus_ports), | 833 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
825 | }; | 834 | }; |
826 | 835 | ||
827 | static const struct dss_features omap34xx_dss_feats __initconst = { | 836 | static const struct dss_features omap34xx_dss_feats = { |
828 | .fck_div_max = 16, | 837 | .fck_div_max = 16, |
829 | .dss_fck_multiplier = 2, | 838 | .dss_fck_multiplier = 2, |
830 | .parent_clk_name = "dpll4_ck", | 839 | .parent_clk_name = "dpll4_ck", |
@@ -833,7 +842,7 @@ static const struct dss_features omap34xx_dss_feats __initconst = { | |||
833 | .num_ports = ARRAY_SIZE(omap34xx_ports), | 842 | .num_ports = ARRAY_SIZE(omap34xx_ports), |
834 | }; | 843 | }; |
835 | 844 | ||
836 | static const struct dss_features omap3630_dss_feats __initconst = { | 845 | static const struct dss_features omap3630_dss_feats = { |
837 | .fck_div_max = 32, | 846 | .fck_div_max = 32, |
838 | .dss_fck_multiplier = 1, | 847 | .dss_fck_multiplier = 1, |
839 | .parent_clk_name = "dpll4_ck", | 848 | .parent_clk_name = "dpll4_ck", |
@@ -842,7 +851,7 @@ static const struct dss_features omap3630_dss_feats __initconst = { | |||
842 | .num_ports = ARRAY_SIZE(omap2plus_ports), | 851 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
843 | }; | 852 | }; |
844 | 853 | ||
845 | static const struct dss_features omap44xx_dss_feats __initconst = { | 854 | static const struct dss_features omap44xx_dss_feats = { |
846 | .fck_div_max = 32, | 855 | .fck_div_max = 32, |
847 | .dss_fck_multiplier = 1, | 856 | .dss_fck_multiplier = 1, |
848 | .parent_clk_name = "dpll_per_x2_ck", | 857 | .parent_clk_name = "dpll_per_x2_ck", |
@@ -851,7 +860,7 @@ static const struct dss_features omap44xx_dss_feats __initconst = { | |||
851 | .num_ports = ARRAY_SIZE(omap2plus_ports), | 860 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
852 | }; | 861 | }; |
853 | 862 | ||
854 | static const struct dss_features omap54xx_dss_feats __initconst = { | 863 | static const struct dss_features omap54xx_dss_feats = { |
855 | .fck_div_max = 64, | 864 | .fck_div_max = 64, |
856 | .dss_fck_multiplier = 1, | 865 | .dss_fck_multiplier = 1, |
857 | .parent_clk_name = "dpll_per_x2_ck", | 866 | .parent_clk_name = "dpll_per_x2_ck", |
@@ -860,7 +869,7 @@ static const struct dss_features omap54xx_dss_feats __initconst = { | |||
860 | .num_ports = ARRAY_SIZE(omap2plus_ports), | 869 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
861 | }; | 870 | }; |
862 | 871 | ||
863 | static const struct dss_features am43xx_dss_feats __initconst = { | 872 | static const struct dss_features am43xx_dss_feats = { |
864 | .fck_div_max = 0, | 873 | .fck_div_max = 0, |
865 | .dss_fck_multiplier = 0, | 874 | .dss_fck_multiplier = 0, |
866 | .parent_clk_name = NULL, | 875 | .parent_clk_name = NULL, |
@@ -869,7 +878,7 @@ static const struct dss_features am43xx_dss_feats __initconst = { | |||
869 | .num_ports = ARRAY_SIZE(omap2plus_ports), | 878 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
870 | }; | 879 | }; |
871 | 880 | ||
872 | static const struct dss_features dra7xx_dss_feats __initconst = { | 881 | static const struct dss_features dra7xx_dss_feats = { |
873 | .fck_div_max = 64, | 882 | .fck_div_max = 64, |
874 | .dss_fck_multiplier = 1, | 883 | .dss_fck_multiplier = 1, |
875 | .parent_clk_name = "dpll_per_x2_ck", | 884 | .parent_clk_name = "dpll_per_x2_ck", |
@@ -878,7 +887,7 @@ static const struct dss_features dra7xx_dss_feats __initconst = { | |||
878 | .num_ports = ARRAY_SIZE(dra7xx_ports), | 887 | .num_ports = ARRAY_SIZE(dra7xx_ports), |
879 | }; | 888 | }; |
880 | 889 | ||
881 | static int __init dss_init_features(struct platform_device *pdev) | 890 | static int dss_init_features(struct platform_device *pdev) |
882 | { | 891 | { |
883 | const struct dss_features *src; | 892 | const struct dss_features *src; |
884 | struct dss_features *dst; | 893 | struct dss_features *dst; |
@@ -932,7 +941,7 @@ static int __init dss_init_features(struct platform_device *pdev) | |||
932 | return 0; | 941 | return 0; |
933 | } | 942 | } |
934 | 943 | ||
935 | static int __init dss_init_ports(struct platform_device *pdev) | 944 | static int dss_init_ports(struct platform_device *pdev) |
936 | { | 945 | { |
937 | struct device_node *parent = pdev->dev.of_node; | 946 | struct device_node *parent = pdev->dev.of_node; |
938 | struct device_node *port; | 947 | struct device_node *port; |
@@ -976,7 +985,7 @@ static int __init dss_init_ports(struct platform_device *pdev) | |||
976 | return 0; | 985 | return 0; |
977 | } | 986 | } |
978 | 987 | ||
979 | static void __exit dss_uninit_ports(struct platform_device *pdev) | 988 | static void dss_uninit_ports(struct platform_device *pdev) |
980 | { | 989 | { |
981 | struct device_node *parent = pdev->dev.of_node; | 990 | struct device_node *parent = pdev->dev.of_node; |
982 | struct device_node *port; | 991 | struct device_node *port; |
@@ -1018,14 +1027,74 @@ static void __exit dss_uninit_ports(struct platform_device *pdev) | |||
1018 | } while ((port = omapdss_of_get_next_port(parent, port)) != NULL); | 1027 | } while ((port = omapdss_of_get_next_port(parent, port)) != NULL); |
1019 | } | 1028 | } |
1020 | 1029 | ||
1030 | static int dss_video_pll_probe(struct platform_device *pdev) | ||
1031 | { | ||
1032 | struct device_node *np = pdev->dev.of_node; | ||
1033 | struct regulator *pll_regulator; | ||
1034 | int r; | ||
1035 | |||
1036 | if (!np) | ||
1037 | return 0; | ||
1038 | |||
1039 | if (of_property_read_bool(np, "syscon-pll-ctrl")) { | ||
1040 | dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, | ||
1041 | "syscon-pll-ctrl"); | ||
1042 | if (IS_ERR(dss.syscon_pll_ctrl)) { | ||
1043 | dev_err(&pdev->dev, | ||
1044 | "failed to get syscon-pll-ctrl regmap\n"); | ||
1045 | return PTR_ERR(dss.syscon_pll_ctrl); | ||
1046 | } | ||
1047 | |||
1048 | if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, | ||
1049 | &dss.syscon_pll_ctrl_offset)) { | ||
1050 | dev_err(&pdev->dev, | ||
1051 | "failed to get syscon-pll-ctrl offset\n"); | ||
1052 | return -EINVAL; | ||
1053 | } | ||
1054 | } | ||
1055 | |||
1056 | pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video"); | ||
1057 | if (IS_ERR(pll_regulator)) { | ||
1058 | r = PTR_ERR(pll_regulator); | ||
1059 | |||
1060 | switch (r) { | ||
1061 | case -ENOENT: | ||
1062 | pll_regulator = NULL; | ||
1063 | break; | ||
1064 | |||
1065 | case -EPROBE_DEFER: | ||
1066 | return -EPROBE_DEFER; | ||
1067 | |||
1068 | default: | ||
1069 | DSSERR("can't get DPLL VDDA regulator\n"); | ||
1070 | return r; | ||
1071 | } | ||
1072 | } | ||
1073 | |||
1074 | if (of_property_match_string(np, "reg-names", "pll1") >= 0) { | ||
1075 | dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator); | ||
1076 | if (IS_ERR(dss.video1_pll)) | ||
1077 | return PTR_ERR(dss.video1_pll); | ||
1078 | } | ||
1079 | |||
1080 | if (of_property_match_string(np, "reg-names", "pll2") >= 0) { | ||
1081 | dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator); | ||
1082 | if (IS_ERR(dss.video2_pll)) { | ||
1083 | dss_video_pll_uninit(dss.video1_pll); | ||
1084 | return PTR_ERR(dss.video2_pll); | ||
1085 | } | ||
1086 | } | ||
1087 | |||
1088 | return 0; | ||
1089 | } | ||
1090 | |||
1021 | /* DSS HW IP initialisation */ | 1091 | /* DSS HW IP initialisation */ |
1022 | static int __init omap_dsshw_probe(struct platform_device *pdev) | 1092 | static int dss_bind(struct device *dev) |
1023 | { | 1093 | { |
1094 | struct platform_device *pdev = to_platform_device(dev); | ||
1024 | struct resource *dss_mem; | 1095 | struct resource *dss_mem; |
1025 | struct device_node *np = pdev->dev.of_node; | ||
1026 | u32 rev; | 1096 | u32 rev; |
1027 | int r; | 1097 | int r; |
1028 | struct regulator *pll_regulator; | ||
1029 | 1098 | ||
1030 | dss.pdev = pdev; | 1099 | dss.pdev = pdev; |
1031 | 1100 | ||
@@ -1054,6 +1123,14 @@ static int __init omap_dsshw_probe(struct platform_device *pdev) | |||
1054 | if (r) | 1123 | if (r) |
1055 | goto err_setup_clocks; | 1124 | goto err_setup_clocks; |
1056 | 1125 | ||
1126 | r = dss_video_pll_probe(pdev); | ||
1127 | if (r) | ||
1128 | goto err_pll_init; | ||
1129 | |||
1130 | r = dss_init_ports(pdev); | ||
1131 | if (r) | ||
1132 | goto err_init_ports; | ||
1133 | |||
1057 | pm_runtime_enable(&pdev->dev); | 1134 | pm_runtime_enable(&pdev->dev); |
1058 | 1135 | ||
1059 | r = dss_runtime_get(); | 1136 | r = dss_runtime_get(); |
@@ -1078,86 +1155,48 @@ static int __init omap_dsshw_probe(struct platform_device *pdev) | |||
1078 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | 1155 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; |
1079 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | 1156 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; |
1080 | 1157 | ||
1081 | dss_init_ports(pdev); | ||
1082 | |||
1083 | if (np && of_property_read_bool(np, "syscon-pll-ctrl")) { | ||
1084 | dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, | ||
1085 | "syscon-pll-ctrl"); | ||
1086 | if (IS_ERR(dss.syscon_pll_ctrl)) { | ||
1087 | dev_err(&pdev->dev, | ||
1088 | "failed to get syscon-pll-ctrl regmap\n"); | ||
1089 | return PTR_ERR(dss.syscon_pll_ctrl); | ||
1090 | } | ||
1091 | |||
1092 | if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, | ||
1093 | &dss.syscon_pll_ctrl_offset)) { | ||
1094 | dev_err(&pdev->dev, | ||
1095 | "failed to get syscon-pll-ctrl offset\n"); | ||
1096 | return -EINVAL; | ||
1097 | } | ||
1098 | } | ||
1099 | |||
1100 | pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video"); | ||
1101 | if (IS_ERR(pll_regulator)) { | ||
1102 | r = PTR_ERR(pll_regulator); | ||
1103 | |||
1104 | switch (r) { | ||
1105 | case -ENOENT: | ||
1106 | pll_regulator = NULL; | ||
1107 | break; | ||
1108 | |||
1109 | case -EPROBE_DEFER: | ||
1110 | return -EPROBE_DEFER; | ||
1111 | |||
1112 | default: | ||
1113 | DSSERR("can't get DPLL VDDA regulator\n"); | ||
1114 | return r; | ||
1115 | } | ||
1116 | } | ||
1117 | |||
1118 | if (of_property_match_string(np, "reg-names", "pll1") >= 0) { | ||
1119 | dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator); | ||
1120 | if (IS_ERR(dss.video1_pll)) { | ||
1121 | r = PTR_ERR(dss.video1_pll); | ||
1122 | goto err_pll_init; | ||
1123 | } | ||
1124 | } | ||
1125 | |||
1126 | if (of_property_match_string(np, "reg-names", "pll2") >= 0) { | ||
1127 | dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator); | ||
1128 | if (IS_ERR(dss.video2_pll)) { | ||
1129 | r = PTR_ERR(dss.video2_pll); | ||
1130 | goto err_pll_init; | ||
1131 | } | ||
1132 | } | ||
1133 | |||
1134 | rev = dss_read_reg(DSS_REVISION); | 1158 | rev = dss_read_reg(DSS_REVISION); |
1135 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", | 1159 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", |
1136 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | 1160 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
1137 | 1161 | ||
1138 | dss_runtime_put(); | 1162 | dss_runtime_put(); |
1139 | 1163 | ||
1164 | r = component_bind_all(&pdev->dev, NULL); | ||
1165 | if (r) | ||
1166 | goto err_component; | ||
1167 | |||
1140 | dss_debugfs_create_file("dss", dss_dump_regs); | 1168 | dss_debugfs_create_file("dss", dss_dump_regs); |
1141 | 1169 | ||
1142 | pm_set_vt_switch(0); | 1170 | pm_set_vt_switch(0); |
1143 | 1171 | ||
1172 | dss_initialized = true; | ||
1173 | |||
1144 | return 0; | 1174 | return 0; |
1145 | 1175 | ||
1146 | err_pll_init: | 1176 | err_component: |
1177 | err_runtime_get: | ||
1178 | pm_runtime_disable(&pdev->dev); | ||
1179 | dss_uninit_ports(pdev); | ||
1180 | err_init_ports: | ||
1147 | if (dss.video1_pll) | 1181 | if (dss.video1_pll) |
1148 | dss_video_pll_uninit(dss.video1_pll); | 1182 | dss_video_pll_uninit(dss.video1_pll); |
1149 | 1183 | ||
1150 | if (dss.video2_pll) | 1184 | if (dss.video2_pll) |
1151 | dss_video_pll_uninit(dss.video2_pll); | 1185 | dss_video_pll_uninit(dss.video2_pll); |
1152 | err_runtime_get: | 1186 | err_pll_init: |
1153 | pm_runtime_disable(&pdev->dev); | ||
1154 | err_setup_clocks: | 1187 | err_setup_clocks: |
1155 | dss_put_clocks(); | 1188 | dss_put_clocks(); |
1156 | return r; | 1189 | return r; |
1157 | } | 1190 | } |
1158 | 1191 | ||
1159 | static int __exit omap_dsshw_remove(struct platform_device *pdev) | 1192 | static void dss_unbind(struct device *dev) |
1160 | { | 1193 | { |
1194 | struct platform_device *pdev = to_platform_device(dev); | ||
1195 | |||
1196 | dss_initialized = false; | ||
1197 | |||
1198 | component_unbind_all(&pdev->dev, NULL); | ||
1199 | |||
1161 | if (dss.video1_pll) | 1200 | if (dss.video1_pll) |
1162 | dss_video_pll_uninit(dss.video1_pll); | 1201 | dss_video_pll_uninit(dss.video1_pll); |
1163 | 1202 | ||
@@ -1169,10 +1208,49 @@ static int __exit omap_dsshw_remove(struct platform_device *pdev) | |||
1169 | pm_runtime_disable(&pdev->dev); | 1208 | pm_runtime_disable(&pdev->dev); |
1170 | 1209 | ||
1171 | dss_put_clocks(); | 1210 | dss_put_clocks(); |
1211 | } | ||
1212 | |||
1213 | static const struct component_master_ops dss_component_ops = { | ||
1214 | .bind = dss_bind, | ||
1215 | .unbind = dss_unbind, | ||
1216 | }; | ||
1217 | |||
1218 | static int dss_component_compare(struct device *dev, void *data) | ||
1219 | { | ||
1220 | struct device *child = data; | ||
1221 | return dev == child; | ||
1222 | } | ||
1223 | |||
1224 | static int dss_add_child_component(struct device *dev, void *data) | ||
1225 | { | ||
1226 | struct component_match **match = data; | ||
1227 | |||
1228 | component_match_add(dev->parent, match, dss_component_compare, dev); | ||
1229 | |||
1230 | return 0; | ||
1231 | } | ||
1232 | |||
1233 | static int dss_probe(struct platform_device *pdev) | ||
1234 | { | ||
1235 | struct component_match *match = NULL; | ||
1236 | int r; | ||
1237 | |||
1238 | /* add all the child devices as components */ | ||
1239 | device_for_each_child(&pdev->dev, &match, dss_add_child_component); | ||
1240 | |||
1241 | r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); | ||
1242 | if (r) | ||
1243 | return r; | ||
1172 | 1244 | ||
1173 | return 0; | 1245 | return 0; |
1174 | } | 1246 | } |
1175 | 1247 | ||
1248 | static int dss_remove(struct platform_device *pdev) | ||
1249 | { | ||
1250 | component_master_del(&pdev->dev, &dss_component_ops); | ||
1251 | return 0; | ||
1252 | } | ||
1253 | |||
1176 | static int dss_runtime_suspend(struct device *dev) | 1254 | static int dss_runtime_suspend(struct device *dev) |
1177 | { | 1255 | { |
1178 | dss_save_context(); | 1256 | dss_save_context(); |
@@ -1215,7 +1293,8 @@ static const struct of_device_id dss_of_match[] = { | |||
1215 | MODULE_DEVICE_TABLE(of, dss_of_match); | 1293 | MODULE_DEVICE_TABLE(of, dss_of_match); |
1216 | 1294 | ||
1217 | static struct platform_driver omap_dsshw_driver = { | 1295 | static struct platform_driver omap_dsshw_driver = { |
1218 | .remove = __exit_p(omap_dsshw_remove), | 1296 | .probe = dss_probe, |
1297 | .remove = dss_remove, | ||
1219 | .driver = { | 1298 | .driver = { |
1220 | .name = "omapdss_dss", | 1299 | .name = "omapdss_dss", |
1221 | .pm = &dss_pm_ops, | 1300 | .pm = &dss_pm_ops, |
@@ -1226,7 +1305,7 @@ static struct platform_driver omap_dsshw_driver = { | |||
1226 | 1305 | ||
1227 | int __init dss_init_platform_driver(void) | 1306 | int __init dss_init_platform_driver(void) |
1228 | { | 1307 | { |
1229 | return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe); | 1308 | return platform_driver_register(&omap_dsshw_driver); |
1230 | } | 1309 | } |
1231 | 1310 | ||
1232 | void dss_uninit_platform_driver(void) | 1311 | void dss_uninit_platform_driver(void) |
diff --git a/drivers/video/fbdev/omap2/dss/dss.h b/drivers/video/fbdev/omap2/dss/dss.h index 4812eee2622a..2406bcdb831a 100644 --- a/drivers/video/fbdev/omap2/dss/dss.h +++ b/drivers/video/fbdev/omap2/dss/dss.h | |||
@@ -309,18 +309,18 @@ bool dss_div_calc(unsigned long pck, unsigned long fck_min, | |||
309 | 309 | ||
310 | /* SDI */ | 310 | /* SDI */ |
311 | int sdi_init_platform_driver(void) __init; | 311 | int sdi_init_platform_driver(void) __init; |
312 | void sdi_uninit_platform_driver(void) __exit; | 312 | void sdi_uninit_platform_driver(void); |
313 | 313 | ||
314 | #ifdef CONFIG_OMAP2_DSS_SDI | 314 | #ifdef CONFIG_OMAP2_DSS_SDI |
315 | int sdi_init_port(struct platform_device *pdev, struct device_node *port) __init; | 315 | int sdi_init_port(struct platform_device *pdev, struct device_node *port); |
316 | void sdi_uninit_port(struct device_node *port) __exit; | 316 | void sdi_uninit_port(struct device_node *port); |
317 | #else | 317 | #else |
318 | static inline int __init sdi_init_port(struct platform_device *pdev, | 318 | static inline int sdi_init_port(struct platform_device *pdev, |
319 | struct device_node *port) | 319 | struct device_node *port) |
320 | { | 320 | { |
321 | return 0; | 321 | return 0; |
322 | } | 322 | } |
323 | static inline void __exit sdi_uninit_port(struct device_node *port) | 323 | static inline void sdi_uninit_port(struct device_node *port) |
324 | { | 324 | { |
325 | } | 325 | } |
326 | #endif | 326 | #endif |
@@ -333,7 +333,7 @@ struct dentry; | |||
333 | struct file_operations; | 333 | struct file_operations; |
334 | 334 | ||
335 | int dsi_init_platform_driver(void) __init; | 335 | int dsi_init_platform_driver(void) __init; |
336 | void dsi_uninit_platform_driver(void) __exit; | 336 | void dsi_uninit_platform_driver(void); |
337 | 337 | ||
338 | void dsi_dump_clocks(struct seq_file *s); | 338 | void dsi_dump_clocks(struct seq_file *s); |
339 | 339 | ||
@@ -350,25 +350,25 @@ static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) | |||
350 | 350 | ||
351 | /* DPI */ | 351 | /* DPI */ |
352 | int dpi_init_platform_driver(void) __init; | 352 | int dpi_init_platform_driver(void) __init; |
353 | void dpi_uninit_platform_driver(void) __exit; | 353 | void dpi_uninit_platform_driver(void); |
354 | 354 | ||
355 | #ifdef CONFIG_OMAP2_DSS_DPI | 355 | #ifdef CONFIG_OMAP2_DSS_DPI |
356 | int dpi_init_port(struct platform_device *pdev, struct device_node *port) __init; | 356 | int dpi_init_port(struct platform_device *pdev, struct device_node *port); |
357 | void dpi_uninit_port(struct device_node *port) __exit; | 357 | void dpi_uninit_port(struct device_node *port); |
358 | #else | 358 | #else |
359 | static inline int __init dpi_init_port(struct platform_device *pdev, | 359 | static inline int dpi_init_port(struct platform_device *pdev, |
360 | struct device_node *port) | 360 | struct device_node *port) |
361 | { | 361 | { |
362 | return 0; | 362 | return 0; |
363 | } | 363 | } |
364 | static inline void __exit dpi_uninit_port(struct device_node *port) | 364 | static inline void dpi_uninit_port(struct device_node *port) |
365 | { | 365 | { |
366 | } | 366 | } |
367 | #endif | 367 | #endif |
368 | 368 | ||
369 | /* DISPC */ | 369 | /* DISPC */ |
370 | int dispc_init_platform_driver(void) __init; | 370 | int dispc_init_platform_driver(void) __init; |
371 | void dispc_uninit_platform_driver(void) __exit; | 371 | void dispc_uninit_platform_driver(void); |
372 | void dispc_dump_clocks(struct seq_file *s); | 372 | void dispc_dump_clocks(struct seq_file *s); |
373 | 373 | ||
374 | void dispc_enable_sidle(void); | 374 | void dispc_enable_sidle(void); |
@@ -418,18 +418,18 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi, | |||
418 | 418 | ||
419 | /* VENC */ | 419 | /* VENC */ |
420 | int venc_init_platform_driver(void) __init; | 420 | int venc_init_platform_driver(void) __init; |
421 | void venc_uninit_platform_driver(void) __exit; | 421 | void venc_uninit_platform_driver(void); |
422 | 422 | ||
423 | /* HDMI */ | 423 | /* HDMI */ |
424 | int hdmi4_init_platform_driver(void) __init; | 424 | int hdmi4_init_platform_driver(void) __init; |
425 | void hdmi4_uninit_platform_driver(void) __exit; | 425 | void hdmi4_uninit_platform_driver(void); |
426 | 426 | ||
427 | int hdmi5_init_platform_driver(void) __init; | 427 | int hdmi5_init_platform_driver(void) __init; |
428 | void hdmi5_uninit_platform_driver(void) __exit; | 428 | void hdmi5_uninit_platform_driver(void); |
429 | 429 | ||
430 | /* RFBI */ | 430 | /* RFBI */ |
431 | int rfbi_init_platform_driver(void) __init; | 431 | int rfbi_init_platform_driver(void) __init; |
432 | void rfbi_uninit_platform_driver(void) __exit; | 432 | void rfbi_uninit_platform_driver(void); |
433 | 433 | ||
434 | 434 | ||
435 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | 435 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
diff --git a/drivers/video/fbdev/omap2/dss/hdmi4.c b/drivers/video/fbdev/omap2/dss/hdmi4.c index 916d47978f41..6d3aa3f51c20 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include <linux/clk.h> | 32 | #include <linux/clk.h> |
33 | #include <linux/gpio.h> | 33 | #include <linux/gpio.h> |
34 | #include <linux/regulator/consumer.h> | 34 | #include <linux/regulator/consumer.h> |
35 | #include <linux/component.h> | ||
35 | #include <video/omapdss.h> | 36 | #include <video/omapdss.h> |
36 | #include <sound/omap-hdmi-audio.h> | 37 | #include <sound/omap-hdmi-audio.h> |
37 | 38 | ||
@@ -229,9 +230,9 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) | |||
229 | err_mgr_enable: | 230 | err_mgr_enable: |
230 | hdmi_wp_video_stop(&hdmi.wp); | 231 | hdmi_wp_video_stop(&hdmi.wp); |
231 | err_vid_enable: | 232 | err_vid_enable: |
232 | err_phy_cfg: | ||
233 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); | 233 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); |
234 | err_phy_pwr: | 234 | err_phy_pwr: |
235 | err_phy_cfg: | ||
235 | err_pll_cfg: | 236 | err_pll_cfg: |
236 | dss_pll_disable(&hdmi.pll.pll); | 237 | dss_pll_disable(&hdmi.pll.pll); |
237 | err_pll_enable: | 238 | err_pll_enable: |
@@ -646,8 +647,9 @@ static int hdmi_audio_register(struct device *dev) | |||
646 | } | 647 | } |
647 | 648 | ||
648 | /* HDMI HW IP initialisation */ | 649 | /* HDMI HW IP initialisation */ |
649 | static int omapdss_hdmihw_probe(struct platform_device *pdev) | 650 | static int hdmi4_bind(struct device *dev, struct device *master, void *data) |
650 | { | 651 | { |
652 | struct platform_device *pdev = to_platform_device(dev); | ||
651 | int r; | 653 | int r; |
652 | int irq; | 654 | int irq; |
653 | 655 | ||
@@ -713,8 +715,10 @@ err: | |||
713 | return r; | 715 | return r; |
714 | } | 716 | } |
715 | 717 | ||
716 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) | 718 | static void hdmi4_unbind(struct device *dev, struct device *master, void *data) |
717 | { | 719 | { |
720 | struct platform_device *pdev = to_platform_device(dev); | ||
721 | |||
718 | if (hdmi.audio_pdev) | 722 | if (hdmi.audio_pdev) |
719 | platform_device_unregister(hdmi.audio_pdev); | 723 | platform_device_unregister(hdmi.audio_pdev); |
720 | 724 | ||
@@ -723,7 +727,21 @@ static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) | |||
723 | hdmi_pll_uninit(&hdmi.pll); | 727 | hdmi_pll_uninit(&hdmi.pll); |
724 | 728 | ||
725 | pm_runtime_disable(&pdev->dev); | 729 | pm_runtime_disable(&pdev->dev); |
730 | } | ||
731 | |||
732 | static const struct component_ops hdmi4_component_ops = { | ||
733 | .bind = hdmi4_bind, | ||
734 | .unbind = hdmi4_unbind, | ||
735 | }; | ||
726 | 736 | ||
737 | static int hdmi4_probe(struct platform_device *pdev) | ||
738 | { | ||
739 | return component_add(&pdev->dev, &hdmi4_component_ops); | ||
740 | } | ||
741 | |||
742 | static int hdmi4_remove(struct platform_device *pdev) | ||
743 | { | ||
744 | component_del(&pdev->dev, &hdmi4_component_ops); | ||
727 | return 0; | 745 | return 0; |
728 | } | 746 | } |
729 | 747 | ||
@@ -756,8 +774,8 @@ static const struct of_device_id hdmi_of_match[] = { | |||
756 | }; | 774 | }; |
757 | 775 | ||
758 | static struct platform_driver omapdss_hdmihw_driver = { | 776 | static struct platform_driver omapdss_hdmihw_driver = { |
759 | .probe = omapdss_hdmihw_probe, | 777 | .probe = hdmi4_probe, |
760 | .remove = __exit_p(omapdss_hdmihw_remove), | 778 | .remove = hdmi4_remove, |
761 | .driver = { | 779 | .driver = { |
762 | .name = "omapdss_hdmi", | 780 | .name = "omapdss_hdmi", |
763 | .pm = &hdmi_pm_ops, | 781 | .pm = &hdmi_pm_ops, |
@@ -771,7 +789,7 @@ int __init hdmi4_init_platform_driver(void) | |||
771 | return platform_driver_register(&omapdss_hdmihw_driver); | 789 | return platform_driver_register(&omapdss_hdmihw_driver); |
772 | } | 790 | } |
773 | 791 | ||
774 | void __exit hdmi4_uninit_platform_driver(void) | 792 | void hdmi4_uninit_platform_driver(void) |
775 | { | 793 | { |
776 | platform_driver_unregister(&omapdss_hdmihw_driver); | 794 | platform_driver_unregister(&omapdss_hdmihw_driver); |
777 | } | 795 | } |
diff --git a/drivers/video/fbdev/omap2/dss/hdmi4_core.c b/drivers/video/fbdev/omap2/dss/hdmi4_core.c index 7eafea5b8e19..fa72e735dad2 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4_core.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4_core.c | |||
@@ -654,6 +654,13 @@ static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core, | |||
654 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3); | 654 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3); |
655 | sum += info_aud->db3; | 655 | sum += info_aud->db3; |
656 | 656 | ||
657 | /* | ||
658 | * The OMAP HDMI IP requires to use the 8-channel channel code when | ||
659 | * transmitting more than two channels. | ||
660 | */ | ||
661 | if (info_aud->db4_ca != 0x00) | ||
662 | info_aud->db4_ca = 0x13; | ||
663 | |||
657 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca); | 664 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca); |
658 | sum += info_aud->db4_ca; | 665 | sum += info_aud->db4_ca; |
659 | 666 | ||
@@ -795,7 +802,9 @@ int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, | |||
795 | 802 | ||
796 | /* | 803 | /* |
797 | * the HDMI IP needs to enable four stereo channels when transmitting | 804 | * the HDMI IP needs to enable four stereo channels when transmitting |
798 | * more than 2 audio channels | 805 | * more than 2 audio channels. Similarly, the channel count in the |
806 | * Audio InfoFrame has to match the sample_present bits (some channels | ||
807 | * are padded with zeroes) | ||
799 | */ | 808 | */ |
800 | if (channel_count == 2) { | 809 | if (channel_count == 2) { |
801 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; | 810 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; |
@@ -807,6 +816,7 @@ int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, | |||
807 | HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | | 816 | HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | |
808 | HDMI_AUDIO_I2S_SD3_EN; | 817 | HDMI_AUDIO_I2S_SD3_EN; |
809 | acore.layout = HDMI_AUDIO_LAYOUT_8CH; | 818 | acore.layout = HDMI_AUDIO_LAYOUT_8CH; |
819 | audio->cea->db1_ct_cc = 7; | ||
810 | } | 820 | } |
811 | 821 | ||
812 | acore.en_spdif = false; | 822 | acore.en_spdif = false; |
diff --git a/drivers/video/fbdev/omap2/dss/hdmi5.c b/drivers/video/fbdev/omap2/dss/hdmi5.c index 3f0b34a7031a..7f875788edbc 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi5.c +++ b/drivers/video/fbdev/omap2/dss/hdmi5.c | |||
@@ -37,6 +37,7 @@ | |||
37 | #include <linux/clk.h> | 37 | #include <linux/clk.h> |
38 | #include <linux/gpio.h> | 38 | #include <linux/gpio.h> |
39 | #include <linux/regulator/consumer.h> | 39 | #include <linux/regulator/consumer.h> |
40 | #include <linux/component.h> | ||
40 | #include <video/omapdss.h> | 41 | #include <video/omapdss.h> |
41 | #include <sound/omap-hdmi-audio.h> | 42 | #include <sound/omap-hdmi-audio.h> |
42 | 43 | ||
@@ -681,8 +682,9 @@ static int hdmi_audio_register(struct device *dev) | |||
681 | } | 682 | } |
682 | 683 | ||
683 | /* HDMI HW IP initialisation */ | 684 | /* HDMI HW IP initialisation */ |
684 | static int omapdss_hdmihw_probe(struct platform_device *pdev) | 685 | static int hdmi5_bind(struct device *dev, struct device *master, void *data) |
685 | { | 686 | { |
687 | struct platform_device *pdev = to_platform_device(dev); | ||
686 | int r; | 688 | int r; |
687 | int irq; | 689 | int irq; |
688 | 690 | ||
@@ -748,8 +750,10 @@ err: | |||
748 | return r; | 750 | return r; |
749 | } | 751 | } |
750 | 752 | ||
751 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) | 753 | static void hdmi5_unbind(struct device *dev, struct device *master, void *data) |
752 | { | 754 | { |
755 | struct platform_device *pdev = to_platform_device(dev); | ||
756 | |||
753 | if (hdmi.audio_pdev) | 757 | if (hdmi.audio_pdev) |
754 | platform_device_unregister(hdmi.audio_pdev); | 758 | platform_device_unregister(hdmi.audio_pdev); |
755 | 759 | ||
@@ -758,7 +762,21 @@ static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) | |||
758 | hdmi_pll_uninit(&hdmi.pll); | 762 | hdmi_pll_uninit(&hdmi.pll); |
759 | 763 | ||
760 | pm_runtime_disable(&pdev->dev); | 764 | pm_runtime_disable(&pdev->dev); |
765 | } | ||
766 | |||
767 | static const struct component_ops hdmi5_component_ops = { | ||
768 | .bind = hdmi5_bind, | ||
769 | .unbind = hdmi5_unbind, | ||
770 | }; | ||
761 | 771 | ||
772 | static int hdmi5_probe(struct platform_device *pdev) | ||
773 | { | ||
774 | return component_add(&pdev->dev, &hdmi5_component_ops); | ||
775 | } | ||
776 | |||
777 | static int hdmi5_remove(struct platform_device *pdev) | ||
778 | { | ||
779 | component_del(&pdev->dev, &hdmi5_component_ops); | ||
762 | return 0; | 780 | return 0; |
763 | } | 781 | } |
764 | 782 | ||
@@ -792,8 +810,8 @@ static const struct of_device_id hdmi_of_match[] = { | |||
792 | }; | 810 | }; |
793 | 811 | ||
794 | static struct platform_driver omapdss_hdmihw_driver = { | 812 | static struct platform_driver omapdss_hdmihw_driver = { |
795 | .probe = omapdss_hdmihw_probe, | 813 | .probe = hdmi5_probe, |
796 | .remove = __exit_p(omapdss_hdmihw_remove), | 814 | .remove = hdmi5_remove, |
797 | .driver = { | 815 | .driver = { |
798 | .name = "omapdss_hdmi5", | 816 | .name = "omapdss_hdmi5", |
799 | .pm = &hdmi_pm_ops, | 817 | .pm = &hdmi_pm_ops, |
@@ -807,7 +825,7 @@ int __init hdmi5_init_platform_driver(void) | |||
807 | return platform_driver_register(&omapdss_hdmihw_driver); | 825 | return platform_driver_register(&omapdss_hdmihw_driver); |
808 | } | 826 | } |
809 | 827 | ||
810 | void __exit hdmi5_uninit_platform_driver(void) | 828 | void hdmi5_uninit_platform_driver(void) |
811 | { | 829 | { |
812 | platform_driver_unregister(&omapdss_hdmihw_driver); | 830 | platform_driver_unregister(&omapdss_hdmihw_driver); |
813 | } | 831 | } |
diff --git a/drivers/video/fbdev/omap2/dss/hdmi5_core.c b/drivers/video/fbdev/omap2/dss/hdmi5_core.c index bfc0c4c297d6..8ea531d2652c 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi5_core.c +++ b/drivers/video/fbdev/omap2/dss/hdmi5_core.c | |||
@@ -790,7 +790,9 @@ static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core, | |||
790 | 790 | ||
791 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss); | 791 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss); |
792 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca); | 792 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca); |
793 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, info_aud->db5_dminh_lsv); | 793 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, |
794 | (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 | | ||
795 | (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV)); | ||
794 | } | 796 | } |
795 | 797 | ||
796 | int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, | 798 | int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, |
@@ -870,6 +872,7 @@ int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, | |||
870 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; | 872 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; |
871 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; | 873 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; |
872 | audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; | 874 | audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
875 | audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; | ||
873 | 876 | ||
874 | /* only LPCM atm */ | 877 | /* only LPCM atm */ |
875 | audio_format.type = HDMI_AUDIO_TYPE_LPCM; | 878 | audio_format.type = HDMI_AUDIO_TYPE_LPCM; |
diff --git a/drivers/video/fbdev/omap2/dss/hdmi_wp.c b/drivers/video/fbdev/omap2/dss/hdmi_wp.c index c15377e242cc..7c544bc56fb5 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_wp.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_wp.c | |||
@@ -110,7 +110,23 @@ int hdmi_wp_video_start(struct hdmi_wp_data *wp) | |||
110 | 110 | ||
111 | void hdmi_wp_video_stop(struct hdmi_wp_data *wp) | 111 | void hdmi_wp_video_stop(struct hdmi_wp_data *wp) |
112 | { | 112 | { |
113 | int i; | ||
114 | |||
115 | hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE); | ||
116 | |||
113 | REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); | 117 | REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); |
118 | |||
119 | for (i = 0; i < 50; ++i) { | ||
120 | u32 v; | ||
121 | |||
122 | msleep(20); | ||
123 | |||
124 | v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW); | ||
125 | if (v & HDMI_IRQ_VIDEO_FRAME_DONE) | ||
126 | return; | ||
127 | } | ||
128 | |||
129 | DSSERR("no HDMI FRAMEDONE when disabling output\n"); | ||
114 | } | 130 | } |
115 | 131 | ||
116 | void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, | 132 | void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, |
diff --git a/drivers/video/fbdev/omap2/dss/rfbi.c b/drivers/video/fbdev/omap2/dss/rfbi.c index 065effca9236..1525a494d057 100644 --- a/drivers/video/fbdev/omap2/dss/rfbi.c +++ b/drivers/video/fbdev/omap2/dss/rfbi.c | |||
@@ -36,6 +36,7 @@ | |||
36 | #include <linux/semaphore.h> | 36 | #include <linux/semaphore.h> |
37 | #include <linux/platform_device.h> | 37 | #include <linux/platform_device.h> |
38 | #include <linux/pm_runtime.h> | 38 | #include <linux/pm_runtime.h> |
39 | #include <linux/component.h> | ||
39 | 40 | ||
40 | #include <video/omapdss.h> | 41 | #include <video/omapdss.h> |
41 | #include "dss.h" | 42 | #include "dss.h" |
@@ -938,7 +939,7 @@ static void rfbi_init_output(struct platform_device *pdev) | |||
938 | omapdss_register_output(out); | 939 | omapdss_register_output(out); |
939 | } | 940 | } |
940 | 941 | ||
941 | static void __exit rfbi_uninit_output(struct platform_device *pdev) | 942 | static void rfbi_uninit_output(struct platform_device *pdev) |
942 | { | 943 | { |
943 | struct omap_dss_device *out = &rfbi.output; | 944 | struct omap_dss_device *out = &rfbi.output; |
944 | 945 | ||
@@ -946,8 +947,9 @@ static void __exit rfbi_uninit_output(struct platform_device *pdev) | |||
946 | } | 947 | } |
947 | 948 | ||
948 | /* RFBI HW IP initialisation */ | 949 | /* RFBI HW IP initialisation */ |
949 | static int omap_rfbihw_probe(struct platform_device *pdev) | 950 | static int rfbi_bind(struct device *dev, struct device *master, void *data) |
950 | { | 951 | { |
952 | struct platform_device *pdev = to_platform_device(dev); | ||
951 | u32 rev; | 953 | u32 rev; |
952 | struct resource *rfbi_mem; | 954 | struct resource *rfbi_mem; |
953 | struct clk *clk; | 955 | struct clk *clk; |
@@ -1005,8 +1007,10 @@ err_runtime_get: | |||
1005 | return r; | 1007 | return r; |
1006 | } | 1008 | } |
1007 | 1009 | ||
1008 | static int __exit omap_rfbihw_remove(struct platform_device *pdev) | 1010 | static void rfbi_unbind(struct device *dev, struct device *master, void *data) |
1009 | { | 1011 | { |
1012 | struct platform_device *pdev = to_platform_device(dev); | ||
1013 | |||
1010 | rfbi_uninit_output(pdev); | 1014 | rfbi_uninit_output(pdev); |
1011 | 1015 | ||
1012 | pm_runtime_disable(&pdev->dev); | 1016 | pm_runtime_disable(&pdev->dev); |
@@ -1014,6 +1018,22 @@ static int __exit omap_rfbihw_remove(struct platform_device *pdev) | |||
1014 | return 0; | 1018 | return 0; |
1015 | } | 1019 | } |
1016 | 1020 | ||
1021 | static const struct component_ops rfbi_component_ops = { | ||
1022 | .bind = rfbi_bind, | ||
1023 | .unbind = rfbi_unbind, | ||
1024 | }; | ||
1025 | |||
1026 | static int rfbi_probe(struct platform_device *pdev) | ||
1027 | { | ||
1028 | return component_add(&pdev->dev, &rfbi_component_ops); | ||
1029 | } | ||
1030 | |||
1031 | static int rfbi_remove(struct platform_device *pdev) | ||
1032 | { | ||
1033 | component_del(&pdev->dev, &rfbi_component_ops); | ||
1034 | return 0; | ||
1035 | } | ||
1036 | |||
1017 | static int rfbi_runtime_suspend(struct device *dev) | 1037 | static int rfbi_runtime_suspend(struct device *dev) |
1018 | { | 1038 | { |
1019 | dispc_runtime_put(); | 1039 | dispc_runtime_put(); |
@@ -1038,8 +1058,8 @@ static const struct dev_pm_ops rfbi_pm_ops = { | |||
1038 | }; | 1058 | }; |
1039 | 1059 | ||
1040 | static struct platform_driver omap_rfbihw_driver = { | 1060 | static struct platform_driver omap_rfbihw_driver = { |
1041 | .probe = omap_rfbihw_probe, | 1061 | .probe = rfbi_probe, |
1042 | .remove = __exit_p(omap_rfbihw_remove), | 1062 | .remove = rfbi_remove, |
1043 | .driver = { | 1063 | .driver = { |
1044 | .name = "omapdss_rfbi", | 1064 | .name = "omapdss_rfbi", |
1045 | .pm = &rfbi_pm_ops, | 1065 | .pm = &rfbi_pm_ops, |
@@ -1052,7 +1072,7 @@ int __init rfbi_init_platform_driver(void) | |||
1052 | return platform_driver_register(&omap_rfbihw_driver); | 1072 | return platform_driver_register(&omap_rfbihw_driver); |
1053 | } | 1073 | } |
1054 | 1074 | ||
1055 | void __exit rfbi_uninit_platform_driver(void) | 1075 | void rfbi_uninit_platform_driver(void) |
1056 | { | 1076 | { |
1057 | platform_driver_unregister(&omap_rfbihw_driver); | 1077 | platform_driver_unregister(&omap_rfbihw_driver); |
1058 | } | 1078 | } |
diff --git a/drivers/video/fbdev/omap2/dss/sdi.c b/drivers/video/fbdev/omap2/dss/sdi.c index 5c2ccab5a958..5843580a1deb 100644 --- a/drivers/video/fbdev/omap2/dss/sdi.c +++ b/drivers/video/fbdev/omap2/dss/sdi.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <linux/platform_device.h> | 27 | #include <linux/platform_device.h> |
28 | #include <linux/string.h> | 28 | #include <linux/string.h> |
29 | #include <linux/of.h> | 29 | #include <linux/of.h> |
30 | #include <linux/component.h> | ||
30 | 31 | ||
31 | #include <video/omapdss.h> | 32 | #include <video/omapdss.h> |
32 | #include "dss.h" | 33 | #include "dss.h" |
@@ -350,15 +351,17 @@ static void sdi_init_output(struct platform_device *pdev) | |||
350 | omapdss_register_output(out); | 351 | omapdss_register_output(out); |
351 | } | 352 | } |
352 | 353 | ||
353 | static void __exit sdi_uninit_output(struct platform_device *pdev) | 354 | static void sdi_uninit_output(struct platform_device *pdev) |
354 | { | 355 | { |
355 | struct omap_dss_device *out = &sdi.output; | 356 | struct omap_dss_device *out = &sdi.output; |
356 | 357 | ||
357 | omapdss_unregister_output(out); | 358 | omapdss_unregister_output(out); |
358 | } | 359 | } |
359 | 360 | ||
360 | static int omap_sdi_probe(struct platform_device *pdev) | 361 | static int sdi_bind(struct device *dev, struct device *master, void *data) |
361 | { | 362 | { |
363 | struct platform_device *pdev = to_platform_device(dev); | ||
364 | |||
362 | sdi.pdev = pdev; | 365 | sdi.pdev = pdev; |
363 | 366 | ||
364 | sdi_init_output(pdev); | 367 | sdi_init_output(pdev); |
@@ -366,16 +369,32 @@ static int omap_sdi_probe(struct platform_device *pdev) | |||
366 | return 0; | 369 | return 0; |
367 | } | 370 | } |
368 | 371 | ||
369 | static int __exit omap_sdi_remove(struct platform_device *pdev) | 372 | static void sdi_unbind(struct device *dev, struct device *master, void *data) |
370 | { | 373 | { |
374 | struct platform_device *pdev = to_platform_device(dev); | ||
375 | |||
371 | sdi_uninit_output(pdev); | 376 | sdi_uninit_output(pdev); |
377 | } | ||
378 | |||
379 | static const struct component_ops sdi_component_ops = { | ||
380 | .bind = sdi_bind, | ||
381 | .unbind = sdi_unbind, | ||
382 | }; | ||
372 | 383 | ||
384 | static int sdi_probe(struct platform_device *pdev) | ||
385 | { | ||
386 | return component_add(&pdev->dev, &sdi_component_ops); | ||
387 | } | ||
388 | |||
389 | static int sdi_remove(struct platform_device *pdev) | ||
390 | { | ||
391 | component_del(&pdev->dev, &sdi_component_ops); | ||
373 | return 0; | 392 | return 0; |
374 | } | 393 | } |
375 | 394 | ||
376 | static struct platform_driver omap_sdi_driver = { | 395 | static struct platform_driver omap_sdi_driver = { |
377 | .probe = omap_sdi_probe, | 396 | .probe = sdi_probe, |
378 | .remove = __exit_p(omap_sdi_remove), | 397 | .remove = sdi_remove, |
379 | .driver = { | 398 | .driver = { |
380 | .name = "omapdss_sdi", | 399 | .name = "omapdss_sdi", |
381 | .suppress_bind_attrs = true, | 400 | .suppress_bind_attrs = true, |
@@ -387,12 +406,12 @@ int __init sdi_init_platform_driver(void) | |||
387 | return platform_driver_register(&omap_sdi_driver); | 406 | return platform_driver_register(&omap_sdi_driver); |
388 | } | 407 | } |
389 | 408 | ||
390 | void __exit sdi_uninit_platform_driver(void) | 409 | void sdi_uninit_platform_driver(void) |
391 | { | 410 | { |
392 | platform_driver_unregister(&omap_sdi_driver); | 411 | platform_driver_unregister(&omap_sdi_driver); |
393 | } | 412 | } |
394 | 413 | ||
395 | int __init sdi_init_port(struct platform_device *pdev, struct device_node *port) | 414 | int sdi_init_port(struct platform_device *pdev, struct device_node *port) |
396 | { | 415 | { |
397 | struct device_node *ep; | 416 | struct device_node *ep; |
398 | u32 datapairs; | 417 | u32 datapairs; |
@@ -426,7 +445,7 @@ err_datapairs: | |||
426 | return r; | 445 | return r; |
427 | } | 446 | } |
428 | 447 | ||
429 | void __exit sdi_uninit_port(struct device_node *port) | 448 | void sdi_uninit_port(struct device_node *port) |
430 | { | 449 | { |
431 | if (!sdi.port_initialized) | 450 | if (!sdi.port_initialized) |
432 | return; | 451 | return; |
diff --git a/drivers/video/fbdev/omap2/dss/venc.c b/drivers/video/fbdev/omap2/dss/venc.c index ef7fd925e7f2..99ca268c1cdd 100644 --- a/drivers/video/fbdev/omap2/dss/venc.c +++ b/drivers/video/fbdev/omap2/dss/venc.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include <linux/regulator/consumer.h> | 35 | #include <linux/regulator/consumer.h> |
36 | #include <linux/pm_runtime.h> | 36 | #include <linux/pm_runtime.h> |
37 | #include <linux/of.h> | 37 | #include <linux/of.h> |
38 | #include <linux/component.h> | ||
38 | 39 | ||
39 | #include <video/omapdss.h> | 40 | #include <video/omapdss.h> |
40 | 41 | ||
@@ -802,7 +803,7 @@ static void venc_init_output(struct platform_device *pdev) | |||
802 | omapdss_register_output(out); | 803 | omapdss_register_output(out); |
803 | } | 804 | } |
804 | 805 | ||
805 | static void __exit venc_uninit_output(struct platform_device *pdev) | 806 | static void venc_uninit_output(struct platform_device *pdev) |
806 | { | 807 | { |
807 | struct omap_dss_device *out = &venc.output; | 808 | struct omap_dss_device *out = &venc.output; |
808 | 809 | ||
@@ -852,8 +853,9 @@ err: | |||
852 | } | 853 | } |
853 | 854 | ||
854 | /* VENC HW IP initialisation */ | 855 | /* VENC HW IP initialisation */ |
855 | static int omap_venchw_probe(struct platform_device *pdev) | 856 | static int venc_bind(struct device *dev, struct device *master, void *data) |
856 | { | 857 | { |
858 | struct platform_device *pdev = to_platform_device(dev); | ||
857 | u8 rev_id; | 859 | u8 rev_id; |
858 | struct resource *venc_mem; | 860 | struct resource *venc_mem; |
859 | int r; | 861 | int r; |
@@ -912,12 +914,28 @@ err_runtime_get: | |||
912 | return r; | 914 | return r; |
913 | } | 915 | } |
914 | 916 | ||
915 | static int __exit omap_venchw_remove(struct platform_device *pdev) | 917 | static void venc_unbind(struct device *dev, struct device *master, void *data) |
916 | { | 918 | { |
919 | struct platform_device *pdev = to_platform_device(dev); | ||
920 | |||
917 | venc_uninit_output(pdev); | 921 | venc_uninit_output(pdev); |
918 | 922 | ||
919 | pm_runtime_disable(&pdev->dev); | 923 | pm_runtime_disable(&pdev->dev); |
924 | } | ||
920 | 925 | ||
926 | static const struct component_ops venc_component_ops = { | ||
927 | .bind = venc_bind, | ||
928 | .unbind = venc_unbind, | ||
929 | }; | ||
930 | |||
931 | static int venc_probe(struct platform_device *pdev) | ||
932 | { | ||
933 | return component_add(&pdev->dev, &venc_component_ops); | ||
934 | } | ||
935 | |||
936 | static int venc_remove(struct platform_device *pdev) | ||
937 | { | ||
938 | component_del(&pdev->dev, &venc_component_ops); | ||
921 | return 0; | 939 | return 0; |
922 | } | 940 | } |
923 | 941 | ||
@@ -950,7 +968,6 @@ static const struct dev_pm_ops venc_pm_ops = { | |||
950 | .runtime_resume = venc_runtime_resume, | 968 | .runtime_resume = venc_runtime_resume, |
951 | }; | 969 | }; |
952 | 970 | ||
953 | |||
954 | static const struct of_device_id venc_of_match[] = { | 971 | static const struct of_device_id venc_of_match[] = { |
955 | { .compatible = "ti,omap2-venc", }, | 972 | { .compatible = "ti,omap2-venc", }, |
956 | { .compatible = "ti,omap3-venc", }, | 973 | { .compatible = "ti,omap3-venc", }, |
@@ -959,8 +976,8 @@ static const struct of_device_id venc_of_match[] = { | |||
959 | }; | 976 | }; |
960 | 977 | ||
961 | static struct platform_driver omap_venchw_driver = { | 978 | static struct platform_driver omap_venchw_driver = { |
962 | .probe = omap_venchw_probe, | 979 | .probe = venc_probe, |
963 | .remove = __exit_p(omap_venchw_remove), | 980 | .remove = venc_remove, |
964 | .driver = { | 981 | .driver = { |
965 | .name = "omapdss_venc", | 982 | .name = "omapdss_venc", |
966 | .pm = &venc_pm_ops, | 983 | .pm = &venc_pm_ops, |
@@ -974,7 +991,7 @@ int __init venc_init_platform_driver(void) | |||
974 | return platform_driver_register(&omap_venchw_driver); | 991 | return platform_driver_register(&omap_venchw_driver); |
975 | } | 992 | } |
976 | 993 | ||
977 | void __exit venc_uninit_platform_driver(void) | 994 | void venc_uninit_platform_driver(void) |
978 | { | 995 | { |
979 | platform_driver_unregister(&omap_venchw_driver); | 996 | platform_driver_unregister(&omap_venchw_driver); |
980 | } | 997 | } |
diff --git a/drivers/video/fbdev/pm2fb.c b/drivers/video/fbdev/pm2fb.c index 3b85b647bc10..aa8d28880912 100644 --- a/drivers/video/fbdev/pm2fb.c +++ b/drivers/video/fbdev/pm2fb.c | |||
@@ -38,10 +38,6 @@ | |||
38 | #include <linux/fb.h> | 38 | #include <linux/fb.h> |
39 | #include <linux/init.h> | 39 | #include <linux/init.h> |
40 | #include <linux/pci.h> | 40 | #include <linux/pci.h> |
41 | #ifdef CONFIG_MTRR | ||
42 | #include <asm/mtrr.h> | ||
43 | #endif | ||
44 | |||
45 | #include <video/permedia2.h> | 41 | #include <video/permedia2.h> |
46 | #include <video/cvisionppc.h> | 42 | #include <video/cvisionppc.h> |
47 | 43 | ||
@@ -81,10 +77,7 @@ static char *mode_option; | |||
81 | static bool lowhsync; | 77 | static bool lowhsync; |
82 | static bool lowvsync; | 78 | static bool lowvsync; |
83 | static bool noaccel; | 79 | static bool noaccel; |
84 | /* mtrr option */ | ||
85 | #ifdef CONFIG_MTRR | ||
86 | static bool nomtrr; | 80 | static bool nomtrr; |
87 | #endif | ||
88 | 81 | ||
89 | /* | 82 | /* |
90 | * The hardware state of the graphics card that isn't part of the | 83 | * The hardware state of the graphics card that isn't part of the |
@@ -100,7 +93,7 @@ struct pm2fb_par | |||
100 | u32 mem_control; /* MemControl reg at probe */ | 93 | u32 mem_control; /* MemControl reg at probe */ |
101 | u32 boot_address; /* BootAddress reg at probe */ | 94 | u32 boot_address; /* BootAddress reg at probe */ |
102 | u32 palette[16]; | 95 | u32 palette[16]; |
103 | int mtrr_handle; | 96 | int wc_cookie; |
104 | }; | 97 | }; |
105 | 98 | ||
106 | /* | 99 | /* |
@@ -1637,21 +1630,16 @@ static int pm2fb_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1637 | goto err_exit_mmio; | 1630 | goto err_exit_mmio; |
1638 | } | 1631 | } |
1639 | info->screen_base = | 1632 | info->screen_base = |
1640 | ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len); | 1633 | ioremap_wc(pm2fb_fix.smem_start, pm2fb_fix.smem_len); |
1641 | if (!info->screen_base) { | 1634 | if (!info->screen_base) { |
1642 | printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n"); | 1635 | printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n"); |
1643 | release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); | 1636 | release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); |
1644 | goto err_exit_mmio; | 1637 | goto err_exit_mmio; |
1645 | } | 1638 | } |
1646 | 1639 | ||
1647 | #ifdef CONFIG_MTRR | ||
1648 | default_par->mtrr_handle = -1; | ||
1649 | if (!nomtrr) | 1640 | if (!nomtrr) |
1650 | default_par->mtrr_handle = | 1641 | default_par->wc_cookie = arch_phys_wc_add(pm2fb_fix.smem_start, |
1651 | mtrr_add(pm2fb_fix.smem_start, | 1642 | pm2fb_fix.smem_len); |
1652 | pm2fb_fix.smem_len, | ||
1653 | MTRR_TYPE_WRCOMB, 1); | ||
1654 | #endif | ||
1655 | 1643 | ||
1656 | info->fbops = &pm2fb_ops; | 1644 | info->fbops = &pm2fb_ops; |
1657 | info->fix = pm2fb_fix; | 1645 | info->fix = pm2fb_fix; |
@@ -1733,12 +1721,7 @@ static void pm2fb_remove(struct pci_dev *pdev) | |||
1733 | struct pm2fb_par *par = info->par; | 1721 | struct pm2fb_par *par = info->par; |
1734 | 1722 | ||
1735 | unregister_framebuffer(info); | 1723 | unregister_framebuffer(info); |
1736 | 1724 | arch_phys_wc_del(par->wc_cookie); | |
1737 | #ifdef CONFIG_MTRR | ||
1738 | if (par->mtrr_handle >= 0) | ||
1739 | mtrr_del(par->mtrr_handle, info->fix.smem_start, | ||
1740 | info->fix.smem_len); | ||
1741 | #endif /* CONFIG_MTRR */ | ||
1742 | iounmap(info->screen_base); | 1725 | iounmap(info->screen_base); |
1743 | release_mem_region(fix->smem_start, fix->smem_len); | 1726 | release_mem_region(fix->smem_start, fix->smem_len); |
1744 | iounmap(par->v_regs); | 1727 | iounmap(par->v_regs); |
@@ -1791,10 +1774,8 @@ static int __init pm2fb_setup(char *options) | |||
1791 | lowvsync = 1; | 1774 | lowvsync = 1; |
1792 | else if (!strncmp(this_opt, "hwcursor=", 9)) | 1775 | else if (!strncmp(this_opt, "hwcursor=", 9)) |
1793 | hwcursor = simple_strtoul(this_opt + 9, NULL, 0); | 1776 | hwcursor = simple_strtoul(this_opt + 9, NULL, 0); |
1794 | #ifdef CONFIG_MTRR | ||
1795 | else if (!strncmp(this_opt, "nomtrr", 6)) | 1777 | else if (!strncmp(this_opt, "nomtrr", 6)) |
1796 | nomtrr = 1; | 1778 | nomtrr = 1; |
1797 | #endif | ||
1798 | else if (!strncmp(this_opt, "noaccel", 7)) | 1779 | else if (!strncmp(this_opt, "noaccel", 7)) |
1799 | noaccel = 1; | 1780 | noaccel = 1; |
1800 | else | 1781 | else |
@@ -1847,10 +1828,8 @@ MODULE_PARM_DESC(noaccel, "Disable acceleration"); | |||
1847 | module_param(hwcursor, int, 0644); | 1828 | module_param(hwcursor, int, 0644); |
1848 | MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " | 1829 | MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " |
1849 | "(1=enable, 0=disable, default=1)"); | 1830 | "(1=enable, 0=disable, default=1)"); |
1850 | #ifdef CONFIG_MTRR | ||
1851 | module_param(nomtrr, bool, 0); | 1831 | module_param(nomtrr, bool, 0); |
1852 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)"); | 1832 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)"); |
1853 | #endif | ||
1854 | 1833 | ||
1855 | MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>"); | 1834 | MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>"); |
1856 | MODULE_DESCRIPTION("Permedia2 framebuffer device driver"); | 1835 | MODULE_DESCRIPTION("Permedia2 framebuffer device driver"); |
diff --git a/drivers/video/fbdev/pm3fb.c b/drivers/video/fbdev/pm3fb.c index 77b99ed39ad0..6ff5077a2e15 100644 --- a/drivers/video/fbdev/pm3fb.c +++ b/drivers/video/fbdev/pm3fb.c | |||
@@ -32,9 +32,6 @@ | |||
32 | #include <linux/fb.h> | 32 | #include <linux/fb.h> |
33 | #include <linux/init.h> | 33 | #include <linux/init.h> |
34 | #include <linux/pci.h> | 34 | #include <linux/pci.h> |
35 | #ifdef CONFIG_MTRR | ||
36 | #include <asm/mtrr.h> | ||
37 | #endif | ||
38 | 35 | ||
39 | #include <video/pm3fb.h> | 36 | #include <video/pm3fb.h> |
40 | 37 | ||
@@ -58,11 +55,7 @@ | |||
58 | static int hwcursor = 1; | 55 | static int hwcursor = 1; |
59 | static char *mode_option; | 56 | static char *mode_option; |
60 | static bool noaccel; | 57 | static bool noaccel; |
61 | |||
62 | /* mtrr option */ | ||
63 | #ifdef CONFIG_MTRR | ||
64 | static bool nomtrr; | 58 | static bool nomtrr; |
65 | #endif | ||
66 | 59 | ||
67 | /* | 60 | /* |
68 | * This structure defines the hardware state of the graphics card. Normally | 61 | * This structure defines the hardware state of the graphics card. Normally |
@@ -76,7 +69,7 @@ struct pm3_par { | |||
76 | u32 video; /* video flags before blanking */ | 69 | u32 video; /* video flags before blanking */ |
77 | u32 base; /* screen base in 128 bits unit */ | 70 | u32 base; /* screen base in 128 bits unit */ |
78 | u32 palette[16]; | 71 | u32 palette[16]; |
79 | int mtrr_handle; | 72 | int wc_cookie; |
80 | }; | 73 | }; |
81 | 74 | ||
82 | /* | 75 | /* |
@@ -1374,8 +1367,8 @@ static int pm3fb_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |||
1374 | printk(KERN_WARNING "pm3fb: Can't reserve smem.\n"); | 1367 | printk(KERN_WARNING "pm3fb: Can't reserve smem.\n"); |
1375 | goto err_exit_mmio; | 1368 | goto err_exit_mmio; |
1376 | } | 1369 | } |
1377 | info->screen_base = | 1370 | info->screen_base = ioremap_wc(pm3fb_fix.smem_start, |
1378 | ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len); | 1371 | pm3fb_fix.smem_len); |
1379 | if (!info->screen_base) { | 1372 | if (!info->screen_base) { |
1380 | printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n"); | 1373 | printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n"); |
1381 | release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len); | 1374 | release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len); |
@@ -1383,12 +1376,9 @@ static int pm3fb_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |||
1383 | } | 1376 | } |
1384 | info->screen_size = pm3fb_fix.smem_len; | 1377 | info->screen_size = pm3fb_fix.smem_len; |
1385 | 1378 | ||
1386 | #ifdef CONFIG_MTRR | ||
1387 | if (!nomtrr) | 1379 | if (!nomtrr) |
1388 | par->mtrr_handle = mtrr_add(pm3fb_fix.smem_start, | 1380 | par->wc_cookie = arch_phys_wc_add(pm3fb_fix.smem_start, |
1389 | pm3fb_fix.smem_len, | 1381 | pm3fb_fix.smem_len); |
1390 | MTRR_TYPE_WRCOMB, 1); | ||
1391 | #endif | ||
1392 | info->fbops = &pm3fb_ops; | 1382 | info->fbops = &pm3fb_ops; |
1393 | 1383 | ||
1394 | par->video = PM3_READ_REG(par, PM3VideoControl); | 1384 | par->video = PM3_READ_REG(par, PM3VideoControl); |
@@ -1478,11 +1468,7 @@ static void pm3fb_remove(struct pci_dev *dev) | |||
1478 | unregister_framebuffer(info); | 1468 | unregister_framebuffer(info); |
1479 | fb_dealloc_cmap(&info->cmap); | 1469 | fb_dealloc_cmap(&info->cmap); |
1480 | 1470 | ||
1481 | #ifdef CONFIG_MTRR | 1471 | arch_phys_wc_del(par->wc_cookie); |
1482 | if (par->mtrr_handle >= 0) | ||
1483 | mtrr_del(par->mtrr_handle, info->fix.smem_start, | ||
1484 | info->fix.smem_len); | ||
1485 | #endif /* CONFIG_MTRR */ | ||
1486 | iounmap(info->screen_base); | 1472 | iounmap(info->screen_base); |
1487 | release_mem_region(fix->smem_start, fix->smem_len); | 1473 | release_mem_region(fix->smem_start, fix->smem_len); |
1488 | iounmap(par->v_regs); | 1474 | iounmap(par->v_regs); |
@@ -1533,10 +1519,8 @@ static int __init pm3fb_setup(char *options) | |||
1533 | noaccel = 1; | 1519 | noaccel = 1; |
1534 | else if (!strncmp(this_opt, "hwcursor=", 9)) | 1520 | else if (!strncmp(this_opt, "hwcursor=", 9)) |
1535 | hwcursor = simple_strtoul(this_opt + 9, NULL, 0); | 1521 | hwcursor = simple_strtoul(this_opt + 9, NULL, 0); |
1536 | #ifdef CONFIG_MTRR | ||
1537 | else if (!strncmp(this_opt, "nomtrr", 6)) | 1522 | else if (!strncmp(this_opt, "nomtrr", 6)) |
1538 | nomtrr = 1; | 1523 | nomtrr = 1; |
1539 | #endif | ||
1540 | else | 1524 | else |
1541 | mode_option = this_opt; | 1525 | mode_option = this_opt; |
1542 | } | 1526 | } |
@@ -1577,10 +1561,8 @@ MODULE_PARM_DESC(noaccel, "Disable acceleration"); | |||
1577 | module_param(hwcursor, int, 0644); | 1561 | module_param(hwcursor, int, 0644); |
1578 | MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " | 1562 | MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " |
1579 | "(1=enable, 0=disable, default=1)"); | 1563 | "(1=enable, 0=disable, default=1)"); |
1580 | #ifdef CONFIG_MTRR | ||
1581 | module_param(nomtrr, bool, 0); | 1564 | module_param(nomtrr, bool, 0); |
1582 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)"); | 1565 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)"); |
1583 | #endif | ||
1584 | 1566 | ||
1585 | MODULE_DESCRIPTION("Permedia3 framebuffer device driver"); | 1567 | MODULE_DESCRIPTION("Permedia3 framebuffer device driver"); |
1586 | MODULE_LICENSE("GPL"); | 1568 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/video/fbdev/riva/fbdev.c b/drivers/video/fbdev/riva/fbdev.c index 294a80908c8c..f1ad2747064b 100644 --- a/drivers/video/fbdev/riva/fbdev.c +++ b/drivers/video/fbdev/riva/fbdev.c | |||
@@ -41,9 +41,6 @@ | |||
41 | #include <linux/pci.h> | 41 | #include <linux/pci.h> |
42 | #include <linux/backlight.h> | 42 | #include <linux/backlight.h> |
43 | #include <linux/bitrev.h> | 43 | #include <linux/bitrev.h> |
44 | #ifdef CONFIG_MTRR | ||
45 | #include <asm/mtrr.h> | ||
46 | #endif | ||
47 | #ifdef CONFIG_PMAC_BACKLIGHT | 44 | #ifdef CONFIG_PMAC_BACKLIGHT |
48 | #include <asm/machdep.h> | 45 | #include <asm/machdep.h> |
49 | #include <asm/backlight.h> | 46 | #include <asm/backlight.h> |
@@ -204,9 +201,7 @@ MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); | |||
204 | static int flatpanel = -1; /* Autodetect later */ | 201 | static int flatpanel = -1; /* Autodetect later */ |
205 | static int forceCRTC = -1; | 202 | static int forceCRTC = -1; |
206 | static bool noaccel = 0; | 203 | static bool noaccel = 0; |
207 | #ifdef CONFIG_MTRR | ||
208 | static bool nomtrr = 0; | 204 | static bool nomtrr = 0; |
209 | #endif | ||
210 | #ifdef CONFIG_PMAC_BACKLIGHT | 205 | #ifdef CONFIG_PMAC_BACKLIGHT |
211 | static int backlight = 1; | 206 | static int backlight = 1; |
212 | #else | 207 | #else |
@@ -2010,28 +2005,18 @@ static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) | |||
2010 | 2005 | ||
2011 | rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; | 2006 | rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; |
2012 | default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; | 2007 | default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; |
2013 | info->screen_base = ioremap(rivafb_fix.smem_start, | 2008 | info->screen_base = ioremap_wc(rivafb_fix.smem_start, |
2014 | rivafb_fix.smem_len); | 2009 | rivafb_fix.smem_len); |
2015 | if (!info->screen_base) { | 2010 | if (!info->screen_base) { |
2016 | printk(KERN_ERR PFX "cannot ioremap FB base\n"); | 2011 | printk(KERN_ERR PFX "cannot ioremap FB base\n"); |
2017 | ret = -EIO; | 2012 | ret = -EIO; |
2018 | goto err_iounmap_pramin; | 2013 | goto err_iounmap_pramin; |
2019 | } | 2014 | } |
2020 | 2015 | ||
2021 | #ifdef CONFIG_MTRR | 2016 | if (!nomtrr) |
2022 | if (!nomtrr) { | 2017 | default_par->wc_cookie = |
2023 | default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start, | 2018 | arch_phys_wc_add(rivafb_fix.smem_start, |
2024 | rivafb_fix.smem_len, | 2019 | rivafb_fix.smem_len); |
2025 | MTRR_TYPE_WRCOMB, 1); | ||
2026 | if (default_par->mtrr.vram < 0) { | ||
2027 | printk(KERN_ERR PFX "unable to setup MTRR\n"); | ||
2028 | } else { | ||
2029 | default_par->mtrr.vram_valid = 1; | ||
2030 | /* let there be speed */ | ||
2031 | printk(KERN_INFO PFX "RIVA MTRR set to ON\n"); | ||
2032 | } | ||
2033 | } | ||
2034 | #endif /* CONFIG_MTRR */ | ||
2035 | 2020 | ||
2036 | info->fbops = &riva_fb_ops; | 2021 | info->fbops = &riva_fb_ops; |
2037 | info->fix = rivafb_fix; | 2022 | info->fix = rivafb_fix; |
@@ -2105,13 +2090,7 @@ static void rivafb_remove(struct pci_dev *pd) | |||
2105 | unregister_framebuffer(info); | 2090 | unregister_framebuffer(info); |
2106 | 2091 | ||
2107 | riva_bl_exit(info); | 2092 | riva_bl_exit(info); |
2108 | 2093 | arch_phys_wc_del(par->wc_cookie); | |
2109 | #ifdef CONFIG_MTRR | ||
2110 | if (par->mtrr.vram_valid) | ||
2111 | mtrr_del(par->mtrr.vram, info->fix.smem_start, | ||
2112 | info->fix.smem_len); | ||
2113 | #endif /* CONFIG_MTRR */ | ||
2114 | |||
2115 | iounmap(par->ctrl_base); | 2094 | iounmap(par->ctrl_base); |
2116 | iounmap(info->screen_base); | 2095 | iounmap(info->screen_base); |
2117 | if (par->riva.Architecture == NV_ARCH_03) | 2096 | if (par->riva.Architecture == NV_ARCH_03) |
@@ -2150,10 +2129,8 @@ static int rivafb_setup(char *options) | |||
2150 | flatpanel = 1; | 2129 | flatpanel = 1; |
2151 | } else if (!strncmp(this_opt, "backlight:", 10)) { | 2130 | } else if (!strncmp(this_opt, "backlight:", 10)) { |
2152 | backlight = simple_strtoul(this_opt+10, NULL, 0); | 2131 | backlight = simple_strtoul(this_opt+10, NULL, 0); |
2153 | #ifdef CONFIG_MTRR | ||
2154 | } else if (!strncmp(this_opt, "nomtrr", 6)) { | 2132 | } else if (!strncmp(this_opt, "nomtrr", 6)) { |
2155 | nomtrr = 1; | 2133 | nomtrr = 1; |
2156 | #endif | ||
2157 | } else if (!strncmp(this_opt, "strictmode", 10)) { | 2134 | } else if (!strncmp(this_opt, "strictmode", 10)) { |
2158 | strictmode = 1; | 2135 | strictmode = 1; |
2159 | } else if (!strncmp(this_opt, "noaccel", 7)) { | 2136 | } else if (!strncmp(this_opt, "noaccel", 7)) { |
@@ -2209,10 +2186,8 @@ module_param(flatpanel, int, 0); | |||
2209 | MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); | 2186 | MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); |
2210 | module_param(forceCRTC, int, 0); | 2187 | module_param(forceCRTC, int, 0); |
2211 | MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); | 2188 | MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); |
2212 | #ifdef CONFIG_MTRR | ||
2213 | module_param(nomtrr, bool, 0); | 2189 | module_param(nomtrr, bool, 0); |
2214 | MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); | 2190 | MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); |
2215 | #endif | ||
2216 | module_param(strictmode, bool, 0); | 2191 | module_param(strictmode, bool, 0); |
2217 | MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); | 2192 | MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); |
2218 | 2193 | ||
diff --git a/drivers/video/fbdev/riva/rivafb.h b/drivers/video/fbdev/riva/rivafb.h index d9f107b704c6..61fd37ca490a 100644 --- a/drivers/video/fbdev/riva/rivafb.h +++ b/drivers/video/fbdev/riva/rivafb.h | |||
@@ -61,9 +61,7 @@ struct riva_par { | |||
61 | int FlatPanel; | 61 | int FlatPanel; |
62 | struct pci_dev *pdev; | 62 | struct pci_dev *pdev; |
63 | int cursor_reset; | 63 | int cursor_reset; |
64 | #ifdef CONFIG_MTRR | 64 | int wc_cookie; |
65 | struct { int vram; int vram_valid; } mtrr; | ||
66 | #endif | ||
67 | struct riva_i2c_chan chan[3]; | 65 | struct riva_i2c_chan chan[3]; |
68 | }; | 66 | }; |
69 | 67 | ||
diff --git a/drivers/video/fbdev/savage/savagefb.h b/drivers/video/fbdev/savage/savagefb.h index 8ff4ab1cb69b..aba04afe712d 100644 --- a/drivers/video/fbdev/savage/savagefb.h +++ b/drivers/video/fbdev/savage/savagefb.h | |||
@@ -213,9 +213,7 @@ struct savagefb_par { | |||
213 | void __iomem *vbase; | 213 | void __iomem *vbase; |
214 | u32 pbase; | 214 | u32 pbase; |
215 | u32 len; | 215 | u32 len; |
216 | #ifdef CONFIG_MTRR | 216 | int wc_cookie; |
217 | int mtrr; | ||
218 | #endif | ||
219 | } video; | 217 | } video; |
220 | 218 | ||
221 | struct { | 219 | struct { |
diff --git a/drivers/video/fbdev/savage/savagefb_driver.c b/drivers/video/fbdev/savage/savagefb_driver.c index 4dbf45f3b21a..6c77ab09b0b2 100644 --- a/drivers/video/fbdev/savage/savagefb_driver.c +++ b/drivers/video/fbdev/savage/savagefb_driver.c | |||
@@ -57,10 +57,6 @@ | |||
57 | #include <asm/irq.h> | 57 | #include <asm/irq.h> |
58 | #include <asm/pgtable.h> | 58 | #include <asm/pgtable.h> |
59 | 59 | ||
60 | #ifdef CONFIG_MTRR | ||
61 | #include <asm/mtrr.h> | ||
62 | #endif | ||
63 | |||
64 | #include "savagefb.h" | 60 | #include "savagefb.h" |
65 | 61 | ||
66 | 62 | ||
@@ -1775,7 +1771,7 @@ static int savage_map_video(struct fb_info *info, int video_len) | |||
1775 | 1771 | ||
1776 | par->video.pbase = pci_resource_start(par->pcidev, resource); | 1772 | par->video.pbase = pci_resource_start(par->pcidev, resource); |
1777 | par->video.len = video_len; | 1773 | par->video.len = video_len; |
1778 | par->video.vbase = ioremap(par->video.pbase, par->video.len); | 1774 | par->video.vbase = ioremap_wc(par->video.pbase, par->video.len); |
1779 | 1775 | ||
1780 | if (!par->video.vbase) { | 1776 | if (!par->video.vbase) { |
1781 | printk("savagefb: unable to map screen memory\n"); | 1777 | printk("savagefb: unable to map screen memory\n"); |
@@ -1787,11 +1783,7 @@ static int savage_map_video(struct fb_info *info, int video_len) | |||
1787 | info->fix.smem_start = par->video.pbase; | 1783 | info->fix.smem_start = par->video.pbase; |
1788 | info->fix.smem_len = par->video.len - par->cob_size; | 1784 | info->fix.smem_len = par->video.len - par->cob_size; |
1789 | info->screen_base = par->video.vbase; | 1785 | info->screen_base = par->video.vbase; |
1790 | 1786 | par->video.wc_cookie = arch_phys_wc_add(par->video.pbase, video_len); | |
1791 | #ifdef CONFIG_MTRR | ||
1792 | par->video.mtrr = mtrr_add(par->video.pbase, video_len, | ||
1793 | MTRR_TYPE_WRCOMB, 1); | ||
1794 | #endif | ||
1795 | 1787 | ||
1796 | /* Clear framebuffer, it's all white in memory after boot */ | 1788 | /* Clear framebuffer, it's all white in memory after boot */ |
1797 | memset_io(par->video.vbase, 0, par->video.len); | 1789 | memset_io(par->video.vbase, 0, par->video.len); |
@@ -1806,10 +1798,7 @@ static void savage_unmap_video(struct fb_info *info) | |||
1806 | DBG("savage_unmap_video"); | 1798 | DBG("savage_unmap_video"); |
1807 | 1799 | ||
1808 | if (par->video.vbase) { | 1800 | if (par->video.vbase) { |
1809 | #ifdef CONFIG_MTRR | 1801 | arch_phys_wc_del(par->video.wc_cookie); |
1810 | mtrr_del(par->video.mtrr, par->video.pbase, par->video.len); | ||
1811 | #endif | ||
1812 | |||
1813 | iounmap(par->video.vbase); | 1802 | iounmap(par->video.vbase); |
1814 | par->video.vbase = NULL; | 1803 | par->video.vbase = NULL; |
1815 | info->screen_base = NULL; | 1804 | info->screen_base = NULL; |
diff --git a/drivers/video/fbdev/sis/sis.h b/drivers/video/fbdev/sis/sis.h index 1987f1b7212f..ea1d1c9640bf 100644 --- a/drivers/video/fbdev/sis/sis.h +++ b/drivers/video/fbdev/sis/sis.h | |||
@@ -458,7 +458,7 @@ struct sis_video_info { | |||
458 | 458 | ||
459 | unsigned char *bios_abase; | 459 | unsigned char *bios_abase; |
460 | 460 | ||
461 | int mtrr; | 461 | int wc_cookie; |
462 | 462 | ||
463 | u32 sisfb_mem; | 463 | u32 sisfb_mem; |
464 | 464 | ||
diff --git a/drivers/video/fbdev/sis/sis_main.c b/drivers/video/fbdev/sis/sis_main.c index fcf610edf217..e92303823a4b 100644 --- a/drivers/video/fbdev/sis/sis_main.c +++ b/drivers/video/fbdev/sis/sis_main.c | |||
@@ -53,9 +53,6 @@ | |||
53 | #include <linux/types.h> | 53 | #include <linux/types.h> |
54 | #include <linux/uaccess.h> | 54 | #include <linux/uaccess.h> |
55 | #include <asm/io.h> | 55 | #include <asm/io.h> |
56 | #ifdef CONFIG_MTRR | ||
57 | #include <asm/mtrr.h> | ||
58 | #endif | ||
59 | 56 | ||
60 | #include "sis.h" | 57 | #include "sis.h" |
61 | #include "sis_main.h" | 58 | #include "sis_main.h" |
@@ -4130,13 +4127,13 @@ static void sisfb_post_map_vram(struct sis_video_info *ivideo, | |||
4130 | if (*mapsize < (min << 20)) | 4127 | if (*mapsize < (min << 20)) |
4131 | return; | 4128 | return; |
4132 | 4129 | ||
4133 | ivideo->video_vbase = ioremap(ivideo->video_base, (*mapsize)); | 4130 | ivideo->video_vbase = ioremap_wc(ivideo->video_base, (*mapsize)); |
4134 | 4131 | ||
4135 | if(!ivideo->video_vbase) { | 4132 | if(!ivideo->video_vbase) { |
4136 | printk(KERN_ERR | 4133 | printk(KERN_ERR |
4137 | "sisfb: Unable to map maximum video RAM for size detection\n"); | 4134 | "sisfb: Unable to map maximum video RAM for size detection\n"); |
4138 | (*mapsize) >>= 1; | 4135 | (*mapsize) >>= 1; |
4139 | while((!(ivideo->video_vbase = ioremap(ivideo->video_base, (*mapsize))))) { | 4136 | while((!(ivideo->video_vbase = ioremap_wc(ivideo->video_base, (*mapsize))))) { |
4140 | (*mapsize) >>= 1; | 4137 | (*mapsize) >>= 1; |
4141 | if((*mapsize) < (min << 20)) | 4138 | if((*mapsize) < (min << 20)) |
4142 | break; | 4139 | break; |
@@ -6186,7 +6183,7 @@ static int sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
6186 | goto error_2; | 6183 | goto error_2; |
6187 | } | 6184 | } |
6188 | 6185 | ||
6189 | ivideo->video_vbase = ioremap(ivideo->video_base, ivideo->video_size); | 6186 | ivideo->video_vbase = ioremap_wc(ivideo->video_base, ivideo->video_size); |
6190 | ivideo->SiS_Pr.VideoMemoryAddress = ivideo->video_vbase; | 6187 | ivideo->SiS_Pr.VideoMemoryAddress = ivideo->video_vbase; |
6191 | if(!ivideo->video_vbase) { | 6188 | if(!ivideo->video_vbase) { |
6192 | printk(KERN_ERR "sisfb: Fatal error: Unable to map framebuffer memory\n"); | 6189 | printk(KERN_ERR "sisfb: Fatal error: Unable to map framebuffer memory\n"); |
@@ -6254,8 +6251,6 @@ error_3: vfree(ivideo->bios_abase); | |||
6254 | ivideo->SiS_Pr.VideoMemoryAddress += ivideo->video_offset; | 6251 | ivideo->SiS_Pr.VideoMemoryAddress += ivideo->video_offset; |
6255 | ivideo->SiS_Pr.VideoMemorySize = ivideo->sisfb_mem; | 6252 | ivideo->SiS_Pr.VideoMemorySize = ivideo->sisfb_mem; |
6256 | 6253 | ||
6257 | ivideo->mtrr = -1; | ||
6258 | |||
6259 | ivideo->vbflags = 0; | 6254 | ivideo->vbflags = 0; |
6260 | ivideo->lcddefmodeidx = DEFAULT_LCDMODE; | 6255 | ivideo->lcddefmodeidx = DEFAULT_LCDMODE; |
6261 | ivideo->tvdefmodeidx = DEFAULT_TVMODE; | 6256 | ivideo->tvdefmodeidx = DEFAULT_TVMODE; |
@@ -6443,14 +6438,8 @@ error_3: vfree(ivideo->bios_abase); | |||
6443 | 6438 | ||
6444 | printk(KERN_DEBUG "sisfb: Initial vbflags 0x%x\n", (int)ivideo->vbflags); | 6439 | printk(KERN_DEBUG "sisfb: Initial vbflags 0x%x\n", (int)ivideo->vbflags); |
6445 | 6440 | ||
6446 | #ifdef CONFIG_MTRR | 6441 | ivideo->wc_cookie = arch_phys_wc_add(ivideo->video_base, |
6447 | ivideo->mtrr = mtrr_add(ivideo->video_base, ivideo->video_size, | 6442 | ivideo->video_size); |
6448 | MTRR_TYPE_WRCOMB, 1); | ||
6449 | if(ivideo->mtrr < 0) { | ||
6450 | printk(KERN_DEBUG "sisfb: Failed to add MTRRs\n"); | ||
6451 | } | ||
6452 | #endif | ||
6453 | |||
6454 | if(register_framebuffer(sis_fb_info) < 0) { | 6443 | if(register_framebuffer(sis_fb_info) < 0) { |
6455 | printk(KERN_ERR "sisfb: Fatal error: Failed to register framebuffer\n"); | 6444 | printk(KERN_ERR "sisfb: Fatal error: Failed to register framebuffer\n"); |
6456 | ret = -EINVAL; | 6445 | ret = -EINVAL; |
@@ -6507,11 +6496,7 @@ static void sisfb_remove(struct pci_dev *pdev) | |||
6507 | 6496 | ||
6508 | pci_dev_put(ivideo->nbridge); | 6497 | pci_dev_put(ivideo->nbridge); |
6509 | 6498 | ||
6510 | #ifdef CONFIG_MTRR | 6499 | arch_phys_wc_del(ivideo->wc_cookie); |
6511 | /* Release MTRR region */ | ||
6512 | if(ivideo->mtrr >= 0) | ||
6513 | mtrr_del(ivideo->mtrr, ivideo->video_base, ivideo->video_size); | ||
6514 | #endif | ||
6515 | 6500 | ||
6516 | /* If device was disabled when starting, disable | 6501 | /* If device was disabled when starting, disable |
6517 | * it when quitting. | 6502 | * it when quitting. |
diff --git a/drivers/video/fbdev/ssd1307fb.c b/drivers/video/fbdev/ssd1307fb.c index f7ed6d9016f7..3e153c06131a 100644 --- a/drivers/video/fbdev/ssd1307fb.c +++ b/drivers/video/fbdev/ssd1307fb.c | |||
@@ -7,6 +7,7 @@ | |||
7 | */ | 7 | */ |
8 | 8 | ||
9 | #include <linux/module.h> | 9 | #include <linux/module.h> |
10 | #include <linux/backlight.h> | ||
10 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
11 | #include <linux/i2c.h> | 12 | #include <linux/i2c.h> |
12 | #include <linux/fb.h> | 13 | #include <linux/fb.h> |
@@ -38,22 +39,43 @@ | |||
38 | #define SSD1307FB_SET_COM_PINS_CONFIG 0xda | 39 | #define SSD1307FB_SET_COM_PINS_CONFIG 0xda |
39 | #define SSD1307FB_SET_VCOMH 0xdb | 40 | #define SSD1307FB_SET_VCOMH 0xdb |
40 | 41 | ||
42 | #define MAX_CONTRAST 255 | ||
43 | |||
44 | #define REFRESHRATE 1 | ||
45 | |||
46 | static u_int refreshrate = REFRESHRATE; | ||
47 | module_param(refreshrate, uint, 0); | ||
48 | |||
41 | struct ssd1307fb_par; | 49 | struct ssd1307fb_par; |
42 | 50 | ||
43 | struct ssd1307fb_ops { | 51 | struct ssd1307fb_deviceinfo { |
44 | int (*init)(struct ssd1307fb_par *); | 52 | u32 default_vcomh; |
45 | int (*remove)(struct ssd1307fb_par *); | 53 | u32 default_dclk_div; |
54 | u32 default_dclk_frq; | ||
55 | int need_pwm; | ||
56 | int need_chargepump; | ||
46 | }; | 57 | }; |
47 | 58 | ||
48 | struct ssd1307fb_par { | 59 | struct ssd1307fb_par { |
60 | u32 com_invdir; | ||
61 | u32 com_lrremap; | ||
62 | u32 com_offset; | ||
63 | u32 com_seq; | ||
64 | u32 contrast; | ||
65 | u32 dclk_div; | ||
66 | u32 dclk_frq; | ||
67 | struct ssd1307fb_deviceinfo *device_info; | ||
49 | struct i2c_client *client; | 68 | struct i2c_client *client; |
50 | u32 height; | 69 | u32 height; |
51 | struct fb_info *info; | 70 | struct fb_info *info; |
52 | struct ssd1307fb_ops *ops; | ||
53 | u32 page_offset; | 71 | u32 page_offset; |
72 | u32 prechargep1; | ||
73 | u32 prechargep2; | ||
54 | struct pwm_device *pwm; | 74 | struct pwm_device *pwm; |
55 | u32 pwm_period; | 75 | u32 pwm_period; |
56 | int reset; | 76 | int reset; |
77 | u32 seg_remap; | ||
78 | u32 vcomh; | ||
57 | u32 width; | 79 | u32 width; |
58 | }; | 80 | }; |
59 | 81 | ||
@@ -213,6 +235,16 @@ static ssize_t ssd1307fb_write(struct fb_info *info, const char __user *buf, | |||
213 | return count; | 235 | return count; |
214 | } | 236 | } |
215 | 237 | ||
238 | static int ssd1307fb_blank(int blank_mode, struct fb_info *info) | ||
239 | { | ||
240 | struct ssd1307fb_par *par = info->par; | ||
241 | |||
242 | if (blank_mode != FB_BLANK_UNBLANK) | ||
243 | return ssd1307fb_write_cmd(par->client, SSD1307FB_DISPLAY_OFF); | ||
244 | else | ||
245 | return ssd1307fb_write_cmd(par->client, SSD1307FB_DISPLAY_ON); | ||
246 | } | ||
247 | |||
216 | static void ssd1307fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | 248 | static void ssd1307fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
217 | { | 249 | { |
218 | struct ssd1307fb_par *par = info->par; | 250 | struct ssd1307fb_par *par = info->par; |
@@ -238,6 +270,7 @@ static struct fb_ops ssd1307fb_ops = { | |||
238 | .owner = THIS_MODULE, | 270 | .owner = THIS_MODULE, |
239 | .fb_read = fb_sys_read, | 271 | .fb_read = fb_sys_read, |
240 | .fb_write = ssd1307fb_write, | 272 | .fb_write = ssd1307fb_write, |
273 | .fb_blank = ssd1307fb_blank, | ||
241 | .fb_fillrect = ssd1307fb_fillrect, | 274 | .fb_fillrect = ssd1307fb_fillrect, |
242 | .fb_copyarea = ssd1307fb_copyarea, | 275 | .fb_copyarea = ssd1307fb_copyarea, |
243 | .fb_imageblit = ssd1307fb_imageblit, | 276 | .fb_imageblit = ssd1307fb_imageblit, |
@@ -249,74 +282,46 @@ static void ssd1307fb_deferred_io(struct fb_info *info, | |||
249 | ssd1307fb_update_display(info->par); | 282 | ssd1307fb_update_display(info->par); |
250 | } | 283 | } |
251 | 284 | ||
252 | static struct fb_deferred_io ssd1307fb_defio = { | 285 | static int ssd1307fb_init(struct ssd1307fb_par *par) |
253 | .delay = HZ, | ||
254 | .deferred_io = ssd1307fb_deferred_io, | ||
255 | }; | ||
256 | |||
257 | static int ssd1307fb_ssd1307_init(struct ssd1307fb_par *par) | ||
258 | { | 286 | { |
259 | int ret; | 287 | int ret; |
288 | u32 precharge, dclk, com_invdir, compins; | ||
260 | 289 | ||
261 | par->pwm = pwm_get(&par->client->dev, NULL); | 290 | if (par->device_info->need_pwm) { |
262 | if (IS_ERR(par->pwm)) { | 291 | par->pwm = pwm_get(&par->client->dev, NULL); |
263 | dev_err(&par->client->dev, "Could not get PWM from device tree!\n"); | 292 | if (IS_ERR(par->pwm)) { |
264 | return PTR_ERR(par->pwm); | 293 | dev_err(&par->client->dev, "Could not get PWM from device tree!\n"); |
265 | } | 294 | return PTR_ERR(par->pwm); |
266 | 295 | } | |
267 | par->pwm_period = pwm_get_period(par->pwm); | ||
268 | /* Enable the PWM */ | ||
269 | pwm_config(par->pwm, par->pwm_period / 2, par->pwm_period); | ||
270 | pwm_enable(par->pwm); | ||
271 | |||
272 | dev_dbg(&par->client->dev, "Using PWM%d with a %dns period.\n", | ||
273 | par->pwm->pwm, par->pwm_period); | ||
274 | |||
275 | /* Map column 127 of the OLED to segment 0 */ | ||
276 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SEG_REMAP_ON); | ||
277 | if (ret < 0) | ||
278 | return ret; | ||
279 | |||
280 | /* Turn on the display */ | ||
281 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_DISPLAY_ON); | ||
282 | if (ret < 0) | ||
283 | return ret; | ||
284 | |||
285 | return 0; | ||
286 | } | ||
287 | |||
288 | static int ssd1307fb_ssd1307_remove(struct ssd1307fb_par *par) | ||
289 | { | ||
290 | pwm_disable(par->pwm); | ||
291 | pwm_put(par->pwm); | ||
292 | return 0; | ||
293 | } | ||
294 | 296 | ||
295 | static struct ssd1307fb_ops ssd1307fb_ssd1307_ops = { | 297 | par->pwm_period = pwm_get_period(par->pwm); |
296 | .init = ssd1307fb_ssd1307_init, | 298 | /* Enable the PWM */ |
297 | .remove = ssd1307fb_ssd1307_remove, | 299 | pwm_config(par->pwm, par->pwm_period / 2, par->pwm_period); |
298 | }; | 300 | pwm_enable(par->pwm); |
299 | 301 | ||
300 | static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | 302 | dev_dbg(&par->client->dev, "Using PWM%d with a %dns period.\n", |
301 | { | 303 | par->pwm->pwm, par->pwm_period); |
302 | int ret; | 304 | }; |
303 | 305 | ||
304 | /* Set initial contrast */ | 306 | /* Set initial contrast */ |
305 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_CONTRAST); | 307 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_CONTRAST); |
306 | if (ret < 0) | 308 | if (ret < 0) |
307 | return ret; | 309 | return ret; |
308 | 310 | ||
309 | ret = ssd1307fb_write_cmd(par->client, 0x7f); | 311 | ret = ssd1307fb_write_cmd(par->client, par->contrast); |
310 | if (ret < 0) | ||
311 | return ret; | ||
312 | |||
313 | /* Set COM direction */ | ||
314 | ret = ssd1307fb_write_cmd(par->client, 0xc8); | ||
315 | if (ret < 0) | 312 | if (ret < 0) |
316 | return ret; | 313 | return ret; |
317 | 314 | ||
318 | /* Set segment re-map */ | 315 | /* Set segment re-map */ |
319 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SEG_REMAP_ON); | 316 | if (par->seg_remap) { |
317 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SEG_REMAP_ON); | ||
318 | if (ret < 0) | ||
319 | return ret; | ||
320 | }; | ||
321 | |||
322 | /* Set COM direction */ | ||
323 | com_invdir = 0xc0 | (par->com_invdir & 0x1) << 3; | ||
324 | ret = ssd1307fb_write_cmd(par->client, com_invdir); | ||
320 | if (ret < 0) | 325 | if (ret < 0) |
321 | return ret; | 326 | return ret; |
322 | 327 | ||
@@ -334,7 +339,7 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | |||
334 | if (ret < 0) | 339 | if (ret < 0) |
335 | return ret; | 340 | return ret; |
336 | 341 | ||
337 | ret = ssd1307fb_write_cmd(par->client, 0x20); | 342 | ret = ssd1307fb_write_cmd(par->client, par->com_offset); |
338 | if (ret < 0) | 343 | if (ret < 0) |
339 | return ret; | 344 | return ret; |
340 | 345 | ||
@@ -343,7 +348,8 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | |||
343 | if (ret < 0) | 348 | if (ret < 0) |
344 | return ret; | 349 | return ret; |
345 | 350 | ||
346 | ret = ssd1307fb_write_cmd(par->client, 0xf0); | 351 | dclk = ((par->dclk_div - 1) & 0xf) | (par->dclk_frq & 0xf) << 4; |
352 | ret = ssd1307fb_write_cmd(par->client, dclk); | ||
347 | if (ret < 0) | 353 | if (ret < 0) |
348 | return ret; | 354 | return ret; |
349 | 355 | ||
@@ -352,7 +358,8 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | |||
352 | if (ret < 0) | 358 | if (ret < 0) |
353 | return ret; | 359 | return ret; |
354 | 360 | ||
355 | ret = ssd1307fb_write_cmd(par->client, 0x22); | 361 | precharge = (par->prechargep1 & 0xf) | (par->prechargep2 & 0xf) << 4; |
362 | ret = ssd1307fb_write_cmd(par->client, precharge); | ||
356 | if (ret < 0) | 363 | if (ret < 0) |
357 | return ret; | 364 | return ret; |
358 | 365 | ||
@@ -361,7 +368,9 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | |||
361 | if (ret < 0) | 368 | if (ret < 0) |
362 | return ret; | 369 | return ret; |
363 | 370 | ||
364 | ret = ssd1307fb_write_cmd(par->client, 0x22); | 371 | compins = 0x02 | !(par->com_seq & 0x1) << 4 |
372 | | (par->com_lrremap & 0x1) << 5; | ||
373 | ret = ssd1307fb_write_cmd(par->client, compins); | ||
365 | if (ret < 0) | 374 | if (ret < 0) |
366 | return ret; | 375 | return ret; |
367 | 376 | ||
@@ -370,7 +379,7 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | |||
370 | if (ret < 0) | 379 | if (ret < 0) |
371 | return ret; | 380 | return ret; |
372 | 381 | ||
373 | ret = ssd1307fb_write_cmd(par->client, 0x49); | 382 | ret = ssd1307fb_write_cmd(par->client, par->vcomh); |
374 | if (ret < 0) | 383 | if (ret < 0) |
375 | return ret; | 384 | return ret; |
376 | 385 | ||
@@ -379,7 +388,8 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | |||
379 | if (ret < 0) | 388 | if (ret < 0) |
380 | return ret; | 389 | return ret; |
381 | 390 | ||
382 | ret = ssd1307fb_write_cmd(par->client, 0x14); | 391 | ret = ssd1307fb_write_cmd(par->client, |
392 | (par->device_info->need_chargepump & 0x1 << 2) & 0x14); | ||
383 | if (ret < 0) | 393 | if (ret < 0) |
384 | return ret; | 394 | return ret; |
385 | 395 | ||
@@ -393,6 +403,7 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | |||
393 | if (ret < 0) | 403 | if (ret < 0) |
394 | return ret; | 404 | return ret; |
395 | 405 | ||
406 | /* Set column range */ | ||
396 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_COL_RANGE); | 407 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_COL_RANGE); |
397 | if (ret < 0) | 408 | if (ret < 0) |
398 | return ret; | 409 | return ret; |
@@ -405,6 +416,7 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | |||
405 | if (ret < 0) | 416 | if (ret < 0) |
406 | return ret; | 417 | return ret; |
407 | 418 | ||
419 | /* Set page range */ | ||
408 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_PAGE_RANGE); | 420 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_PAGE_RANGE); |
409 | if (ret < 0) | 421 | if (ret < 0) |
410 | return ret; | 422 | return ret; |
@@ -426,18 +438,75 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) | |||
426 | return 0; | 438 | return 0; |
427 | } | 439 | } |
428 | 440 | ||
429 | static struct ssd1307fb_ops ssd1307fb_ssd1306_ops = { | 441 | static int ssd1307fb_update_bl(struct backlight_device *bdev) |
430 | .init = ssd1307fb_ssd1306_init, | 442 | { |
443 | struct ssd1307fb_par *par = bl_get_data(bdev); | ||
444 | int ret; | ||
445 | int brightness = bdev->props.brightness; | ||
446 | |||
447 | par->contrast = brightness; | ||
448 | |||
449 | ret = ssd1307fb_write_cmd(par->client, SSD1307FB_CONTRAST); | ||
450 | if (ret < 0) | ||
451 | return ret; | ||
452 | ret = ssd1307fb_write_cmd(par->client, par->contrast); | ||
453 | if (ret < 0) | ||
454 | return ret; | ||
455 | return 0; | ||
456 | } | ||
457 | |||
458 | static int ssd1307fb_get_brightness(struct backlight_device *bdev) | ||
459 | { | ||
460 | struct ssd1307fb_par *par = bl_get_data(bdev); | ||
461 | |||
462 | return par->contrast; | ||
463 | } | ||
464 | |||
465 | static int ssd1307fb_check_fb(struct backlight_device *bdev, | ||
466 | struct fb_info *info) | ||
467 | { | ||
468 | return (info->bl_dev == bdev); | ||
469 | } | ||
470 | |||
471 | static const struct backlight_ops ssd1307fb_bl_ops = { | ||
472 | .options = BL_CORE_SUSPENDRESUME, | ||
473 | .update_status = ssd1307fb_update_bl, | ||
474 | .get_brightness = ssd1307fb_get_brightness, | ||
475 | .check_fb = ssd1307fb_check_fb, | ||
476 | }; | ||
477 | |||
478 | static struct ssd1307fb_deviceinfo ssd1307fb_ssd1305_deviceinfo = { | ||
479 | .default_vcomh = 0x34, | ||
480 | .default_dclk_div = 1, | ||
481 | .default_dclk_frq = 7, | ||
482 | }; | ||
483 | |||
484 | static struct ssd1307fb_deviceinfo ssd1307fb_ssd1306_deviceinfo = { | ||
485 | .default_vcomh = 0x20, | ||
486 | .default_dclk_div = 1, | ||
487 | .default_dclk_frq = 8, | ||
488 | .need_chargepump = 1, | ||
489 | }; | ||
490 | |||
491 | static struct ssd1307fb_deviceinfo ssd1307fb_ssd1307_deviceinfo = { | ||
492 | .default_vcomh = 0x20, | ||
493 | .default_dclk_div = 2, | ||
494 | .default_dclk_frq = 12, | ||
495 | .need_pwm = 1, | ||
431 | }; | 496 | }; |
432 | 497 | ||
433 | static const struct of_device_id ssd1307fb_of_match[] = { | 498 | static const struct of_device_id ssd1307fb_of_match[] = { |
434 | { | 499 | { |
500 | .compatible = "solomon,ssd1305fb-i2c", | ||
501 | .data = (void *)&ssd1307fb_ssd1305_deviceinfo, | ||
502 | }, | ||
503 | { | ||
435 | .compatible = "solomon,ssd1306fb-i2c", | 504 | .compatible = "solomon,ssd1306fb-i2c", |
436 | .data = (void *)&ssd1307fb_ssd1306_ops, | 505 | .data = (void *)&ssd1307fb_ssd1306_deviceinfo, |
437 | }, | 506 | }, |
438 | { | 507 | { |
439 | .compatible = "solomon,ssd1307fb-i2c", | 508 | .compatible = "solomon,ssd1307fb-i2c", |
440 | .data = (void *)&ssd1307fb_ssd1307_ops, | 509 | .data = (void *)&ssd1307fb_ssd1307_deviceinfo, |
441 | }, | 510 | }, |
442 | {}, | 511 | {}, |
443 | }; | 512 | }; |
@@ -446,8 +515,11 @@ MODULE_DEVICE_TABLE(of, ssd1307fb_of_match); | |||
446 | static int ssd1307fb_probe(struct i2c_client *client, | 515 | static int ssd1307fb_probe(struct i2c_client *client, |
447 | const struct i2c_device_id *id) | 516 | const struct i2c_device_id *id) |
448 | { | 517 | { |
518 | struct backlight_device *bl; | ||
519 | char bl_name[12]; | ||
449 | struct fb_info *info; | 520 | struct fb_info *info; |
450 | struct device_node *node = client->dev.of_node; | 521 | struct device_node *node = client->dev.of_node; |
522 | struct fb_deferred_io *ssd1307fb_defio; | ||
451 | u32 vmem_size; | 523 | u32 vmem_size; |
452 | struct ssd1307fb_par *par; | 524 | struct ssd1307fb_par *par; |
453 | u8 *vmem; | 525 | u8 *vmem; |
@@ -468,8 +540,8 @@ static int ssd1307fb_probe(struct i2c_client *client, | |||
468 | par->info = info; | 540 | par->info = info; |
469 | par->client = client; | 541 | par->client = client; |
470 | 542 | ||
471 | par->ops = (struct ssd1307fb_ops *)of_match_device(ssd1307fb_of_match, | 543 | par->device_info = (struct ssd1307fb_deviceinfo *)of_match_device( |
472 | &client->dev)->data; | 544 | ssd1307fb_of_match, &client->dev)->data; |
473 | 545 | ||
474 | par->reset = of_get_named_gpio(client->dev.of_node, | 546 | par->reset = of_get_named_gpio(client->dev.of_node, |
475 | "reset-gpios", 0); | 547 | "reset-gpios", 0); |
@@ -487,19 +559,51 @@ static int ssd1307fb_probe(struct i2c_client *client, | |||
487 | if (of_property_read_u32(node, "solomon,page-offset", &par->page_offset)) | 559 | if (of_property_read_u32(node, "solomon,page-offset", &par->page_offset)) |
488 | par->page_offset = 1; | 560 | par->page_offset = 1; |
489 | 561 | ||
562 | if (of_property_read_u32(node, "solomon,com-offset", &par->com_offset)) | ||
563 | par->com_offset = 0; | ||
564 | |||
565 | if (of_property_read_u32(node, "solomon,prechargep1", &par->prechargep1)) | ||
566 | par->prechargep1 = 2; | ||
567 | |||
568 | if (of_property_read_u32(node, "solomon,prechargep2", &par->prechargep2)) | ||
569 | par->prechargep2 = 2; | ||
570 | |||
571 | par->seg_remap = !of_property_read_bool(node, "solomon,segment-no-remap"); | ||
572 | par->com_seq = of_property_read_bool(node, "solomon,com-seq"); | ||
573 | par->com_lrremap = of_property_read_bool(node, "solomon,com-lrremap"); | ||
574 | par->com_invdir = of_property_read_bool(node, "solomon,com-invdir"); | ||
575 | |||
576 | par->contrast = 127; | ||
577 | par->vcomh = par->device_info->default_vcomh; | ||
578 | |||
579 | /* Setup display timing */ | ||
580 | par->dclk_div = par->device_info->default_dclk_div; | ||
581 | par->dclk_frq = par->device_info->default_dclk_frq; | ||
582 | |||
490 | vmem_size = par->width * par->height / 8; | 583 | vmem_size = par->width * par->height / 8; |
491 | 584 | ||
492 | vmem = devm_kzalloc(&client->dev, vmem_size, GFP_KERNEL); | 585 | vmem = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
586 | get_order(vmem_size)); | ||
493 | if (!vmem) { | 587 | if (!vmem) { |
494 | dev_err(&client->dev, "Couldn't allocate graphical memory.\n"); | 588 | dev_err(&client->dev, "Couldn't allocate graphical memory.\n"); |
495 | ret = -ENOMEM; | 589 | ret = -ENOMEM; |
496 | goto fb_alloc_error; | 590 | goto fb_alloc_error; |
497 | } | 591 | } |
498 | 592 | ||
593 | ssd1307fb_defio = devm_kzalloc(&client->dev, sizeof(struct fb_deferred_io), GFP_KERNEL); | ||
594 | if (!ssd1307fb_defio) { | ||
595 | dev_err(&client->dev, "Couldn't allocate deferred io.\n"); | ||
596 | ret = -ENOMEM; | ||
597 | goto fb_alloc_error; | ||
598 | } | ||
599 | |||
600 | ssd1307fb_defio->delay = HZ / refreshrate; | ||
601 | ssd1307fb_defio->deferred_io = ssd1307fb_deferred_io; | ||
602 | |||
499 | info->fbops = &ssd1307fb_ops; | 603 | info->fbops = &ssd1307fb_ops; |
500 | info->fix = ssd1307fb_fix; | 604 | info->fix = ssd1307fb_fix; |
501 | info->fix.line_length = par->width / 8; | 605 | info->fix.line_length = par->width / 8; |
502 | info->fbdefio = &ssd1307fb_defio; | 606 | info->fbdefio = ssd1307fb_defio; |
503 | 607 | ||
504 | info->var = ssd1307fb_var; | 608 | info->var = ssd1307fb_var; |
505 | info->var.xres = par->width; | 609 | info->var.xres = par->width; |
@@ -515,7 +619,7 @@ static int ssd1307fb_probe(struct i2c_client *client, | |||
515 | info->var.blue.offset = 0; | 619 | info->var.blue.offset = 0; |
516 | 620 | ||
517 | info->screen_base = (u8 __force __iomem *)vmem; | 621 | info->screen_base = (u8 __force __iomem *)vmem; |
518 | info->fix.smem_start = (unsigned long)vmem; | 622 | info->fix.smem_start = __pa(vmem); |
519 | info->fix.smem_len = vmem_size; | 623 | info->fix.smem_len = vmem_size; |
520 | 624 | ||
521 | fb_deferred_io_init(info); | 625 | fb_deferred_io_init(info); |
@@ -538,11 +642,9 @@ static int ssd1307fb_probe(struct i2c_client *client, | |||
538 | gpio_set_value(par->reset, 1); | 642 | gpio_set_value(par->reset, 1); |
539 | udelay(4); | 643 | udelay(4); |
540 | 644 | ||
541 | if (par->ops->init) { | 645 | ret = ssd1307fb_init(par); |
542 | ret = par->ops->init(par); | 646 | if (ret) |
543 | if (ret) | 647 | goto reset_oled_error; |
544 | goto reset_oled_error; | ||
545 | } | ||
546 | 648 | ||
547 | ret = register_framebuffer(info); | 649 | ret = register_framebuffer(info); |
548 | if (ret) { | 650 | if (ret) { |
@@ -550,13 +652,30 @@ static int ssd1307fb_probe(struct i2c_client *client, | |||
550 | goto panel_init_error; | 652 | goto panel_init_error; |
551 | } | 653 | } |
552 | 654 | ||
655 | snprintf(bl_name, sizeof(bl_name), "ssd1307fb%d", info->node); | ||
656 | bl = backlight_device_register(bl_name, &client->dev, par, | ||
657 | &ssd1307fb_bl_ops, NULL); | ||
658 | if (IS_ERR(bl)) { | ||
659 | dev_err(&client->dev, "unable to register backlight device: %ld\n", | ||
660 | PTR_ERR(bl)); | ||
661 | goto bl_init_error; | ||
662 | } | ||
663 | |||
664 | bl->props.brightness = par->contrast; | ||
665 | bl->props.max_brightness = MAX_CONTRAST; | ||
666 | info->bl_dev = bl; | ||
667 | |||
553 | dev_info(&client->dev, "fb%d: %s framebuffer device registered, using %d bytes of video memory\n", info->node, info->fix.id, vmem_size); | 668 | dev_info(&client->dev, "fb%d: %s framebuffer device registered, using %d bytes of video memory\n", info->node, info->fix.id, vmem_size); |
554 | 669 | ||
555 | return 0; | 670 | return 0; |
556 | 671 | ||
672 | bl_init_error: | ||
673 | unregister_framebuffer(info); | ||
557 | panel_init_error: | 674 | panel_init_error: |
558 | if (par->ops->remove) | 675 | if (par->device_info->need_pwm) { |
559 | par->ops->remove(par); | 676 | pwm_disable(par->pwm); |
677 | pwm_put(par->pwm); | ||
678 | }; | ||
560 | reset_oled_error: | 679 | reset_oled_error: |
561 | fb_deferred_io_cleanup(info); | 680 | fb_deferred_io_cleanup(info); |
562 | fb_alloc_error: | 681 | fb_alloc_error: |
@@ -569,16 +688,24 @@ static int ssd1307fb_remove(struct i2c_client *client) | |||
569 | struct fb_info *info = i2c_get_clientdata(client); | 688 | struct fb_info *info = i2c_get_clientdata(client); |
570 | struct ssd1307fb_par *par = info->par; | 689 | struct ssd1307fb_par *par = info->par; |
571 | 690 | ||
691 | ssd1307fb_write_cmd(par->client, SSD1307FB_DISPLAY_OFF); | ||
692 | |||
693 | backlight_device_unregister(info->bl_dev); | ||
694 | |||
572 | unregister_framebuffer(info); | 695 | unregister_framebuffer(info); |
573 | if (par->ops->remove) | 696 | if (par->device_info->need_pwm) { |
574 | par->ops->remove(par); | 697 | pwm_disable(par->pwm); |
698 | pwm_put(par->pwm); | ||
699 | }; | ||
575 | fb_deferred_io_cleanup(info); | 700 | fb_deferred_io_cleanup(info); |
701 | __free_pages(__va(info->fix.smem_start), get_order(info->fix.smem_len)); | ||
576 | framebuffer_release(info); | 702 | framebuffer_release(info); |
577 | 703 | ||
578 | return 0; | 704 | return 0; |
579 | } | 705 | } |
580 | 706 | ||
581 | static const struct i2c_device_id ssd1307fb_i2c_id[] = { | 707 | static const struct i2c_device_id ssd1307fb_i2c_id[] = { |
708 | { "ssd1305fb", 0 }, | ||
582 | { "ssd1306fb", 0 }, | 709 | { "ssd1306fb", 0 }, |
583 | { "ssd1307fb", 0 }, | 710 | { "ssd1307fb", 0 }, |
584 | { } | 711 | { } |
diff --git a/drivers/video/fbdev/tdfxfb.c b/drivers/video/fbdev/tdfxfb.c index f761fe375f5b..621fa441a6db 100644 --- a/drivers/video/fbdev/tdfxfb.c +++ b/drivers/video/fbdev/tdfxfb.c | |||
@@ -78,24 +78,6 @@ | |||
78 | 78 | ||
79 | #define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b) | 79 | #define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b) |
80 | 80 | ||
81 | #ifdef CONFIG_MTRR | ||
82 | #include <asm/mtrr.h> | ||
83 | #else | ||
84 | /* duplicate asm/mtrr.h defines to work on archs without mtrr */ | ||
85 | #define MTRR_TYPE_WRCOMB 1 | ||
86 | |||
87 | static inline int mtrr_add(unsigned long base, unsigned long size, | ||
88 | unsigned int type, char increment) | ||
89 | { | ||
90 | return -ENODEV; | ||
91 | } | ||
92 | static inline int mtrr_del(int reg, unsigned long base, | ||
93 | unsigned long size) | ||
94 | { | ||
95 | return -ENODEV; | ||
96 | } | ||
97 | #endif | ||
98 | |||
99 | #define BANSHEE_MAX_PIXCLOCK 270000 | 81 | #define BANSHEE_MAX_PIXCLOCK 270000 |
100 | #define VOODOO3_MAX_PIXCLOCK 300000 | 82 | #define VOODOO3_MAX_PIXCLOCK 300000 |
101 | #define VOODOO5_MAX_PIXCLOCK 350000 | 83 | #define VOODOO5_MAX_PIXCLOCK 350000 |
@@ -167,7 +149,6 @@ static int nopan; | |||
167 | static int nowrap = 1; /* not implemented (yet) */ | 149 | static int nowrap = 1; /* not implemented (yet) */ |
168 | static int hwcursor = 1; | 150 | static int hwcursor = 1; |
169 | static char *mode_option; | 151 | static char *mode_option; |
170 | /* mtrr option */ | ||
171 | static bool nomtrr; | 152 | static bool nomtrr; |
172 | 153 | ||
173 | /* ------------------------------------------------------------------------- | 154 | /* ------------------------------------------------------------------------- |
@@ -1454,8 +1435,8 @@ static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1454 | goto out_err_regbase; | 1435 | goto out_err_regbase; |
1455 | } | 1436 | } |
1456 | 1437 | ||
1457 | info->screen_base = ioremap_nocache(info->fix.smem_start, | 1438 | info->screen_base = ioremap_wc(info->fix.smem_start, |
1458 | info->fix.smem_len); | 1439 | info->fix.smem_len); |
1459 | if (!info->screen_base) { | 1440 | if (!info->screen_base) { |
1460 | printk(KERN_ERR "fb: Can't remap %s framebuffer.\n", | 1441 | printk(KERN_ERR "fb: Can't remap %s framebuffer.\n", |
1461 | info->fix.id); | 1442 | info->fix.id); |
@@ -1473,11 +1454,9 @@ static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1473 | printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id, | 1454 | printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id, |
1474 | info->fix.smem_len >> 10); | 1455 | info->fix.smem_len >> 10); |
1475 | 1456 | ||
1476 | default_par->mtrr_handle = -1; | ||
1477 | if (!nomtrr) | 1457 | if (!nomtrr) |
1478 | default_par->mtrr_handle = | 1458 | default_par->wc_cookie= arch_phys_wc_add(info->fix.smem_start, |
1479 | mtrr_add(info->fix.smem_start, info->fix.smem_len, | 1459 | info->fix.smem_len); |
1480 | MTRR_TYPE_WRCOMB, 1); | ||
1481 | 1460 | ||
1482 | info->fix.ypanstep = nopan ? 0 : 1; | 1461 | info->fix.ypanstep = nopan ? 0 : 1; |
1483 | info->fix.ywrapstep = nowrap ? 0 : 1; | 1462 | info->fix.ywrapstep = nowrap ? 0 : 1; |
@@ -1566,9 +1545,7 @@ out_err_iobase: | |||
1566 | #ifdef CONFIG_FB_3DFX_I2C | 1545 | #ifdef CONFIG_FB_3DFX_I2C |
1567 | tdfxfb_delete_i2c_busses(default_par); | 1546 | tdfxfb_delete_i2c_busses(default_par); |
1568 | #endif | 1547 | #endif |
1569 | if (default_par->mtrr_handle >= 0) | 1548 | arch_phys_wc_del(default_par->wc_cookie); |
1570 | mtrr_del(default_par->mtrr_handle, info->fix.smem_start, | ||
1571 | info->fix.smem_len); | ||
1572 | release_region(pci_resource_start(pdev, 2), | 1549 | release_region(pci_resource_start(pdev, 2), |
1573 | pci_resource_len(pdev, 2)); | 1550 | pci_resource_len(pdev, 2)); |
1574 | out_err_screenbase: | 1551 | out_err_screenbase: |
@@ -1604,10 +1581,8 @@ static void __init tdfxfb_setup(char *options) | |||
1604 | nowrap = 1; | 1581 | nowrap = 1; |
1605 | } else if (!strncmp(this_opt, "hwcursor=", 9)) { | 1582 | } else if (!strncmp(this_opt, "hwcursor=", 9)) { |
1606 | hwcursor = simple_strtoul(this_opt + 9, NULL, 0); | 1583 | hwcursor = simple_strtoul(this_opt + 9, NULL, 0); |
1607 | #ifdef CONFIG_MTRR | ||
1608 | } else if (!strncmp(this_opt, "nomtrr", 6)) { | 1584 | } else if (!strncmp(this_opt, "nomtrr", 6)) { |
1609 | nomtrr = 1; | 1585 | nomtrr = 1; |
1610 | #endif | ||
1611 | } else { | 1586 | } else { |
1612 | mode_option = this_opt; | 1587 | mode_option = this_opt; |
1613 | } | 1588 | } |
@@ -1633,9 +1608,7 @@ static void tdfxfb_remove(struct pci_dev *pdev) | |||
1633 | #ifdef CONFIG_FB_3DFX_I2C | 1608 | #ifdef CONFIG_FB_3DFX_I2C |
1634 | tdfxfb_delete_i2c_busses(par); | 1609 | tdfxfb_delete_i2c_busses(par); |
1635 | #endif | 1610 | #endif |
1636 | if (par->mtrr_handle >= 0) | 1611 | arch_phys_wc_del(par->wc_cookie); |
1637 | mtrr_del(par->mtrr_handle, info->fix.smem_start, | ||
1638 | info->fix.smem_len); | ||
1639 | iounmap(par->regbase_virt); | 1612 | iounmap(par->regbase_virt); |
1640 | iounmap(info->screen_base); | 1613 | iounmap(info->screen_base); |
1641 | 1614 | ||
@@ -1677,10 +1650,8 @@ MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " | |||
1677 | "(1=enable, 0=disable, default=1)"); | 1650 | "(1=enable, 0=disable, default=1)"); |
1678 | module_param(mode_option, charp, 0); | 1651 | module_param(mode_option, charp, 0); |
1679 | MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); | 1652 | MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); |
1680 | #ifdef CONFIG_MTRR | ||
1681 | module_param(nomtrr, bool, 0); | 1653 | module_param(nomtrr, bool, 0); |
1682 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)"); | 1654 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)"); |
1683 | #endif | ||
1684 | 1655 | ||
1685 | module_init(tdfxfb_init); | 1656 | module_init(tdfxfb_init); |
1686 | module_exit(tdfxfb_exit); | 1657 | module_exit(tdfxfb_exit); |
diff --git a/drivers/video/fbdev/vesafb.c b/drivers/video/fbdev/vesafb.c index d79a0ac49fc7..528fe917dd49 100644 --- a/drivers/video/fbdev/vesafb.c +++ b/drivers/video/fbdev/vesafb.c | |||
@@ -19,16 +19,20 @@ | |||
19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/screen_info.h> | 21 | #include <linux/screen_info.h> |
22 | #include <linux/io.h> | ||
22 | 23 | ||
23 | #include <video/vga.h> | 24 | #include <video/vga.h> |
24 | #include <asm/io.h> | ||
25 | #include <asm/mtrr.h> | ||
26 | 25 | ||
27 | #define dac_reg (0x3c8) | 26 | #define dac_reg (0x3c8) |
28 | #define dac_val (0x3c9) | 27 | #define dac_val (0x3c9) |
29 | 28 | ||
30 | /* --------------------------------------------------------------------- */ | 29 | /* --------------------------------------------------------------------- */ |
31 | 30 | ||
31 | struct vesafb_par { | ||
32 | u32 pseudo_palette[256]; | ||
33 | int wc_cookie; | ||
34 | }; | ||
35 | |||
32 | static struct fb_var_screeninfo vesafb_defined = { | 36 | static struct fb_var_screeninfo vesafb_defined = { |
33 | .activate = FB_ACTIVATE_NOW, | 37 | .activate = FB_ACTIVATE_NOW, |
34 | .height = -1, | 38 | .height = -1, |
@@ -175,7 +179,10 @@ static int vesafb_setcolreg(unsigned regno, unsigned red, unsigned green, | |||
175 | 179 | ||
176 | static void vesafb_destroy(struct fb_info *info) | 180 | static void vesafb_destroy(struct fb_info *info) |
177 | { | 181 | { |
182 | struct vesafb_par *par = info->par; | ||
183 | |||
178 | fb_dealloc_cmap(&info->cmap); | 184 | fb_dealloc_cmap(&info->cmap); |
185 | arch_phys_wc_del(par->wc_cookie); | ||
179 | if (info->screen_base) | 186 | if (info->screen_base) |
180 | iounmap(info->screen_base); | 187 | iounmap(info->screen_base); |
181 | release_mem_region(info->apertures->ranges[0].base, info->apertures->ranges[0].size); | 188 | release_mem_region(info->apertures->ranges[0].base, info->apertures->ranges[0].size); |
@@ -228,6 +235,7 @@ static int vesafb_setup(char *options) | |||
228 | static int vesafb_probe(struct platform_device *dev) | 235 | static int vesafb_probe(struct platform_device *dev) |
229 | { | 236 | { |
230 | struct fb_info *info; | 237 | struct fb_info *info; |
238 | struct vesafb_par *par; | ||
231 | int i, err; | 239 | int i, err; |
232 | unsigned int size_vmode; | 240 | unsigned int size_vmode; |
233 | unsigned int size_remap; | 241 | unsigned int size_remap; |
@@ -291,14 +299,14 @@ static int vesafb_probe(struct platform_device *dev) | |||
291 | spaces our resource handlers simply don't know about */ | 299 | spaces our resource handlers simply don't know about */ |
292 | } | 300 | } |
293 | 301 | ||
294 | info = framebuffer_alloc(sizeof(u32) * 256, &dev->dev); | 302 | info = framebuffer_alloc(sizeof(struct vesafb_par), &dev->dev); |
295 | if (!info) { | 303 | if (!info) { |
296 | release_mem_region(vesafb_fix.smem_start, size_total); | 304 | release_mem_region(vesafb_fix.smem_start, size_total); |
297 | return -ENOMEM; | 305 | return -ENOMEM; |
298 | } | 306 | } |
299 | platform_set_drvdata(dev, info); | 307 | platform_set_drvdata(dev, info); |
300 | info->pseudo_palette = info->par; | 308 | par = info->par; |
301 | info->par = NULL; | 309 | info->pseudo_palette = par->pseudo_palette; |
302 | 310 | ||
303 | /* set vesafb aperture size for generic probing */ | 311 | /* set vesafb aperture size for generic probing */ |
304 | info->apertures = alloc_apertures(1); | 312 | info->apertures = alloc_apertures(1); |
@@ -404,60 +412,27 @@ static int vesafb_probe(struct platform_device *dev) | |||
404 | * region already (FIXME) */ | 412 | * region already (FIXME) */ |
405 | request_region(0x3c0, 32, "vesafb"); | 413 | request_region(0x3c0, 32, "vesafb"); |
406 | 414 | ||
407 | #ifdef CONFIG_MTRR | 415 | if (mtrr == 3) { |
408 | if (mtrr) { | ||
409 | unsigned int temp_size = size_total; | 416 | unsigned int temp_size = size_total; |
410 | unsigned int type = 0; | ||
411 | |||
412 | switch (mtrr) { | ||
413 | case 1: | ||
414 | type = MTRR_TYPE_UNCACHABLE; | ||
415 | break; | ||
416 | case 2: | ||
417 | type = MTRR_TYPE_WRBACK; | ||
418 | break; | ||
419 | case 3: | ||
420 | type = MTRR_TYPE_WRCOMB; | ||
421 | break; | ||
422 | case 4: | ||
423 | type = MTRR_TYPE_WRTHROUGH; | ||
424 | break; | ||
425 | default: | ||
426 | type = 0; | ||
427 | break; | ||
428 | } | ||
429 | 417 | ||
430 | if (type) { | 418 | /* Find the largest power-of-two */ |
431 | int rc; | 419 | temp_size = roundup_pow_of_two(temp_size); |
432 | 420 | ||
433 | /* Find the largest power-of-two */ | 421 | /* Try and find a power of two to add */ |
434 | temp_size = roundup_pow_of_two(temp_size); | 422 | do { |
423 | par->wc_cookie = | ||
424 | arch_phys_wc_add(vesafb_fix.smem_start, | ||
425 | temp_size); | ||
426 | temp_size >>= 1; | ||
427 | } while (temp_size >= PAGE_SIZE && par->wc_cookie < 0); | ||
435 | 428 | ||
436 | /* Try and find a power of two to add */ | ||
437 | do { | ||
438 | rc = mtrr_add(vesafb_fix.smem_start, temp_size, | ||
439 | type, 1); | ||
440 | temp_size >>= 1; | ||
441 | } while (temp_size >= PAGE_SIZE && rc == -EINVAL); | ||
442 | } | ||
443 | } | ||
444 | #endif | ||
445 | |||
446 | switch (mtrr) { | ||
447 | case 1: /* uncachable */ | ||
448 | info->screen_base = ioremap_nocache(vesafb_fix.smem_start, vesafb_fix.smem_len); | ||
449 | break; | ||
450 | case 2: /* write-back */ | ||
451 | info->screen_base = ioremap_cache(vesafb_fix.smem_start, vesafb_fix.smem_len); | ||
452 | break; | ||
453 | case 3: /* write-combining */ | ||
454 | info->screen_base = ioremap_wc(vesafb_fix.smem_start, vesafb_fix.smem_len); | 429 | info->screen_base = ioremap_wc(vesafb_fix.smem_start, vesafb_fix.smem_len); |
455 | break; | 430 | } else { |
456 | case 4: /* write-through */ | 431 | if (mtrr && mtrr != 3) |
457 | default: | 432 | WARN_ONCE(1, "Only MTRR_TYPE_WRCOMB (3) make sense\n"); |
458 | info->screen_base = ioremap(vesafb_fix.smem_start, vesafb_fix.smem_len); | 433 | info->screen_base = ioremap(vesafb_fix.smem_start, vesafb_fix.smem_len); |
459 | break; | ||
460 | } | 434 | } |
435 | |||
461 | if (!info->screen_base) { | 436 | if (!info->screen_base) { |
462 | printk(KERN_ERR | 437 | printk(KERN_ERR |
463 | "vesafb: abort, cannot ioremap video memory 0x%x @ 0x%lx\n", | 438 | "vesafb: abort, cannot ioremap video memory 0x%x @ 0x%lx\n", |
@@ -492,6 +467,7 @@ static int vesafb_probe(struct platform_device *dev) | |||
492 | fb_info(info, "%s frame buffer device\n", info->fix.id); | 467 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
493 | return 0; | 468 | return 0; |
494 | err: | 469 | err: |
470 | arch_phys_wc_del(par->wc_cookie); | ||
495 | if (info->screen_base) | 471 | if (info->screen_base) |
496 | iounmap(info->screen_base); | 472 | iounmap(info->screen_base); |
497 | framebuffer_release(info); | 473 | framebuffer_release(info); |
diff --git a/include/linux/platform_data/video-msm_fb.h b/include/linux/platform_data/video-msm_fb.h deleted file mode 100644 index 31449be3eadb..000000000000 --- a/include/linux/platform_data/video-msm_fb.h +++ /dev/null | |||
@@ -1,146 +0,0 @@ | |||
1 | /* | ||
2 | * Internal shared definitions for various MSM framebuffer parts. | ||
3 | * | ||
4 | * Copyright (C) 2007 Google Incorporated | ||
5 | * | ||
6 | * This software is licensed under the terms of the GNU General Public | ||
7 | * License version 2, as published by the Free Software Foundation, and | ||
8 | * may be copied, distributed, and modified under those terms. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _MSM_FB_H_ | ||
17 | #define _MSM_FB_H_ | ||
18 | |||
19 | #include <linux/device.h> | ||
20 | |||
21 | struct mddi_info; | ||
22 | |||
23 | struct msm_fb_data { | ||
24 | int xres; /* x resolution in pixels */ | ||
25 | int yres; /* y resolution in pixels */ | ||
26 | int width; /* disply width in mm */ | ||
27 | int height; /* display height in mm */ | ||
28 | unsigned output_format; | ||
29 | }; | ||
30 | |||
31 | struct msmfb_callback { | ||
32 | void (*func)(struct msmfb_callback *); | ||
33 | }; | ||
34 | |||
35 | enum { | ||
36 | MSM_MDDI_PMDH_INTERFACE, | ||
37 | MSM_MDDI_EMDH_INTERFACE, | ||
38 | MSM_EBI2_INTERFACE, | ||
39 | }; | ||
40 | |||
41 | #define MSMFB_CAP_PARTIAL_UPDATES (1 << 0) | ||
42 | |||
43 | struct msm_panel_data { | ||
44 | /* turns off the fb memory */ | ||
45 | int (*suspend)(struct msm_panel_data *); | ||
46 | /* turns on the fb memory */ | ||
47 | int (*resume)(struct msm_panel_data *); | ||
48 | /* turns off the panel */ | ||
49 | int (*blank)(struct msm_panel_data *); | ||
50 | /* turns on the panel */ | ||
51 | int (*unblank)(struct msm_panel_data *); | ||
52 | void (*wait_vsync)(struct msm_panel_data *); | ||
53 | void (*request_vsync)(struct msm_panel_data *, struct msmfb_callback *); | ||
54 | void (*clear_vsync)(struct msm_panel_data *); | ||
55 | /* from the enum above */ | ||
56 | unsigned interface_type; | ||
57 | /* data to be passed to the fb driver */ | ||
58 | struct msm_fb_data *fb_data; | ||
59 | |||
60 | /* capabilities supported by the panel */ | ||
61 | uint32_t caps; | ||
62 | }; | ||
63 | |||
64 | struct msm_mddi_client_data { | ||
65 | void (*suspend)(struct msm_mddi_client_data *); | ||
66 | void (*resume)(struct msm_mddi_client_data *); | ||
67 | void (*activate_link)(struct msm_mddi_client_data *); | ||
68 | void (*remote_write)(struct msm_mddi_client_data *, uint32_t val, | ||
69 | uint32_t reg); | ||
70 | uint32_t (*remote_read)(struct msm_mddi_client_data *, uint32_t reg); | ||
71 | void (*auto_hibernate)(struct msm_mddi_client_data *, int); | ||
72 | /* custom data that needs to be passed from the board file to a | ||
73 | * particular client */ | ||
74 | void *private_client_data; | ||
75 | struct resource *fb_resource; | ||
76 | /* from the list above */ | ||
77 | unsigned interface_type; | ||
78 | }; | ||
79 | |||
80 | struct msm_mddi_platform_data { | ||
81 | unsigned int clk_rate; | ||
82 | void (*power_client)(struct msm_mddi_client_data *, int on); | ||
83 | |||
84 | /* fixup the mfr name, product id */ | ||
85 | void (*fixup)(uint16_t *mfr_name, uint16_t *product_id); | ||
86 | |||
87 | struct resource *fb_resource; /*optional*/ | ||
88 | /* number of clients in the list that follows */ | ||
89 | int num_clients; | ||
90 | /* array of client information of clients */ | ||
91 | struct { | ||
92 | unsigned product_id; /* mfr id in top 16 bits, product id | ||
93 | * in lower 16 bits | ||
94 | */ | ||
95 | char *name; /* the device name will be the platform | ||
96 | * device name registered for the client, | ||
97 | * it should match the name of the associated | ||
98 | * driver | ||
99 | */ | ||
100 | unsigned id; /* id for mddi client device node, will also | ||
101 | * be used as device id of panel devices, if | ||
102 | * the client device will have multiple panels | ||
103 | * space must be left here for them | ||
104 | */ | ||
105 | void *client_data; /* required private client data */ | ||
106 | unsigned int clk_rate; /* optional: if the client requires a | ||
107 | * different mddi clk rate | ||
108 | */ | ||
109 | } client_platform_data[]; | ||
110 | }; | ||
111 | |||
112 | struct mdp_blit_req; | ||
113 | struct fb_info; | ||
114 | struct mdp_device { | ||
115 | struct device dev; | ||
116 | void (*dma)(struct mdp_device *mpd, uint32_t addr, | ||
117 | uint32_t stride, uint32_t w, uint32_t h, uint32_t x, | ||
118 | uint32_t y, struct msmfb_callback *callback, int interface); | ||
119 | void (*dma_wait)(struct mdp_device *mdp); | ||
120 | int (*blit)(struct mdp_device *mdp, struct fb_info *fb, | ||
121 | struct mdp_blit_req *req); | ||
122 | void (*set_grp_disp)(struct mdp_device *mdp, uint32_t disp_id); | ||
123 | }; | ||
124 | |||
125 | struct class_interface; | ||
126 | int register_mdp_client(struct class_interface *class_intf); | ||
127 | |||
128 | /**** private client data structs go below this line ***/ | ||
129 | |||
130 | struct msm_mddi_bridge_platform_data { | ||
131 | /* from board file */ | ||
132 | int (*init)(struct msm_mddi_bridge_platform_data *, | ||
133 | struct msm_mddi_client_data *); | ||
134 | int (*uninit)(struct msm_mddi_bridge_platform_data *, | ||
135 | struct msm_mddi_client_data *); | ||
136 | /* passed to panel for use by the fb driver */ | ||
137 | int (*blank)(struct msm_mddi_bridge_platform_data *, | ||
138 | struct msm_mddi_client_data *); | ||
139 | int (*unblank)(struct msm_mddi_bridge_platform_data *, | ||
140 | struct msm_mddi_client_data *); | ||
141 | struct msm_fb_data fb_data; | ||
142 | }; | ||
143 | |||
144 | |||
145 | |||
146 | #endif | ||
diff --git a/include/video/neomagic.h b/include/video/neomagic.h index bc5013e8059d..91e225a6107d 100644 --- a/include/video/neomagic.h +++ b/include/video/neomagic.h | |||
@@ -159,10 +159,7 @@ struct neofb_par { | |||
159 | unsigned char VCLK3NumeratorHigh; | 159 | unsigned char VCLK3NumeratorHigh; |
160 | unsigned char VCLK3Denominator; | 160 | unsigned char VCLK3Denominator; |
161 | unsigned char VerticalExt; | 161 | unsigned char VerticalExt; |
162 | 162 | int wc_cookie; | |
163 | #ifdef CONFIG_MTRR | ||
164 | int mtrr; | ||
165 | #endif | ||
166 | u8 __iomem *mmio_vbase; | 163 | u8 __iomem *mmio_vbase; |
167 | u8 cursorOff; | 164 | u8 cursorOff; |
168 | u8 *cursorPad; /* Must die !! */ | 165 | u8 *cursorPad; /* Must die !! */ |
diff --git a/include/video/tdfx.h b/include/video/tdfx.h index befbaf0a92d8..69674b94bb68 100644 --- a/include/video/tdfx.h +++ b/include/video/tdfx.h | |||
@@ -196,7 +196,7 @@ struct tdfx_par { | |||
196 | u32 palette[16]; | 196 | u32 palette[16]; |
197 | void __iomem *regbase_virt; | 197 | void __iomem *regbase_virt; |
198 | unsigned long iobase; | 198 | unsigned long iobase; |
199 | int mtrr_handle; | 199 | int wc_cookie; |
200 | #ifdef CONFIG_FB_3DFX_I2C | 200 | #ifdef CONFIG_FB_3DFX_I2C |
201 | struct tdfxfb_i2c_chan chan[2]; | 201 | struct tdfxfb_i2c_chan chan[2]; |
202 | #endif | 202 | #endif |
diff --git a/sound/soc/omap/omap-hdmi-audio.c b/sound/soc/omap/omap-hdmi-audio.c index 4775da4c4db5..aeef25c0cb3d 100644 --- a/sound/soc/omap/omap-hdmi-audio.c +++ b/sound/soc/omap/omap-hdmi-audio.c | |||
@@ -210,16 +210,18 @@ static int hdmi_dai_hw_params(struct snd_pcm_substream *substream, | |||
210 | 210 | ||
211 | cea->db3 = 0; /* not used, all zeros */ | 211 | cea->db3 = 0; /* not used, all zeros */ |
212 | 212 | ||
213 | /* | ||
214 | * The OMAP HDMI IP requires to use the 8-channel channel code when | ||
215 | * transmitting more than two channels. | ||
216 | */ | ||
217 | if (params_channels(params) == 2) | 213 | if (params_channels(params) == 2) |
218 | cea->db4_ca = 0x0; | 214 | cea->db4_ca = 0x0; |
215 | else if (params_channels(params) == 6) | ||
216 | cea->db4_ca = 0xb; | ||
219 | else | 217 | else |
220 | cea->db4_ca = 0x13; | 218 | cea->db4_ca = 0x13; |
221 | 219 | ||
222 | cea->db5_dminh_lsv = CEA861_AUDIO_INFOFRAME_DB5_DM_INH_PROHIBITED; | 220 | if (cea->db4_ca == 0x00) |
221 | cea->db5_dminh_lsv = CEA861_AUDIO_INFOFRAME_DB5_DM_INH_PERMITTED; | ||
222 | else | ||
223 | cea->db5_dminh_lsv = CEA861_AUDIO_INFOFRAME_DB5_DM_INH_PROHIBITED; | ||
224 | |||
223 | /* the expression is trivial but makes clear what we are doing */ | 225 | /* the expression is trivial but makes clear what we are doing */ |
224 | cea->db5_dminh_lsv |= (0 & CEA861_AUDIO_INFOFRAME_DB5_LSV); | 226 | cea->db5_dminh_lsv |= (0 & CEA861_AUDIO_INFOFRAME_DB5_LSV); |
225 | 227 | ||