diff options
| author | Xu Han <xu.han@intel.com> | 2017-03-28 22:13:56 -0400 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2017-03-29 03:28:51 -0400 |
| commit | 18af19dbe1a521921b148b8f82d03e585f0bed41 (patch) | |
| tree | 55e5ab760d62d2892d84b4e9b8dde5a76db18006 | |
| parent | 7a7a65617b84912287ec4c6ed7b85f9418c7304b (diff) | |
drm/i915/gvt: Add KBL platform definition.
Add KBL platform definition.
Signed-off-by: Xu Han <xu.han@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/mmio.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h index a3a027025cd0..7edd66f38ef9 100644 --- a/drivers/gpu/drm/i915/gvt/mmio.h +++ b/drivers/gpu/drm/i915/gvt/mmio.h | |||
| @@ -44,20 +44,21 @@ struct intel_vgpu; | |||
| 44 | #define D_HSW (1 << 2) | 44 | #define D_HSW (1 << 2) |
| 45 | #define D_BDW (1 << 3) | 45 | #define D_BDW (1 << 3) |
| 46 | #define D_SKL (1 << 4) | 46 | #define D_SKL (1 << 4) |
| 47 | #define D_KBL (1 << 5) | ||
| 47 | 48 | ||
| 48 | #define D_GEN9PLUS (D_SKL) | 49 | #define D_GEN9PLUS (D_SKL | D_KBL) |
| 49 | #define D_GEN8PLUS (D_BDW | D_SKL) | 50 | #define D_GEN8PLUS (D_BDW | D_SKL | D_KBL) |
| 50 | #define D_GEN75PLUS (D_HSW | D_BDW | D_SKL) | 51 | #define D_GEN75PLUS (D_HSW | D_BDW | D_SKL | D_KBL) |
| 51 | #define D_GEN7PLUS (D_IVB | D_HSW | D_BDW | D_SKL) | 52 | #define D_GEN7PLUS (D_IVB | D_HSW | D_BDW | D_SKL | D_KBL) |
| 52 | 53 | ||
| 53 | #define D_SKL_PLUS (D_SKL) | 54 | #define D_SKL_PLUS (D_SKL | D_KBL) |
| 54 | #define D_BDW_PLUS (D_BDW | D_SKL) | 55 | #define D_BDW_PLUS (D_BDW | D_SKL | D_KBL) |
| 55 | #define D_HSW_PLUS (D_HSW | D_BDW | D_SKL) | 56 | #define D_HSW_PLUS (D_HSW | D_BDW | D_SKL | D_KBL) |
| 56 | #define D_IVB_PLUS (D_IVB | D_HSW | D_BDW | D_SKL) | 57 | #define D_IVB_PLUS (D_IVB | D_HSW | D_BDW | D_SKL | D_KBL) |
| 57 | 58 | ||
| 58 | #define D_PRE_BDW (D_SNB | D_IVB | D_HSW) | 59 | #define D_PRE_BDW (D_SNB | D_IVB | D_HSW) |
| 59 | #define D_PRE_SKL (D_SNB | D_IVB | D_HSW | D_BDW) | 60 | #define D_PRE_SKL (D_SNB | D_IVB | D_HSW | D_BDW) |
| 60 | #define D_ALL (D_SNB | D_IVB | D_HSW | D_BDW | D_SKL) | 61 | #define D_ALL (D_SNB | D_IVB | D_HSW | D_BDW | D_SKL | D_KBL) |
| 61 | 62 | ||
| 62 | struct intel_gvt_mmio_info { | 63 | struct intel_gvt_mmio_info { |
| 63 | u32 offset; | 64 | u32 offset; |