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authorSteven J. Hill <steven.hill@cavium.com>2016-07-23 06:42:50 -0400
committerMark Brown <broonie@kernel.org>2016-07-24 16:54:29 -0400
commit187fc9b37458547e198eaf9af4b33c56999748ad (patch)
treec8f8ab00a7093f66047d72bb555f6fbd15e30a88
parent523d939ef98fd712632d93a5a2b588e477a7565e (diff)
spi: octeon: Convert driver to use readq()/writeq() functions
Remove all calls to cvmx_read_csr()/cvmx_write_csr() and use the portable readq()/writeq() functions. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--drivers/spi/spi-octeon.c23
1 files changed, 11 insertions, 12 deletions
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
index 3b170093989f..b53ba530a1c8 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-octeon.c
@@ -27,7 +27,7 @@
27#define OCTEON_SPI_MAX_CLOCK_HZ 16000000 27#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
28 28
29struct octeon_spi { 29struct octeon_spi {
30 u64 register_base; 30 void __iomem *register_base;
31 u64 last_cfg; 31 u64 last_cfg;
32 u64 cs_enax; 32 u64 cs_enax;
33}; 33};
@@ -40,7 +40,7 @@ static void octeon_spi_wait_ready(struct octeon_spi *p)
40 do { 40 do {
41 if (loops++) 41 if (loops++)
42 __delay(500); 42 __delay(500);
43 mpi_sts.u64 = cvmx_read_csr(p->register_base + OCTEON_SPI_STS); 43 mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS);
44 } while (mpi_sts.s.busy); 44 } while (mpi_sts.s.busy);
45} 45}
46 46
@@ -85,7 +85,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
85 85
86 if (mpi_cfg.u64 != p->last_cfg) { 86 if (mpi_cfg.u64 != p->last_cfg) {
87 p->last_cfg = mpi_cfg.u64; 87 p->last_cfg = mpi_cfg.u64;
88 cvmx_write_csr(p->register_base + OCTEON_SPI_CFG, mpi_cfg.u64); 88 writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG);
89 } 89 }
90 tx_buf = xfer->tx_buf; 90 tx_buf = xfer->tx_buf;
91 rx_buf = xfer->rx_buf; 91 rx_buf = xfer->rx_buf;
@@ -97,19 +97,19 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
97 d = *tx_buf++; 97 d = *tx_buf++;
98 else 98 else
99 d = 0; 99 d = 0;
100 cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); 100 writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
101 } 101 }
102 mpi_tx.u64 = 0; 102 mpi_tx.u64 = 0;
103 mpi_tx.s.csid = spi->chip_select; 103 mpi_tx.s.csid = spi->chip_select;
104 mpi_tx.s.leavecs = 1; 104 mpi_tx.s.leavecs = 1;
105 mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0; 105 mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
106 mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES; 106 mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
107 cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64); 107 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);
108 108
109 octeon_spi_wait_ready(p); 109 octeon_spi_wait_ready(p);
110 if (rx_buf) 110 if (rx_buf)
111 for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) { 111 for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
112 u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i)); 112 u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
113 *rx_buf++ = (u8)v; 113 *rx_buf++ = (u8)v;
114 } 114 }
115 len -= OCTEON_SPI_MAX_BYTES; 115 len -= OCTEON_SPI_MAX_BYTES;
@@ -121,7 +121,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
121 d = *tx_buf++; 121 d = *tx_buf++;
122 else 122 else
123 d = 0; 123 d = 0;
124 cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); 124 writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
125 } 125 }
126 126
127 mpi_tx.u64 = 0; 127 mpi_tx.u64 = 0;
@@ -132,12 +132,12 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
132 mpi_tx.s.leavecs = !xfer->cs_change; 132 mpi_tx.s.leavecs = !xfer->cs_change;
133 mpi_tx.s.txnum = tx_buf ? len : 0; 133 mpi_tx.s.txnum = tx_buf ? len : 0;
134 mpi_tx.s.totnum = len; 134 mpi_tx.s.totnum = len;
135 cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64); 135 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);
136 136
137 octeon_spi_wait_ready(p); 137 octeon_spi_wait_ready(p);
138 if (rx_buf) 138 if (rx_buf)
139 for (i = 0; i < len; i++) { 139 for (i = 0; i < len; i++) {
140 u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i)); 140 u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
141 *rx_buf++ = (u8)v; 141 *rx_buf++ = (u8)v;
142 } 142 }
143 143
@@ -193,7 +193,7 @@ static int octeon_spi_probe(struct platform_device *pdev)
193 goto fail; 193 goto fail;
194 } 194 }
195 195
196 p->register_base = (u64)reg_base; 196 p->register_base = reg_base;
197 197
198 master->num_chipselect = 4; 198 master->num_chipselect = 4;
199 master->mode_bits = SPI_CPHA | 199 master->mode_bits = SPI_CPHA |
@@ -225,10 +225,9 @@ static int octeon_spi_remove(struct platform_device *pdev)
225{ 225{
226 struct spi_master *master = platform_get_drvdata(pdev); 226 struct spi_master *master = platform_get_drvdata(pdev);
227 struct octeon_spi *p = spi_master_get_devdata(master); 227 struct octeon_spi *p = spi_master_get_devdata(master);
228 u64 register_base = p->register_base;
229 228
230 /* Clear the CSENA* and put everything in a known state. */ 229 /* Clear the CSENA* and put everything in a known state. */
231 cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0); 230 writeq(0, p->register_base + OCTEON_SPI_CFG);
232 231
233 return 0; 232 return 0;
234} 233}