drm/amd/powerplay: fix PSI feature on Polars12.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5 files changed, 36 insertions, 2 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index 4b0a94cc995e..953e0c9ad7cd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -1396,3 +1396,25 @@ int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
 
         return 0;
 }
+
+int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+                                uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
+                                uint16_t *load_line)
+{
+        ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
+                (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
+
+        const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
+
+        PP_ASSERT_WITH_CODE((NULL != voltage_info),
+                        "Could not find Voltage Table in BIOS.", return -EINVAL);
+
+        voltage_object = atomctrl_lookup_voltage_type_v3
+                (voltage_info, voltage_type,  VOLTAGE_OBJ_SVID2);
+
+        *svd_gpio_id = voltage_object->asSVID2Obj.ucSVDGpioId;
+        *svc_gpio_id = voltage_object->asSVID2Obj.ucSVCGpioId;
+        *load_line = voltage_object->asSVID2Obj.usLoadLine_PSI;
+
+        return 0;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
index fc898afce002..e9fe2e84006b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
@@ -311,5 +311,8 @@ extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_a
 
 extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
 
+extern int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+                                uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
+                                uint16_t *load_line);
 #endif
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b1de9e8ccdbc..f75ee33ec5bb 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1383,6 +1383,15 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
         data->force_pcie_gen = PP_PCIEGenInvalid;
         data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
 
+        if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) {
+                uint8_t tmp1, tmp2;
+                uint16_t tmp3 = 0;
+                atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
+                                                &tmp3);
+                tmp3 = (tmp3 >> 5) & 0x3;
+                data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
+        }
+
         data->fast_watermark_threshold = 100;
         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index 27e7f76ad8a6..f221e17b67e7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -268,7 +268,7 @@ struct smu7_hwmgr {
         uint32_t                       fast_watermark_threshold;
 
         /* ---- Phase Shedding ---- */
-        bool                           vddc_phase_shed_control;
+        uint8_t                           vddc_phase_shed_control;
 
         /* ---- DI/DT ---- */
         struct smu7_display_timing        display_timing;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index c6c3c5751ac7..80e2329a1b9e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -503,7 +503,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 
-        if (smumgr->is_kicker)
+        if (smumgr->chip_id == CHIP_POLARIS12 || smumgr->is_kicker)
                 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
         else
                 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;