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authorKan Liang <kan.liang@linux.intel.com>2018-03-12 10:45:37 -0400
committerIngo Molnar <mingo@kernel.org>2018-03-20 03:58:29 -0400
commit174afc3e7dd7823df8218e16e7768b834097184e (patch)
treef6521428aebf7e8f61ca0d40a5b09daf9cf222fe
parente340895c9ed0b44548f08bbaaee4afc7bfacd354 (diff)
perf/x86/intel: Rename confusing 'freerunning PEBS' API and implementation to 'large PEBS'
The 'freerunning PEBS' and 'large PEBS' are the same thing. Both of these names appear in the code and in the API, which causes confusion. Rename 'freerunning PEBS' to 'large PEBS' to unify the code, which eliminates the confusion. No functional change. Reported-by: Vince Weaver <vincent.weaver@maine.edu> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1520865937-22910-1-git-send-email-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r--arch/x86/events/core.c2
-rw-r--r--arch/x86/events/intel/core.c12
-rw-r--r--arch/x86/events/intel/ds.c6
-rw-r--r--arch/x86/events/perf_event.h6
4 files changed, 13 insertions, 13 deletions
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 3d24edfef3e4..88797c80b3e0 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2119,7 +2119,7 @@ static int x86_pmu_event_init(struct perf_event *event)
2119 } 2119 }
2120 2120
2121 if (READ_ONCE(x86_pmu.attr_rdpmc) && 2121 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2122 !(event->hw.flags & PERF_X86_EVENT_FREERUNNING)) 2122 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2123 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; 2123 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2124 2124
2125 return err; 2125 return err;
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9b18a227fff7..1e41d7508d99 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2952,9 +2952,9 @@ static void intel_pebs_aliases_skl(struct perf_event *event)
2952 return intel_pebs_aliases_precdist(event); 2952 return intel_pebs_aliases_precdist(event);
2953} 2953}
2954 2954
2955static unsigned long intel_pmu_free_running_flags(struct perf_event *event) 2955static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
2956{ 2956{
2957 unsigned long flags = x86_pmu.free_running_flags; 2957 unsigned long flags = x86_pmu.large_pebs_flags;
2958 2958
2959 if (event->attr.use_clockid) 2959 if (event->attr.use_clockid)
2960 flags &= ~PERF_SAMPLE_TIME; 2960 flags &= ~PERF_SAMPLE_TIME;
@@ -2976,8 +2976,8 @@ static int intel_pmu_hw_config(struct perf_event *event)
2976 if (!event->attr.freq) { 2976 if (!event->attr.freq) {
2977 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 2977 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
2978 if (!(event->attr.sample_type & 2978 if (!(event->attr.sample_type &
2979 ~intel_pmu_free_running_flags(event))) 2979 ~intel_pmu_large_pebs_flags(event)))
2980 event->hw.flags |= PERF_X86_EVENT_FREERUNNING; 2980 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
2981 } 2981 }
2982 if (x86_pmu.pebs_aliases) 2982 if (x86_pmu.pebs_aliases)
2983 x86_pmu.pebs_aliases(event); 2983 x86_pmu.pebs_aliases(event);
@@ -3460,7 +3460,7 @@ static __initconst const struct x86_pmu core_pmu = {
3460 .event_map = intel_pmu_event_map, 3460 .event_map = intel_pmu_event_map,
3461 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3461 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3462 .apic = 1, 3462 .apic = 1,
3463 .free_running_flags = PEBS_FREERUNNING_FLAGS, 3463 .large_pebs_flags = LARGE_PEBS_FLAGS,
3464 3464
3465 /* 3465 /*
3466 * Intel PMCs cannot be accessed sanely above 32-bit width, 3466 * Intel PMCs cannot be accessed sanely above 32-bit width,
@@ -3502,7 +3502,7 @@ static __initconst const struct x86_pmu intel_pmu = {
3502 .event_map = intel_pmu_event_map, 3502 .event_map = intel_pmu_event_map,
3503 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3503 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3504 .apic = 1, 3504 .apic = 1,
3505 .free_running_flags = PEBS_FREERUNNING_FLAGS, 3505 .large_pebs_flags = LARGE_PEBS_FLAGS,
3506 /* 3506 /*
3507 * Intel PMCs cannot be accessed sanely above 32 bit width, 3507 * Intel PMCs cannot be accessed sanely above 32 bit width,
3508 * so we install an artificial 1<<31 period regardless of 3508 * so we install an artificial 1<<31 period regardless of
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 18c25ab28557..d8015235ba76 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -935,7 +935,7 @@ void intel_pmu_pebs_add(struct perf_event *event)
935 bool needed_cb = pebs_needs_sched_cb(cpuc); 935 bool needed_cb = pebs_needs_sched_cb(cpuc);
936 936
937 cpuc->n_pebs++; 937 cpuc->n_pebs++;
938 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) 938 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
939 cpuc->n_large_pebs++; 939 cpuc->n_large_pebs++;
940 940
941 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); 941 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
@@ -975,7 +975,7 @@ void intel_pmu_pebs_del(struct perf_event *event)
975 bool needed_cb = pebs_needs_sched_cb(cpuc); 975 bool needed_cb = pebs_needs_sched_cb(cpuc);
976 976
977 cpuc->n_pebs--; 977 cpuc->n_pebs--;
978 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) 978 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
979 cpuc->n_large_pebs--; 979 cpuc->n_large_pebs--;
980 980
981 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); 981 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
@@ -1530,7 +1530,7 @@ void __init intel_ds_init(void)
1530 x86_pmu.pebs_record_size = 1530 x86_pmu.pebs_record_size =
1531 sizeof(struct pebs_record_skl); 1531 sizeof(struct pebs_record_skl);
1532 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1532 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1533 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME; 1533 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
1534 break; 1534 break;
1535 1535
1536 default: 1536 default:
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 78f91ec1056e..39cd0615f04f 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -69,7 +69,7 @@ struct event_constraint {
69#define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */ 69#define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */
70#define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */ 70#define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */
71#define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */ 71#define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */
72#define PERF_X86_EVENT_FREERUNNING 0x0800 /* use freerunning PEBS */ 72#define PERF_X86_EVENT_LARGE_PEBS 0x0800 /* use large PEBS */
73 73
74 74
75struct amd_nb { 75struct amd_nb {
@@ -88,7 +88,7 @@ struct amd_nb {
88 * REGS_USER can be handled for events limited to ring 3. 88 * REGS_USER can be handled for events limited to ring 3.
89 * 89 *
90 */ 90 */
91#define PEBS_FREERUNNING_FLAGS \ 91#define LARGE_PEBS_FLAGS \
92 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 92 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
93 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 93 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
94 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 94 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
@@ -608,7 +608,7 @@ struct x86_pmu {
608 struct event_constraint *pebs_constraints; 608 struct event_constraint *pebs_constraints;
609 void (*pebs_aliases)(struct perf_event *event); 609 void (*pebs_aliases)(struct perf_event *event);
610 int max_pebs_events; 610 int max_pebs_events;
611 unsigned long free_running_flags; 611 unsigned long large_pebs_flags;
612 612
613 /* 613 /*
614 * Intel LBR 614 * Intel LBR