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authorBen Skeggs <bskeggs@redhat.com>2013-11-04 23:26:58 -0500
committerBen Skeggs <bskeggs@redhat.com>2013-11-08 00:39:59 -0500
commit16c4f227ffc556a4851518092e2b5979da1280c1 (patch)
tree801918e6d2738a6ecf8b6e044f4870beb58daeef
parentaabf19c27fc72c9c218844c8385744ff5620a229 (diff)
drm/nouveau/fifo: make external class definitions into pointers
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv04.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv10.c14
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv20.c8
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv30.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv40.c32
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv50.c28
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nvc0.c18
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nve0.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/include/engine/fifo.h16
17 files changed, 86 insertions, 86 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
index 971e852dd8a7..59dc340c6416 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
@@ -57,7 +57,7 @@ nv04_identify(struct nouveau_device *device)
57 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 57 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
58 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 58 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
60 device->oclass[NVDEV_ENGINE_FIFO ] = &nv04_fifo_oclass; 60 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
61 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; 61 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
62 device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; 62 device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
63 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 63 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -75,7 +75,7 @@ nv04_identify(struct nouveau_device *device)
75 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 75 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
76 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 76 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
78 device->oclass[NVDEV_ENGINE_FIFO ] = &nv04_fifo_oclass; 78 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
79 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; 79 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
80 device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; 80 device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
81 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 81 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
index 1c4490c42450..a2f44b26fbfc 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
@@ -76,7 +76,7 @@ nv10_identify(struct nouveau_device *device)
76 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 76 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
77 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 77 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
79 device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; 79 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
80 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 80 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
82 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 82 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -95,7 +95,7 @@ nv10_identify(struct nouveau_device *device)
95 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 95 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
96 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 96 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
98 device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; 98 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
99 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 99 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
100 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 100 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
101 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 101 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -114,7 +114,7 @@ nv10_identify(struct nouveau_device *device)
114 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 114 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
115 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 115 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
117 device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; 117 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
118 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 118 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
119 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 119 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
120 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 120 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -133,7 +133,7 @@ nv10_identify(struct nouveau_device *device)
133 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 133 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
134 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 134 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
136 device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; 136 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
137 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 137 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
138 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 138 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
139 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 139 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -152,7 +152,7 @@ nv10_identify(struct nouveau_device *device)
152 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 152 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
153 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 153 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
155 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 155 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
156 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 156 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
157 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 157 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
158 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 158 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -171,7 +171,7 @@ nv10_identify(struct nouveau_device *device)
171 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 171 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
172 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 172 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
174 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 174 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
175 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 175 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
176 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 176 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
177 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 177 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -190,7 +190,7 @@ nv10_identify(struct nouveau_device *device)
190 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 190 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
191 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 191 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
193 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 193 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
194 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 194 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
195 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 195 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
196 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 196 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
index 298a3d3fb6ab..4e02e0f87d06 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
@@ -60,7 +60,7 @@ nv20_identify(struct nouveau_device *device)
60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
61 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 61 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
63 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
65 device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass; 65 device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass;
66 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 66 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -79,7 +79,7 @@ nv20_identify(struct nouveau_device *device)
79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
80 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 80 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
82 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
84 device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; 84 device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
85 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 85 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -98,7 +98,7 @@ nv20_identify(struct nouveau_device *device)
98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
99 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 99 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
101 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
103 device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; 103 device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
104 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 104 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -117,7 +117,7 @@ nv20_identify(struct nouveau_device *device)
117 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 117 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
118 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 118 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
119 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 119 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
120 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 120 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
121 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 121 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
122 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass; 122 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass;
123 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 123 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
index d2d7d934754a..0be52b78139d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
@@ -60,7 +60,7 @@ nv30_identify(struct nouveau_device *device)
60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
61 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 61 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
63 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
65 device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; 65 device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
66 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 66 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -79,7 +79,7 @@ nv30_identify(struct nouveau_device *device)
79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
80 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 80 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
82 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
84 device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; 84 device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
85 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; 85 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@@ -98,7 +98,7 @@ nv30_identify(struct nouveau_device *device)
98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
99 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 99 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
101 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
103 device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; 103 device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
104 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; 104 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
@@ -118,7 +118,7 @@ nv30_identify(struct nouveau_device *device)
118 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 118 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
119 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 119 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
121 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 121 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
122 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 122 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
123 device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; 123 device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
124 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; 124 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
@@ -138,7 +138,7 @@ nv30_identify(struct nouveau_device *device)
138 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 138 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
139 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 139 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
140 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 140 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
141 device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 141 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
142 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 142 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
143 device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass; 143 device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass;
144 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; 144 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
index 31a50d10dd1b..0bf6066658b1 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
@@ -63,7 +63,7 @@ nv40_identify(struct nouveau_device *device)
63 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 63 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
64 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 64 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
65 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 65 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
66 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 66 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
67 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 67 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
68 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 68 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
69 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 69 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
@@ -84,7 +84,7 @@ nv40_identify(struct nouveau_device *device)
84 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 84 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
85 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 85 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
87 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 87 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
88 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 88 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
89 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 89 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
90 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 90 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
@@ -105,7 +105,7 @@ nv40_identify(struct nouveau_device *device)
105 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 105 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
106 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 106 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
108 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 108 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
109 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 109 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
110 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 110 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
111 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 111 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
@@ -126,7 +126,7 @@ nv40_identify(struct nouveau_device *device)
126 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 126 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
127 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 127 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
128 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 128 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
129 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 129 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
130 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 130 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
131 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 131 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
132 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 132 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
@@ -147,7 +147,7 @@ nv40_identify(struct nouveau_device *device)
147 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 147 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
148 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 148 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
150 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 150 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
151 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 151 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
152 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 152 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
153 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 153 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -168,7 +168,7 @@ nv40_identify(struct nouveau_device *device)
168 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 168 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
169 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 169 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
170 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 170 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
171 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 171 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
172 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 172 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
173 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 173 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
174 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 174 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -189,7 +189,7 @@ nv40_identify(struct nouveau_device *device)
189 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 189 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
190 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 190 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
191 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 191 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
192 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 192 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
193 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 193 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
194 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 194 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
195 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 195 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -210,7 +210,7 @@ nv40_identify(struct nouveau_device *device)
210 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 210 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
211 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 211 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
212 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 212 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
213 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 213 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
214 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 214 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
215 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 215 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
216 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 216 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -231,7 +231,7 @@ nv40_identify(struct nouveau_device *device)
231 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 231 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
232 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 232 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
233 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 233 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
234 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 234 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
235 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 235 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
236 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 236 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
237 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 237 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -252,7 +252,7 @@ nv40_identify(struct nouveau_device *device)
252 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 252 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
253 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 253 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
254 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 254 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
255 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 255 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
256 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 256 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
257 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 257 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
258 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 258 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -273,7 +273,7 @@ nv40_identify(struct nouveau_device *device)
273 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 273 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
274 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 274 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
276 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 276 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
277 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 277 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
278 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 278 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
279 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 279 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -294,7 +294,7 @@ nv40_identify(struct nouveau_device *device)
294 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 294 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
295 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 295 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
296 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 296 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
297 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 297 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
298 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 298 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
299 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 299 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
300 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 300 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -315,7 +315,7 @@ nv40_identify(struct nouveau_device *device)
315 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 315 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
316 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 316 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
317 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 317 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
318 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 318 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
319 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 319 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
320 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 320 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
321 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 321 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -336,7 +336,7 @@ nv40_identify(struct nouveau_device *device)
336 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 336 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
337 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 337 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
338 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 338 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
339 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 339 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
340 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 340 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
341 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 341 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
342 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 342 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -357,7 +357,7 @@ nv40_identify(struct nouveau_device *device)
357 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 357 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
358 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 358 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
359 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 359 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
360 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 360 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
361 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 361 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
362 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 362 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
363 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 363 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
@@ -378,7 +378,7 @@ nv40_identify(struct nouveau_device *device)
378 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 378 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
379 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 379 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
380 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 380 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
381 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 381 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
382 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 382 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
383 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 383 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
384 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 384 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
index 129955c84536..3ac753a99297 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
@@ -71,7 +71,7 @@ nv50_identify(struct nouveau_device *device)
71 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 71 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
72 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 72 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
73 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 73 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
74 device->oclass[NVDEV_ENGINE_FIFO ] = &nv50_fifo_oclass; 74 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
75 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 75 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
76 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 76 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
77 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; 77 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
@@ -94,7 +94,7 @@ nv50_identify(struct nouveau_device *device)
94 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 94 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
95 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 95 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
96 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 96 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
97 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 97 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
98 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 98 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
99 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 99 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
100 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 100 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -120,7 +120,7 @@ nv50_identify(struct nouveau_device *device)
120 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 120 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
121 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 121 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
122 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 122 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
123 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 123 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
124 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 124 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
125 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 125 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
126 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 126 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -146,7 +146,7 @@ nv50_identify(struct nouveau_device *device)
146 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 146 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
147 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 147 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
148 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 148 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
149 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 149 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
150 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 150 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
151 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 151 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
152 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 152 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -172,7 +172,7 @@ nv50_identify(struct nouveau_device *device)
172 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 172 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
173 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 173 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
174 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 174 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
175 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 175 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
176 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 176 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
177 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 177 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
178 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 178 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -198,7 +198,7 @@ nv50_identify(struct nouveau_device *device)
198 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 198 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
199 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 199 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
200 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 200 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
201 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 201 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
202 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 202 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
203 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 203 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
204 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 204 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -224,7 +224,7 @@ nv50_identify(struct nouveau_device *device)
224 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 224 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
225 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 225 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
226 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 226 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
227 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 227 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
228 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 228 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
229 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 229 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
230 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 230 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
@@ -250,7 +250,7 @@ nv50_identify(struct nouveau_device *device)
250 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 250 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
251 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 251 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
253 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 253 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
254 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 254 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
255 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 255 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
256 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 256 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -276,7 +276,7 @@ nv50_identify(struct nouveau_device *device)
276 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 276 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
277 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 277 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
278 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 278 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
279 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 279 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
280 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 280 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
281 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 281 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
282 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 282 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
@@ -302,7 +302,7 @@ nv50_identify(struct nouveau_device *device)
302 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 302 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
303 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 303 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
305 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 305 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
306 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 306 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
307 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 307 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
308 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 308 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
@@ -328,7 +328,7 @@ nv50_identify(struct nouveau_device *device)
328 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 328 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
329 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 329 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
330 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 330 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
331 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 331 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
332 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 332 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
333 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 333 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
334 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 334 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -355,7 +355,7 @@ nv50_identify(struct nouveau_device *device)
355 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 355 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
356 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 356 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
357 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 357 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
358 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 358 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
359 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 359 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
360 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 360 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
361 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 361 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
@@ -381,7 +381,7 @@ nv50_identify(struct nouveau_device *device)
381 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 381 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
382 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 382 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
383 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 383 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
384 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 384 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
385 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 385 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
386 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 386 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
387 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 387 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
@@ -407,7 +407,7 @@ nv50_identify(struct nouveau_device *device)
407 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 407 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
408 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 408 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
409 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 409 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
410 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 410 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
411 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 411 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
412 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 412 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
413 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 413 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index b5b4db69cd02..54c22e90ec45 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -73,7 +73,7 @@ nvc0_identify(struct nouveau_device *device)
73 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 73 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
74 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 74 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
76 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 76 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
77 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 77 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
78 device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass; 78 device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass;
79 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 79 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
@@ -102,7 +102,7 @@ nvc0_identify(struct nouveau_device *device)
102 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 102 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
103 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 103 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
104 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 104 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
105 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 105 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
106 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 106 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
107 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; 107 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
108 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 108 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
@@ -131,7 +131,7 @@ nvc0_identify(struct nouveau_device *device)
131 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 131 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
132 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 132 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
133 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 133 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
134 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 134 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
135 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 135 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
136 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; 136 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
137 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 137 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
@@ -159,7 +159,7 @@ nvc0_identify(struct nouveau_device *device)
159 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 159 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
160 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 160 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
161 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 161 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
162 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 162 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
163 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 163 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
164 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; 164 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
165 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 165 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
@@ -188,7 +188,7 @@ nvc0_identify(struct nouveau_device *device)
188 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 188 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
189 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 189 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
190 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 190 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
191 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 191 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
192 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 192 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
193 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; 193 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
194 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 194 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
@@ -217,7 +217,7 @@ nvc0_identify(struct nouveau_device *device)
217 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 217 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
218 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 218 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
219 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 219 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
220 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 220 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
221 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 221 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
222 device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass; 222 device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass;
223 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 223 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
@@ -245,7 +245,7 @@ nvc0_identify(struct nouveau_device *device)
245 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 245 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
246 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 246 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
247 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 247 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
248 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 248 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
249 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 249 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
250 device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass; 250 device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass;
251 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 251 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
@@ -274,7 +274,7 @@ nvc0_identify(struct nouveau_device *device)
274 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 274 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
275 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 275 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
276 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 276 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
277 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 277 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
278 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 278 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
279 device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass; 279 device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
280 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 280 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
@@ -302,7 +302,7 @@ nvc0_identify(struct nouveau_device *device)
302 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 302 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
303 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 303 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
305 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 305 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
306 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 306 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
307 device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass; 307 device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
308 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 308 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index 29eadb568d8d..9171f8d315ff 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -73,7 +73,7 @@ nve0_identify(struct nouveau_device *device)
73 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 73 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
74 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 74 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
76 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 76 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
77 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 77 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
78 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; 78 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
79 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; 79 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
@@ -103,7 +103,7 @@ nve0_identify(struct nouveau_device *device)
103 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 103 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
104 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 104 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
105 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 105 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
106 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 106 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
107 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 107 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
108 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; 108 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
109 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; 109 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
@@ -133,7 +133,7 @@ nve0_identify(struct nouveau_device *device)
133 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 133 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
134 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 134 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
136 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 136 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
137 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 137 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
138 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; 138 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
139 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; 139 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
@@ -163,7 +163,7 @@ nve0_identify(struct nouveau_device *device)
163 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 163 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
164 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 164 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
166 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 166 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
167 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 167 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
168 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; 168 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
169 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; 169 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
@@ -196,7 +196,7 @@ nve0_identify(struct nouveau_device *device)
196 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 196 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
197 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 197 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
198#if 0 198#if 0
199 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 199 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
200 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 200 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
201 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; 201 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
202#endif 202#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
index f877bd524a92..54f26cc801c7 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
@@ -632,8 +632,8 @@ nv04_fifo_init(struct nouveau_object *object)
632 return 0; 632 return 0;
633} 633}
634 634
635struct nouveau_oclass 635struct nouveau_oclass *
636nv04_fifo_oclass = { 636nv04_fifo_oclass = &(struct nouveau_oclass) {
637 .handle = NV_ENGINE(FIFO, 0x04), 637 .handle = NV_ENGINE(FIFO, 0x04),
638 .ofuncs = &(struct nouveau_ofuncs) { 638 .ofuncs = &(struct nouveau_ofuncs) {
639 .ctor = nv04_fifo_ctor, 639 .ctor = nv04_fifo_ctor,
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
index 2c927c1d173b..571a22aa1ae5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
@@ -159,8 +159,8 @@ nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
159 return 0; 159 return 0;
160} 160}
161 161
162struct nouveau_oclass 162struct nouveau_oclass *
163nv10_fifo_oclass = { 163nv10_fifo_oclass = &(struct nouveau_oclass) {
164 .handle = NV_ENGINE(FIFO, 0x10), 164 .handle = NV_ENGINE(FIFO, 0x10),
165 .ofuncs = &(struct nouveau_ofuncs) { 165 .ofuncs = &(struct nouveau_ofuncs) {
166 .ctor = nv10_fifo_ctor, 166 .ctor = nv10_fifo_ctor,
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
index a9cb51d38c57..f25760209316 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
@@ -196,8 +196,8 @@ nv17_fifo_init(struct nouveau_object *object)
196 return 0; 196 return 0;
197} 197}
198 198
199struct nouveau_oclass 199struct nouveau_oclass *
200nv17_fifo_oclass = { 200nv17_fifo_oclass = &(struct nouveau_oclass) {
201 .handle = NV_ENGINE(FIFO, 0x17), 201 .handle = NV_ENGINE(FIFO, 0x17),
202 .ofuncs = &(struct nouveau_ofuncs) { 202 .ofuncs = &(struct nouveau_ofuncs) {
203 .ctor = nv17_fifo_ctor, 203 .ctor = nv17_fifo_ctor,
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
index 5c7433d5069f..343487ed2238 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
@@ -337,8 +337,8 @@ nv40_fifo_init(struct nouveau_object *object)
337 return 0; 337 return 0;
338} 338}
339 339
340struct nouveau_oclass 340struct nouveau_oclass *
341nv40_fifo_oclass = { 341nv40_fifo_oclass = &(struct nouveau_oclass) {
342 .handle = NV_ENGINE(FIFO, 0x40), 342 .handle = NV_ENGINE(FIFO, 0x40),
343 .ofuncs = &(struct nouveau_ofuncs) { 343 .ofuncs = &(struct nouveau_ofuncs) {
344 .ctor = nv40_fifo_ctor, 344 .ctor = nv40_fifo_ctor,
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
index 7e5dff51d3c5..5f555788121c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
@@ -502,8 +502,8 @@ nv50_fifo_init(struct nouveau_object *object)
502 return 0; 502 return 0;
503} 503}
504 504
505struct nouveau_oclass 505struct nouveau_oclass *
506nv50_fifo_oclass = { 506nv50_fifo_oclass = &(struct nouveau_oclass) {
507 .handle = NV_ENGINE(FIFO, 0x50), 507 .handle = NV_ENGINE(FIFO, 0x50),
508 .ofuncs = &(struct nouveau_ofuncs) { 508 .ofuncs = &(struct nouveau_ofuncs) {
509 .ctor = nv50_fifo_ctor, 509 .ctor = nv50_fifo_ctor,
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
index 0c2c18bea9c4..0908dc834c84 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
@@ -435,8 +435,8 @@ nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
435 return 0; 435 return 0;
436} 436}
437 437
438struct nouveau_oclass 438struct nouveau_oclass *
439nv84_fifo_oclass = { 439nv84_fifo_oclass = &(struct nouveau_oclass) {
440 .handle = NV_ENGINE(FIFO, 0x84), 440 .handle = NV_ENGINE(FIFO, 0x84),
441 .ofuncs = &(struct nouveau_ofuncs) { 441 .ofuncs = &(struct nouveau_ofuncs) {
442 .ctor = nv84_fifo_ctor, 442 .ctor = nv84_fifo_ctor,
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
index ce92f289e751..e21453a94971 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
@@ -720,8 +720,8 @@ nvc0_fifo_init(struct nouveau_object *object)
720 return 0; 720 return 0;
721} 721}
722 722
723struct nouveau_oclass 723struct nouveau_oclass *
724nvc0_fifo_oclass = { 724nvc0_fifo_oclass = &(struct nouveau_oclass) {
725 .handle = NV_ENGINE(FIFO, 0xc0), 725 .handle = NV_ENGINE(FIFO, 0xc0),
726 .ofuncs = &(struct nouveau_ofuncs) { 726 .ofuncs = &(struct nouveau_ofuncs) {
727 .ctor = nvc0_fifo_ctor, 727 .ctor = nvc0_fifo_ctor,
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index 8e8121abe31b..fcd449e5aba7 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -675,8 +675,8 @@ nve0_fifo_init(struct nouveau_object *object)
675 return 0; 675 return 0;
676} 676}
677 677
678struct nouveau_oclass 678struct nouveau_oclass *
679nve0_fifo_oclass = { 679nve0_fifo_oclass = &(struct nouveau_oclass) {
680 .handle = NV_ENGINE(FIFO, 0xe0), 680 .handle = NV_ENGINE(FIFO, 0xe0),
681 .ofuncs = &(struct nouveau_ofuncs) { 681 .ofuncs = &(struct nouveau_ofuncs) {
682 .ctor = nve0_fifo_ctor, 682 .ctor = nve0_fifo_ctor,
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
index 633c2f806482..8c32cf4d83c7 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
@@ -101,14 +101,14 @@ nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid);
101#define _nouveau_fifo_init _nouveau_engine_init 101#define _nouveau_fifo_init _nouveau_engine_init
102#define _nouveau_fifo_fini _nouveau_engine_fini 102#define _nouveau_fifo_fini _nouveau_engine_fini
103 103
104extern struct nouveau_oclass nv04_fifo_oclass; 104extern struct nouveau_oclass *nv04_fifo_oclass;
105extern struct nouveau_oclass nv10_fifo_oclass; 105extern struct nouveau_oclass *nv10_fifo_oclass;
106extern struct nouveau_oclass nv17_fifo_oclass; 106extern struct nouveau_oclass *nv17_fifo_oclass;
107extern struct nouveau_oclass nv40_fifo_oclass; 107extern struct nouveau_oclass *nv40_fifo_oclass;
108extern struct nouveau_oclass nv50_fifo_oclass; 108extern struct nouveau_oclass *nv50_fifo_oclass;
109extern struct nouveau_oclass nv84_fifo_oclass; 109extern struct nouveau_oclass *nv84_fifo_oclass;
110extern struct nouveau_oclass nvc0_fifo_oclass; 110extern struct nouveau_oclass *nvc0_fifo_oclass;
111extern struct nouveau_oclass nve0_fifo_oclass; 111extern struct nouveau_oclass *nve0_fifo_oclass;
112 112
113void nv04_fifo_intr(struct nouveau_subdev *); 113void nv04_fifo_intr(struct nouveau_subdev *);
114int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); 114int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 07:03:07 -0400