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authorQais Yousef <qais.yousef@imgtec.com>2015-12-08 08:20:30 -0500
committerThomas Gleixner <tglx@linutronix.de>2016-02-25 04:56:58 -0500
commit16a8083cedbe628228dbb08fc1469c70e6208619 (patch)
treed7d67a7c34c3fa1885ef38fe692c4f75a0a793fa
parent7eb8c99db26cc6499bfb1eba72dffc4730570752 (diff)
irqchip/mips-gic: Add new DT property to reserve IPIs
The new property will allow to specify the range of GIC hwirqs to use for IPIs. This is an optinal property. We preserve the previous behaviour of allocating the last 2 * gic_vpes if it's not specified or DT is not supported. Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: <jason@lakedaemon.net> Cc: <marc.zyngier@arm.com> Cc: <jiang.liu@linux.intel.com> Cc: <linux-mips@linux-mips.org> Cc: <lisa.parratt@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Link: http://lkml.kernel.org/r/1449580830-23652-20-git-send-email-qais.yousef@imgtec.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt7
-rw-r--r--drivers/irqchip/irq-mips-gic.c12
2 files changed, 17 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
index aae4c384ee1f..173595305e26 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
@@ -23,6 +23,12 @@ Optional properties:
23- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors 23- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
24 to which the GIC may not route interrupts. Valid values are 2 - 7. 24 to which the GIC may not route interrupts. Valid values are 2 - 7.
25 This property is ignored if the CPU is started in EIC mode. 25 This property is ignored if the CPU is started in EIC mode.
26- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
27 reserved for IPIs.
28 It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
29 of the reserved range.
30 If not specified, the driver will allocate the last 2 * number of VPEs in the
31 system.
26 32
27Required properties for timer sub-node: 33Required properties for timer sub-node:
28- compatible : Should be "mti,gic-timer". 34- compatible : Should be "mti,gic-timer".
@@ -44,6 +50,7 @@ Example:
44 #interrupt-cells = <3>; 50 #interrupt-cells = <3>;
45 51
46 mti,reserved-cpu-vectors = <7>; 52 mti,reserved-cpu-vectors = <7>;
53 mti,reserved-ipi-vectors = <40 8>;
47 54
48 timer { 55 timer {
49 compatible = "mti,gic-timer"; 56 compatible = "mti,gic-timer";
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 37831a557bcb..94a30da0cfac 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -957,6 +957,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
957 struct device_node *node) 957 struct device_node *node)
958{ 958{
959 unsigned int gicconfig; 959 unsigned int gicconfig;
960 unsigned int v[2];
960 961
961 __gic_base_addr = gic_base_addr; 962 __gic_base_addr = gic_base_addr;
962 963
@@ -1027,8 +1028,15 @@ static void __init __gic_init(unsigned long gic_base_addr,
1027 1028
1028 gic_ipi_domain->bus_token = DOMAIN_BUS_IPI; 1029 gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
1029 1030
1030 /* Make the last 2 * gic_vpes available for IPIs */ 1031 if (node &&
1031 bitmap_set(ipi_resrv, gic_shared_intrs - 2 * gic_vpes, 2 * gic_vpes); 1032 !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
1033 bitmap_set(ipi_resrv, v[0], v[1]);
1034 } else {
1035 /* Make the last 2 * gic_vpes available for IPIs */
1036 bitmap_set(ipi_resrv,
1037 gic_shared_intrs - 2 * gic_vpes,
1038 2 * gic_vpes);
1039 }
1032 1040
1033 gic_basic_init(); 1041 gic_basic_init();
1034} 1042}