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authorRob Herring <robh@kernel.org>2015-12-08 15:44:16 -0500
committerArnd Bergmann <arnd@arndb.de>2015-12-15 17:53:21 -0500
commit16956fed35fecde2201e23458cda193526b19559 (patch)
tree540334f3232efb2bd79c00aaa75dca6d4a7bea5f
parenta8e2894c125f69aaea474592ebebd463bb7e1b0a (diff)
ARM: versatile: switch to DT only booting and remove legacy code
With DT support for clocks, irqchips, timers, and PCI now in place, DT based booting has feature parity with non-DT legacy boot. The final piece is actually enabling common clock support on Versatile. Enabling full DT support requires either removing the old Versatile clock code, updating the legacy boot to use the common clock code, or making DT and legacy boot mutually exclusive. Given that removing legacy boot code is the goal anyway, I am going with the 1st option. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/Kconfig13
-rw-r--r--arch/arm/mach-versatile/Kconfig33
-rw-r--r--arch/arm/mach-versatile/Makefile6
-rw-r--r--arch/arm/mach-versatile/core.c497
-rw-r--r--arch/arm/mach-versatile/core.h9
-rw-r--r--arch/arm/mach-versatile/include/mach/clkdev.h16
-rw-r--r--arch/arm/mach-versatile/include/mach/hardware.h6
-rw-r--r--arch/arm/mach-versatile/include/mach/irqs.h134
-rw-r--r--arch/arm/mach-versatile/include/mach/platform.h174
-rw-r--r--arch/arm/mach-versatile/pci.c368
-rw-r--r--arch/arm/mach-versatile/versatile_ab.c44
-rw-r--r--arch/arm/mach-versatile/versatile_dt.c1
-rw-r--r--arch/arm/mach-versatile/versatile_pb.c91
-rw-r--r--drivers/clk/versatile/Kconfig4
14 files changed, 24 insertions, 1372 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 34e1569a11ee..34e2162213cb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -368,13 +368,16 @@ config ARCH_VERSATILE
368 select ARM_AMBA 368 select ARM_AMBA
369 select ARM_TIMER_SP804 369 select ARM_TIMER_SP804
370 select ARM_VIC 370 select ARM_VIC
371 select CLKDEV_LOOKUP 371 select CLKSRC_VERSATILE
372 select COMMON_CLK
373 select COMMON_CLK_VERSATILE
374 select CPU_ARM926T
372 select GENERIC_CLOCKEVENTS 375 select GENERIC_CLOCKEVENTS
373 select HAVE_MACH_CLKDEV
374 select ICST 376 select ICST
375 select PLAT_VERSATILE 377 select PLAT_VERSATILE
376 select PLAT_VERSATILE_CLOCK 378 select MIGHT_HAVE_PCI
377 select PLAT_VERSATILE_SCHED_CLOCK 379 select SPARSE_IRQ
380 select USE_OF
378 select VERSATILE_FPGA_IRQ 381 select VERSATILE_FPGA_IRQ
379 help 382 help
380 This enables support for ARM Ltd Versatile board. 383 This enables support for ARM Ltd Versatile board.
@@ -926,8 +929,6 @@ source "arch/arm/mach-uniphier/Kconfig"
926 929
927source "arch/arm/mach-ux500/Kconfig" 930source "arch/arm/mach-ux500/Kconfig"
928 931
929source "arch/arm/mach-versatile/Kconfig"
930
931source "arch/arm/mach-vexpress/Kconfig" 932source "arch/arm/mach-vexpress/Kconfig"
932source "arch/arm/plat-versatile/Kconfig" 933source "arch/arm/plat-versatile/Kconfig"
933 934
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
deleted file mode 100644
index 1dba3688275f..000000000000
--- a/arch/arm/mach-versatile/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
1menu "Versatile platform type"
2 depends on ARCH_VERSATILE
3
4config ARCH_VERSATILE_PB
5 bool "Support Versatile Platform Baseboard for ARM926EJ-S"
6 default y
7 select CPU_ARM926T
8 select MIGHT_HAVE_PCI
9 help
10 Include support for the ARM(R) Versatile Platform Baseboard
11 for the ARM926EJ-S.
12
13config MACH_VERSATILE_AB
14 bool "Support Versatile Application Baseboard for ARM926EJ-S"
15 select CPU_ARM926T
16 help
17 Include support for the ARM(R) Versatile Application Baseboard
18 for the ARM926EJ-S.
19
20config MACH_VERSATILE_DT
21 bool "Support Versatile platform from device tree"
22 select CPU_ARM926T
23 select USE_OF
24 help
25 Include support for the ARM(R) Versatile/PB platform,
26 using the device tree for discovery
27
28config MACH_VERSATILE_AUTO
29 def_bool y
30 depends on !ARCH_VERSATILE_PB && !MACH_VERSATILE_AB
31 select MACH_VERSATILE_DT
32
33endmenu
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index 81fa3fe25e1a..ccef51284d0d 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -2,8 +2,4 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := core.o 5obj-y := core.o versatile_dt.o
6obj-$(CONFIG_ARCH_VERSATILE_PB) += versatile_pb.o
7obj-$(CONFIG_MACH_VERSATILE_AB) += versatile_ab.o
8obj-$(CONFIG_MACH_VERSATILE_DT) += versatile_dt.o
9obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 23a04fe5d2ad..072ae192421c 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -23,111 +23,22 @@
23#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/irqdomain.h>
27#include <linux/of_address.h>
28#include <linux/of_platform.h> 26#include <linux/of_platform.h>
29#include <linux/amba/bus.h> 27#include <linux/amba/bus.h>
30#include <linux/amba/clcd.h> 28#include <linux/amba/clcd.h>
31#include <linux/platform_data/video-clcd-versatile.h> 29#include <linux/platform_data/video-clcd-versatile.h>
32#include <linux/amba/pl061.h>
33#include <linux/amba/mmci.h> 30#include <linux/amba/mmci.h>
34#include <linux/amba/pl022.h>
35#include <linux/io.h> 31#include <linux/io.h>
36#include <linux/irqchip/arm-vic.h>
37#include <linux/irqchip/versatile-fpga.h>
38#include <linux/gfp.h>
39#include <linux/clkdev.h>
40#include <linux/mtd/physmap.h> 32#include <linux/mtd/physmap.h>
41#include <linux/bitops.h>
42#include <linux/reboot.h> 33#include <linux/reboot.h>
43 34
44#include <clocksource/timer-sp804.h>
45
46#include <asm/irq.h>
47#include <asm/hardware/icst.h>
48#include <asm/mach-types.h>
49
50#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
51#include <asm/mach/irq.h>
52#include <asm/mach/time.h>
53#include <asm/mach/map.h> 36#include <asm/mach/map.h>
54#include <mach/hardware.h> 37#include <mach/hardware.h>
55#include <mach/platform.h> 38#include <mach/platform.h>
56 39
57#include <plat/sched_clock.h>
58
59#include "core.h" 40#include "core.h"
60 41
61/*
62 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
63 * is the (PA >> 12).
64 *
65 * Setup a VA for the Versatile Vectored Interrupt Controller.
66 */
67#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
68#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
69
70/* These PIC IRQs are valid in each configuration */
71#define PIC_VALID_ALL BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \
72 BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \
73 BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \
74 BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \
75 BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \
76 BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \
77 BIT(SIC_INT_PCI3)
78#if 1
79#define IRQ_MMCI0A IRQ_VICSOURCE22
80#define IRQ_AACI IRQ_VICSOURCE24
81#define IRQ_ETH IRQ_VICSOURCE25
82#define PIC_MASK 0xFFD00000
83#define PIC_VALID PIC_VALID_ALL
84#else
85#define IRQ_MMCI0A IRQ_SIC_MMCI0A
86#define IRQ_AACI IRQ_SIC_AACI
87#define IRQ_ETH IRQ_SIC_ETH
88#define PIC_MASK 0
89#define PIC_VALID PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \
90 BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \
91 BIT(SIC_INT_ETH)
92#endif
93
94/* Lookup table for finding a DT node that represents the vic instance */
95static const struct of_device_id vic_of_match[] __initconst = {
96 { .compatible = "arm,versatile-vic", },
97 {}
98};
99
100static const struct of_device_id sic_of_match[] __initconst = {
101 { .compatible = "arm,versatile-sic", },
102 {}
103};
104
105void __init versatile_init_irq(void)
106{
107 struct device_node *np;
108
109 np = of_find_matching_node_by_address(NULL, vic_of_match,
110 VERSATILE_VIC_BASE);
111 __vic_init(VA_VIC_BASE, 0, IRQ_VIC_START, ~0, 0, np);
112
113 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
114
115 np = of_find_matching_node_by_address(NULL, sic_of_match,
116 VERSATILE_SIC_BASE);
117
118 fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
119 IRQ_VICSOURCE31, PIC_VALID, np);
120
121 /*
122 * Interrupts on secondary controller from 0 to 8 are routed to
123 * source 31 on PIC.
124 * Interrupts from 21 to 31 are routed directly to the VIC on
125 * the corresponding number on primary controller. This is controlled
126 * by setting PIC_ENABLEx.
127 */
128 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
129}
130
131static struct map_desc versatile_io_desc[] __initdata __maybe_unused = { 42static struct map_desc versatile_io_desc[] __initdata __maybe_unused = {
132 { 43 {
133 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE), 44 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
@@ -135,59 +46,22 @@ static struct map_desc versatile_io_desc[] __initdata __maybe_unused = {
135 .length = SZ_4K, 46 .length = SZ_4K,
136 .type = MT_DEVICE 47 .type = MT_DEVICE
137 }, { 48 }, {
138 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
139 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
140 .length = SZ_4K,
141 .type = MT_DEVICE
142 }, {
143 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
144 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
145 .length = SZ_4K,
146 .type = MT_DEVICE
147 }, {
148 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE), 49 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
149 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE), 50 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
150 .length = SZ_4K * 9, 51 .length = SZ_4K * 9,
151 .type = MT_DEVICE 52 .type = MT_DEVICE
152 }, 53 },
153#ifdef CONFIG_MACH_VERSATILE_AB
154 { 54 {
155 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE), 55 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
156 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE), 56 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
157 .length = SZ_64M, 57 .length = SZ_64M,
158 .type = MT_DEVICE 58 .type = MT_DEVICE
159 }, 59 },
160#endif
161#ifdef CONFIG_DEBUG_LL
162 {
163 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
164 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
165 .length = SZ_4K,
166 .type = MT_DEVICE
167 },
168#endif
169#ifdef CONFIG_PCI
170 {
171 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
172 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
173 .length = SZ_4K,
174 .type = MT_DEVICE
175 }, {
176 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
177 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
178 .length = VERSATILE_PCI_BASE_SIZE,
179 .type = MT_DEVICE
180 }, {
181 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
182 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
183 .length = VERSATILE_PCI_CFG_BASE_SIZE,
184 .type = MT_DEVICE
185 },
186#endif
187}; 60};
188 61
189void __init versatile_map_io(void) 62void __init versatile_map_io(void)
190{ 63{
64 debug_ll_io_init();
191 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc)); 65 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
192} 66}
193 67
@@ -217,7 +91,7 @@ static struct resource versatile_flash_resource = {
217 .flags = IORESOURCE_MEM, 91 .flags = IORESOURCE_MEM,
218}; 92};
219 93
220static struct platform_device versatile_flash_device = { 94struct platform_device versatile_flash_device = {
221 .name = "physmap-flash", 95 .name = "physmap-flash",
222 .id = 0, 96 .id = 0,
223 .dev = { 97 .dev = {
@@ -227,52 +101,6 @@ static struct platform_device versatile_flash_device = {
227 .resource = &versatile_flash_resource, 101 .resource = &versatile_flash_resource,
228}; 102};
229 103
230static struct resource smc91x_resources[] = {
231 [0] = {
232 .start = VERSATILE_ETH_BASE,
233 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = IRQ_ETH,
238 .end = IRQ_ETH,
239 .flags = IORESOURCE_IRQ,
240 },
241};
242
243static struct platform_device smc91x_device = {
244 .name = "smc91x",
245 .id = 0,
246 .num_resources = ARRAY_SIZE(smc91x_resources),
247 .resource = smc91x_resources,
248};
249
250static struct resource versatile_i2c_resource = {
251 .start = VERSATILE_I2C_BASE,
252 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
253 .flags = IORESOURCE_MEM,
254};
255
256static struct platform_device versatile_i2c_device = {
257 .name = "versatile-i2c",
258 .id = 0,
259 .num_resources = 1,
260 .resource = &versatile_i2c_resource,
261};
262
263static struct i2c_board_info versatile_i2c_board_info[] = {
264 {
265 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
266 },
267};
268
269static int __init versatile_i2c_init(void)
270{
271 return i2c_register_board_info(0, versatile_i2c_board_info,
272 ARRAY_SIZE(versatile_i2c_board_info));
273}
274arch_initcall(versatile_i2c_init);
275
276#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET) 104#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
277 105
278unsigned int mmc_status(struct device *dev) 106unsigned int mmc_status(struct device *dev)
@@ -295,126 +123,11 @@ static struct mmci_platform_data mmc0_plat_data = {
295 .gpio_cd = -1, 123 .gpio_cd = -1,
296}; 124};
297 125
298static struct resource char_lcd_resources[] = { 126static struct mmci_platform_data mmc1_plat_data = {
299 { 127 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
300 .start = VERSATILE_CHAR_LCD_BASE, 128 .status = mmc_status,
301 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1), 129 .gpio_wp = -1,
302 .flags = IORESOURCE_MEM, 130 .gpio_cd = -1,
303 },
304};
305
306static struct platform_device char_lcd_device = {
307 .name = "arm-charlcd",
308 .id = -1,
309 .num_resources = ARRAY_SIZE(char_lcd_resources),
310 .resource = char_lcd_resources,
311};
312
313static struct resource leds_resources[] = {
314 {
315 .start = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET,
316 .end = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET + 4,
317 .flags = IORESOURCE_MEM,
318 },
319};
320
321static struct platform_device leds_device = {
322 .name = "versatile-leds",
323 .id = -1,
324 .num_resources = ARRAY_SIZE(leds_resources),
325 .resource = leds_resources,
326};
327
328/*
329 * Clock handling
330 */
331static const struct icst_params versatile_oscvco_params = {
332 .ref = 24000000,
333 .vco_max = ICST307_VCO_MAX,
334 .vco_min = ICST307_VCO_MIN,
335 .vd_min = 4 + 8,
336 .vd_max = 511 + 8,
337 .rd_min = 1 + 2,
338 .rd_max = 127 + 2,
339 .s2div = icst307_s2div,
340 .idx2s = icst307_idx2s,
341};
342
343static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
344{
345 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
346 u32 val;
347
348 val = readl(clk->vcoreg) & ~0x7ffff;
349 val |= vco.v | (vco.r << 9) | (vco.s << 16);
350
351 writel(0xa05f, sys_lock);
352 writel(val, clk->vcoreg);
353 writel(0, sys_lock);
354}
355
356static const struct clk_ops osc4_clk_ops = {
357 .round = icst_clk_round,
358 .set = icst_clk_set,
359 .setvco = versatile_oscvco_set,
360};
361
362static struct clk osc4_clk = {
363 .ops = &osc4_clk_ops,
364 .params = &versatile_oscvco_params,
365};
366
367/*
368 * These are fixed clocks.
369 */
370static struct clk ref24_clk = {
371 .rate = 24000000,
372};
373
374static struct clk sp804_clk = {
375 .rate = 1000000,
376};
377
378static struct clk dummy_apb_pclk;
379
380static struct clk_lookup lookups[] = {
381 { /* AMBA bus clock */
382 .con_id = "apb_pclk",
383 .clk = &dummy_apb_pclk,
384 }, { /* UART0 */
385 .dev_id = "dev:f1",
386 .clk = &ref24_clk,
387 }, { /* UART1 */
388 .dev_id = "dev:f2",
389 .clk = &ref24_clk,
390 }, { /* UART2 */
391 .dev_id = "dev:f3",
392 .clk = &ref24_clk,
393 }, { /* UART3 */
394 .dev_id = "fpga:09",
395 .clk = &ref24_clk,
396 }, { /* KMI0 */
397 .dev_id = "fpga:06",
398 .clk = &ref24_clk,
399 }, { /* KMI1 */
400 .dev_id = "fpga:07",
401 .clk = &ref24_clk,
402 }, { /* MMC0 */
403 .dev_id = "fpga:05",
404 .clk = &ref24_clk,
405 }, { /* MMC1 */
406 .dev_id = "fpga:0b",
407 .clk = &ref24_clk,
408 }, { /* SSP */
409 .dev_id = "dev:f4",
410 .clk = &ref24_clk,
411 }, { /* CLCD */
412 .dev_id = "dev:20",
413 .clk = &osc4_clk,
414 }, { /* SP804 timers */
415 .dev_id = "sp804",
416 .clk = &sp804_clk,
417 },
418}; 131};
419 132
420/* 133/*
@@ -449,11 +162,10 @@ static void versatile_clcd_disable(struct clcd_fb *fb)
449 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; 162 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
450 writel(val, sys_clcd); 163 writel(val, sys_clcd);
451 164
452#ifdef CONFIG_MACH_VERSATILE_AB
453 /* 165 /*
454 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off 166 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
455 */ 167 */
456 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) { 168 if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) {
457 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); 169 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
458 unsigned long ctrl; 170 unsigned long ctrl;
459 171
@@ -461,7 +173,6 @@ static void versatile_clcd_disable(struct clcd_fb *fb)
461 ctrl &= ~0x01; 173 ctrl &= ~0x01;
462 writel(ctrl, versatile_ib2_ctrl); 174 writel(ctrl, versatile_ib2_ctrl);
463 } 175 }
464#endif
465} 176}
466 177
467/* 178/*
@@ -502,11 +213,10 @@ static void versatile_clcd_enable(struct clcd_fb *fb)
502 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; 213 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
503 writel(val, sys_clcd); 214 writel(val, sys_clcd);
504 215
505#ifdef CONFIG_MACH_VERSATILE_AB
506 /* 216 /*
507 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on 217 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
508 */ 218 */
509 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) { 219 if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) {
510 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); 220 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
511 unsigned long ctrl; 221 unsigned long ctrl;
512 222
@@ -514,7 +224,6 @@ static void versatile_clcd_enable(struct clcd_fb *fb)
514 ctrl |= 0x01; 224 ctrl |= 0x01;
515 writel(ctrl, versatile_ib2_ctrl); 225 writel(ctrl, versatile_ib2_ctrl);
516 } 226 }
517#endif
518} 227}
519 228
520/* 229/*
@@ -575,113 +284,6 @@ static struct clcd_board clcd_plat_data = {
575 .remove = versatile_clcd_remove_dma, 284 .remove = versatile_clcd_remove_dma,
576}; 285};
577 286
578static struct pl061_platform_data gpio0_plat_data = {
579 .gpio_base = 0,
580 .irq_base = IRQ_GPIO0_START,
581};
582
583static struct pl061_platform_data gpio1_plat_data = {
584 .gpio_base = 8,
585 .irq_base = IRQ_GPIO1_START,
586};
587
588static struct pl061_platform_data gpio2_plat_data = {
589 .gpio_base = 16,
590 .irq_base = IRQ_GPIO2_START,
591};
592
593static struct pl061_platform_data gpio3_plat_data = {
594 .gpio_base = 24,
595 .irq_base = IRQ_GPIO3_START,
596};
597
598static struct pl022_ssp_controller ssp0_plat_data = {
599 .bus_id = 0,
600 .enable_dma = 0,
601 .num_chipselect = 1,
602};
603
604#define AACI_IRQ { IRQ_AACI }
605#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
606#define KMI0_IRQ { IRQ_SIC_KMI0 }
607#define KMI1_IRQ { IRQ_SIC_KMI1 }
608
609/*
610 * These devices are connected directly to the multi-layer AHB switch
611 */
612#define SMC_IRQ { }
613#define MPMC_IRQ { }
614#define CLCD_IRQ { IRQ_CLCDINT }
615#define DMAC_IRQ { IRQ_DMAINT }
616
617/*
618 * These devices are connected via the core APB bridge
619 */
620#define SCTL_IRQ { }
621#define WATCHDOG_IRQ { IRQ_WDOGINT }
622#define GPIO0_IRQ { IRQ_GPIOINT0 }
623#define GPIO1_IRQ { IRQ_GPIOINT1 }
624#define GPIO2_IRQ { IRQ_GPIOINT2 }
625#define GPIO3_IRQ { IRQ_GPIOINT3 }
626#define RTC_IRQ { IRQ_RTCINT }
627
628/*
629 * These devices are connected via the DMA APB bridge
630 */
631#define SCI_IRQ { IRQ_SCIINT }
632#define UART0_IRQ { IRQ_UARTINT0 }
633#define UART1_IRQ { IRQ_UARTINT1 }
634#define UART2_IRQ { IRQ_UARTINT2 }
635#define SSP_IRQ { IRQ_SSPINT }
636
637/* FPGA Primecells */
638APB_DEVICE(aaci, "fpga:04", AACI, NULL);
639APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
640APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
641APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
642
643/* DevChip Primecells */
644AHB_DEVICE(smc, "dev:00", SMC, NULL);
645AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
646AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
647AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
648APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
649APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
650APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
651APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
652APB_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data);
653APB_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data);
654APB_DEVICE(rtc, "dev:e8", RTC, NULL);
655APB_DEVICE(sci0, "dev:f0", SCI, NULL);
656APB_DEVICE(uart0, "dev:f1", UART0, NULL);
657APB_DEVICE(uart1, "dev:f2", UART1, NULL);
658APB_DEVICE(uart2, "dev:f3", UART2, NULL);
659APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
660
661static struct amba_device *amba_devs[] __initdata = {
662 &dmac_device,
663 &uart0_device,
664 &uart1_device,
665 &uart2_device,
666 &smc_device,
667 &mpmc_device,
668 &clcd_device,
669 &sctl_device,
670 &wdog_device,
671 &gpio0_device,
672 &gpio1_device,
673 &gpio2_device,
674 &gpio3_device,
675 &rtc_device,
676 &sci0_device,
677 &ssp0_device,
678 &aaci_device,
679 &mmc0_device,
680 &kmi0_device,
681 &kmi1_device,
682};
683
684#ifdef CONFIG_OF
685/* 287/*
686 * Lookup table for attaching a specific name and platform_data pointer to 288 * Lookup table for attaching a specific name and platform_data pointer to
687 * devices as they get created by of_platform_populate(). Ideally this table 289 * devices as they get created by of_platform_populate(). Ideally this table
@@ -690,43 +292,12 @@ static struct amba_device *amba_devs[] __initdata = {
690 */ 292 */
691struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = { 293struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
692 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data), 294 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
693 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL), 295 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data),
694 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
695 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
696 /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
697 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
698 296
699 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data), 297 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
700 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
701 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
702 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
703 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
704 298
705#if 0
706 /*
707 * These entries are unnecessary because no clocks referencing
708 * them. I've left them in for now as place holders in case
709 * any of them need to be added back, but they should be
710 * removed before actually committing this patch. --gcl
711 */
712 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
713 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
714 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
715 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
716 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
717
718 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
719 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
720 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
721 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
722 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
723 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
724 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
725 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
726#endif
727 {} 299 {}
728}; 300};
729#endif
730 301
731void versatile_restart(enum reboot_mode mode, const char *cmd) 302void versatile_restart(enum reboot_mode mode, const char *cmd)
732{ 303{
@@ -745,12 +316,6 @@ void versatile_restart(enum reboot_mode mode, const char *cmd)
745void __init versatile_init_early(void) 316void __init versatile_init_early(void)
746{ 317{
747 u32 val; 318 u32 val;
748 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
749
750 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
751 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
752
753 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
754 319
755 /* 320 /*
756 * set clock frequency: 321 * set clock frequency:
@@ -764,45 +329,3 @@ void __init versatile_init_early(void)
764 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, 329 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
765 __io_address(VERSATILE_SCTL_BASE)); 330 __io_address(VERSATILE_SCTL_BASE));
766} 331}
767
768void __init versatile_init(void)
769{
770 int i;
771
772 platform_device_register(&versatile_flash_device);
773 platform_device_register(&versatile_i2c_device);
774 platform_device_register(&smc91x_device);
775 platform_device_register(&char_lcd_device);
776 platform_device_register(&leds_device);
777
778 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
779 struct amba_device *d = amba_devs[i];
780 amba_device_register(d, &iomem_resource);
781 }
782}
783
784/*
785 * Where is the timer (VA)?
786 */
787#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
788#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
789#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
790#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
791
792/*
793 * Set up timer interrupt, and return the current time in seconds.
794 */
795void __init versatile_timer_init(void)
796{
797
798 /*
799 * Initialise to a known state (all timers off)
800 */
801 sp804_timer_disable(TIMER0_VA_BASE);
802 sp804_timer_disable(TIMER1_VA_BASE);
803 sp804_timer_disable(TIMER2_VA_BASE);
804 sp804_timer_disable(TIMER3_VA_BASE);
805
806 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
807 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
808}
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index f06d5768e428..c3d71571fc7a 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -26,7 +26,8 @@
26#include <linux/of_platform.h> 26#include <linux/of_platform.h>
27#include <linux/reboot.h> 27#include <linux/reboot.h>
28 28
29extern void __init versatile_init(void); 29extern struct platform_device versatile_flash_device;
30
30extern void __init versatile_init_early(void); 31extern void __init versatile_init_early(void);
31extern void __init versatile_init_irq(void); 32extern void __init versatile_init_irq(void);
32extern void __init versatile_map_io(void); 33extern void __init versatile_map_io(void);
@@ -37,10 +38,4 @@ extern unsigned int mmc_status(struct device *dev);
37extern struct of_dev_auxdata versatile_auxdata_lookup[]; 38extern struct of_dev_auxdata versatile_auxdata_lookup[];
38#endif 39#endif
39 40
40#define APB_DEVICE(name, busid, base, plat) \
41static AMBA_APB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
42
43#define AHB_DEVICE(name, busid, base, plat) \
44static AMBA_AHB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
45
46#endif 41#endif
diff --git a/arch/arm/mach-versatile/include/mach/clkdev.h b/arch/arm/mach-versatile/include/mach/clkdev.h
deleted file mode 100644
index e58d0771b64e..000000000000
--- a/arch/arm/mach-versatile/include/mach/clkdev.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#include <plat/clock.h>
5
6struct clk {
7 unsigned long rate;
8 const struct clk_ops *ops;
9 const struct icst_params *params;
10 void __iomem *vcoreg;
11};
12
13#define __clk_get(clk) ({ 1; })
14#define __clk_put(clk) do { } while (0)
15
16#endif
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
index 3e5d425e2a92..22a1158b7e27 100644
--- a/arch/arm/mach-versatile/include/mach/hardware.h
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -24,12 +24,6 @@
24 24
25#include <asm/sizes.h> 25#include <asm/sizes.h>
26 26
27/*
28 * PCI space virtual addresses
29 */
30#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul
31#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul
32
33/* macro to get at MMIO space when running virtually */ 27/* macro to get at MMIO space when running virtually */
34#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) 28#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
35 29
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h
deleted file mode 100644
index 0fd771ca617b..000000000000
--- a/arch/arm/mach-versatile/include/mach/irqs.h
+++ /dev/null
@@ -1,134 +0,0 @@
1/*
2 * arch/arm/mach-versatile/include/mach/irqs.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <mach/platform.h>
23
24/*
25 * IRQ interrupts definitions are the same as the INT definitions
26 * held within platform.h
27 */
28#define IRQ_VIC_START 32
29#define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT)
30#define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT)
31#define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx)
32#define IRQ_COMMTx (IRQ_VIC_START + INT_COMMTx)
33#define IRQ_TIMERINT0_1 (IRQ_VIC_START + INT_TIMERINT0_1)
34#define IRQ_TIMERINT2_3 (IRQ_VIC_START + INT_TIMERINT2_3)
35#define IRQ_GPIOINT0 (IRQ_VIC_START + INT_GPIOINT0)
36#define IRQ_GPIOINT1 (IRQ_VIC_START + INT_GPIOINT1)
37#define IRQ_GPIOINT2 (IRQ_VIC_START + INT_GPIOINT2)
38#define IRQ_GPIOINT3 (IRQ_VIC_START + INT_GPIOINT3)
39#define IRQ_RTCINT (IRQ_VIC_START + INT_RTCINT)
40#define IRQ_SSPINT (IRQ_VIC_START + INT_SSPINT)
41#define IRQ_UARTINT0 (IRQ_VIC_START + INT_UARTINT0)
42#define IRQ_UARTINT1 (IRQ_VIC_START + INT_UARTINT1)
43#define IRQ_UARTINT2 (IRQ_VIC_START + INT_UARTINT2)
44#define IRQ_SCIINT (IRQ_VIC_START + INT_SCIINT)
45#define IRQ_CLCDINT (IRQ_VIC_START + INT_CLCDINT)
46#define IRQ_DMAINT (IRQ_VIC_START + INT_DMAINT)
47#define IRQ_PWRFAILINT (IRQ_VIC_START + INT_PWRFAILINT)
48#define IRQ_MBXINT (IRQ_VIC_START + INT_MBXINT)
49#define IRQ_GNDINT (IRQ_VIC_START + INT_GNDINT)
50#define IRQ_VICSOURCE21 (IRQ_VIC_START + INT_VICSOURCE21)
51#define IRQ_VICSOURCE22 (IRQ_VIC_START + INT_VICSOURCE22)
52#define IRQ_VICSOURCE23 (IRQ_VIC_START + INT_VICSOURCE23)
53#define IRQ_VICSOURCE24 (IRQ_VIC_START + INT_VICSOURCE24)
54#define IRQ_VICSOURCE25 (IRQ_VIC_START + INT_VICSOURCE25)
55#define IRQ_VICSOURCE26 (IRQ_VIC_START + INT_VICSOURCE26)
56#define IRQ_VICSOURCE27 (IRQ_VIC_START + INT_VICSOURCE27)
57#define IRQ_VICSOURCE28 (IRQ_VIC_START + INT_VICSOURCE28)
58#define IRQ_VICSOURCE29 (IRQ_VIC_START + INT_VICSOURCE29)
59#define IRQ_VICSOURCE30 (IRQ_VIC_START + INT_VICSOURCE30)
60#define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31)
61#define IRQ_VIC_END (IRQ_VIC_START + 31)
62
63/*
64 * FIQ interrupts definitions are the same as the INT definitions.
65 */
66#define FIQ_WDOGINT INT_WDOGINT
67#define FIQ_SOFTINT INT_SOFTINT
68#define FIQ_COMMRx INT_COMMRx
69#define FIQ_COMMTx INT_COMMTx
70#define FIQ_TIMERINT0_1 INT_TIMERINT0_1
71#define FIQ_TIMERINT2_3 INT_TIMERINT2_3
72#define FIQ_GPIOINT0 INT_GPIOINT0
73#define FIQ_GPIOINT1 INT_GPIOINT1
74#define FIQ_GPIOINT2 INT_GPIOINT2
75#define FIQ_GPIOINT3 INT_GPIOINT3
76#define FIQ_RTCINT INT_RTCINT
77#define FIQ_SSPINT INT_SSPINT
78#define FIQ_UARTINT0 INT_UARTINT0
79#define FIQ_UARTINT1 INT_UARTINT1
80#define FIQ_UARTINT2 INT_UARTINT2
81#define FIQ_SCIINT INT_SCIINT
82#define FIQ_CLCDINT INT_CLCDINT
83#define FIQ_DMAINT INT_DMAINT
84#define FIQ_PWRFAILINT INT_PWRFAILINT
85#define FIQ_MBXINT INT_MBXINT
86#define FIQ_GNDINT INT_GNDINT
87#define FIQ_VICSOURCE21 INT_VICSOURCE21
88#define FIQ_VICSOURCE22 INT_VICSOURCE22
89#define FIQ_VICSOURCE23 INT_VICSOURCE23
90#define FIQ_VICSOURCE24 INT_VICSOURCE24
91#define FIQ_VICSOURCE25 INT_VICSOURCE25
92#define FIQ_VICSOURCE26 INT_VICSOURCE26
93#define FIQ_VICSOURCE27 INT_VICSOURCE27
94#define FIQ_VICSOURCE28 INT_VICSOURCE28
95#define FIQ_VICSOURCE29 INT_VICSOURCE29
96#define FIQ_VICSOURCE30 INT_VICSOURCE30
97#define FIQ_VICSOURCE31 INT_VICSOURCE31
98
99
100/*
101 * Secondary interrupt controller
102 */
103#define IRQ_SIC_START 64
104#define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B)
105#define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B)
106#define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0)
107#define IRQ_SIC_KMI1 (IRQ_SIC_START + SIC_INT_KMI1)
108#define IRQ_SIC_SCI3 (IRQ_SIC_START + SIC_INT_SCI3)
109#define IRQ_SIC_UART3 (IRQ_SIC_START + SIC_INT_UART3)
110#define IRQ_SIC_CLCD (IRQ_SIC_START + SIC_INT_CLCD)
111#define IRQ_SIC_TOUCH (IRQ_SIC_START + SIC_INT_TOUCH)
112#define IRQ_SIC_KEYPAD (IRQ_SIC_START + SIC_INT_KEYPAD)
113#define IRQ_SIC_DoC (IRQ_SIC_START + SIC_INT_DoC)
114#define IRQ_SIC_MMCI0A (IRQ_SIC_START + SIC_INT_MMCI0A)
115#define IRQ_SIC_MMCI1A (IRQ_SIC_START + SIC_INT_MMCI1A)
116#define IRQ_SIC_AACI (IRQ_SIC_START + SIC_INT_AACI)
117#define IRQ_SIC_ETH (IRQ_SIC_START + SIC_INT_ETH)
118#define IRQ_SIC_USB (IRQ_SIC_START + SIC_INT_USB)
119#define IRQ_SIC_PCI0 (IRQ_SIC_START + SIC_INT_PCI0)
120#define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1)
121#define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2)
122#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
123#define IRQ_SIC_END 95
124
125#define IRQ_GPIO0_START (IRQ_SIC_END + 1)
126#define IRQ_GPIO0_END (IRQ_GPIO0_START + 31)
127#define IRQ_GPIO1_START (IRQ_GPIO0_END + 1)
128#define IRQ_GPIO1_END (IRQ_GPIO1_START + 31)
129#define IRQ_GPIO2_START (IRQ_GPIO1_END + 1)
130#define IRQ_GPIO2_END (IRQ_GPIO2_START + 31)
131#define IRQ_GPIO3_START (IRQ_GPIO2_END + 1)
132#define IRQ_GPIO3_END (IRQ_GPIO3_START + 31)
133
134#define NR_IRQS (IRQ_GPIO3_END + 1)
diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h
index 6f938ccb0c54..7fe008bd1509 100644
--- a/arch/arm/mach-versatile/include/mach/platform.h
+++ b/arch/arm/mach-versatile/include/mach/platform.h
@@ -185,79 +185,13 @@
185/* 185/*
186 * VERSATILE peripheral addresses 186 * VERSATILE peripheral addresses
187 */ 187 */
188#define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */
189#define VERSATILE_I2C_BASE 0x10002000 /* I2C control */
190#define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */
191#define VERSATILE_AACI_BASE 0x10004000 /* Audio */
192#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */ 188#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
193#define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */
194#define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */
195#define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */
196#define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */
197#define VERSATILE_SCI1_BASE 0x1000A000
198#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */ 189#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
199 /* 0x1000C000 - 0x1000CFFF = reserved */
200#define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */
201#define VERSATILE_USB_BASE 0x10020000 /* USB */
202 /* 0x10030000 - 0x100FFFFF = reserved */
203#define VERSATILE_SMC_BASE 0x10100000 /* SMC */
204#define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */
205#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */ 190#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
206#define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */
207#define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */
208#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */
209 /* 0x10000000 - 0x100FFFFF */
210#define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */
211#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ 191#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
212#define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */
213#define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */
214#define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */
215#define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */
216#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */
217#define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */
218#define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */
219#define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */
220 /* 0x101E9000 - reserved */
221#define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */
222#define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */
223#define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */
224#define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */
225#define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */
226
227#define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */
228#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */ 192#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
229#define VERSATILE_MBX_BASE 0x40000000 /* MBX */
230
231/* PCI space */
232#define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */
233#define VERSATILE_PCI_CFG_BASE 0x42000000
234#define VERSATILE_PCI_IO_BASE 0x43000000
235#define VERSATILE_PCI_MEM_BASE0 0x44000000
236#define VERSATILE_PCI_MEM_BASE1 0x50000000
237#define VERSATILE_PCI_MEM_BASE2 0x60000000
238/* Sizes of above maps */
239#define VERSATILE_PCI_BASE_SIZE 0x01000000
240#define VERSATILE_PCI_CFG_BASE_SIZE 0x02000000
241#define VERSATILE_PCI_IO_BASE_SIZE 0x01000000
242#define VERSATILE_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
243#define VERSATILE_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
244#define VERSATILE_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
245
246#define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
247#define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */
248 193
249/* 194/*
250 * Disk on Chip
251 */
252#define VERSATILE_DOC_BASE 0x2C000000
253#define VERSATILE_DOC_SIZE (16 << 20)
254#define VERSATILE_DOC_PAGE_SIZE 512
255#define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
256
257#define ERASE_UNIT_PAGES 32
258#define START_PAGE 0x80
259
260/*
261 * LED settings, bits [7:0] 195 * LED settings, bits [7:0]
262 */ 196 */
263#define VERSATILE_SYS_LED0 (1 << 0) 197#define VERSATILE_SYS_LED0 (1 << 0)
@@ -281,106 +215,6 @@
281#define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */ 215#define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */
282#define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */ 216#define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */
283 217
284
285/* ------------------------------------------------------------------------
286 * Versatile Interrupt Controller - control registers
287 * ------------------------------------------------------------------------
288 *
289 * Offsets from interrupt controller base
290 *
291 * System Controller interrupt controller base is
292 *
293 * VERSATILE_IC_BASE
294 *
295 * Core Module interrupt controller base is
296 *
297 * VERSATILE_SYS_IC
298 *
299 */
300/* VIC definitions in include/asm-arm/hardware/vic.h */
301
302#define SIC_IRQ_STATUS 0
303#define SIC_IRQ_RAW_STATUS 0x04
304#define SIC_IRQ_ENABLE 0x08
305#define SIC_IRQ_ENABLE_SET 0x08
306#define SIC_IRQ_ENABLE_CLEAR 0x0C
307#define SIC_INT_SOFT_SET 0x10
308#define SIC_INT_SOFT_CLEAR 0x14
309#define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */
310#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */
311#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */
312
313/* ------------------------------------------------------------------------
314 * Interrupts - bit assignment (primary)
315 * ------------------------------------------------------------------------
316 */
317
318#define INT_WDOGINT 0 /* Watchdog timer */
319#define INT_SOFTINT 1 /* Software interrupt */
320#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
321#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
322#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
323#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
324#define INT_GPIOINT0 6 /* GPIO 0 */
325#define INT_GPIOINT1 7 /* GPIO 1 */
326#define INT_GPIOINT2 8 /* GPIO 2 */
327#define INT_GPIOINT3 9 /* GPIO 3 */
328#define INT_RTCINT 10 /* Real Time Clock */
329#define INT_SSPINT 11 /* Synchronous Serial Port */
330#define INT_UARTINT0 12 /* UART 0 on development chip */
331#define INT_UARTINT1 13 /* UART 1 on development chip */
332#define INT_UARTINT2 14 /* UART 2 on development chip */
333#define INT_SCIINT 15 /* Smart Card Interface */
334#define INT_CLCDINT 16 /* CLCD controller */
335#define INT_DMAINT 17 /* DMA controller */
336#define INT_PWRFAILINT 18 /* Power failure */
337#define INT_MBXINT 19 /* Graphics processor */
338#define INT_GNDINT 20 /* Reserved */
339 /* External interrupt signals from logic tiles or secondary controller */
340#define INT_VICSOURCE21 21 /* Disk on Chip */
341#define INT_VICSOURCE22 22 /* MCI0A */
342#define INT_VICSOURCE23 23 /* MCI1A */
343#define INT_VICSOURCE24 24 /* AACI */
344#define INT_VICSOURCE25 25 /* Ethernet */
345#define INT_VICSOURCE26 26 /* USB */
346#define INT_VICSOURCE27 27 /* PCI 0 */
347#define INT_VICSOURCE28 28 /* PCI 1 */
348#define INT_VICSOURCE29 29 /* PCI 2 */
349#define INT_VICSOURCE30 30 /* PCI 3 */
350#define INT_VICSOURCE31 31 /* SIC source */
351
352#define VERSATILE_SC_VALID_INT 0x003FFFFF
353
354#define MAXIRQNUM 31
355#define MAXFIQNUM 31
356#define MAXSWINUM 31
357
358/* ------------------------------------------------------------------------
359 * Interrupts - bit assignment (secondary)
360 * ------------------------------------------------------------------------
361 */
362#define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */
363#define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */
364#define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */
365#define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */
366#define SIC_INT_SCI3 5 /* Smart Card interface */
367#define SIC_INT_UART3 6 /* UART 3 empty or data available */
368#define SIC_INT_CLCD 7 /* Character LCD */
369#define SIC_INT_TOUCH 8 /* Touchscreen */
370#define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */
371 /* 10:20 - reserved */
372#define SIC_INT_DoC 21 /* Disk on Chip memory controller */
373#define SIC_INT_MMCI0A 22 /* MMC 0A */
374#define SIC_INT_MMCI1A 23 /* MMC 1A */
375#define SIC_INT_AACI 24 /* Audio Codec */
376#define SIC_INT_ETH 25 /* Ethernet controller */
377#define SIC_INT_USB 26 /* USB controller */
378#define SIC_INT_PCI0 27
379#define SIC_INT_PCI1 28
380#define SIC_INT_PCI2 29
381#define SIC_INT_PCI3 30
382
383
384/* 218/*
385 * System controller bit assignment 219 * System controller bit assignment
386 */ 220 */
@@ -393,16 +227,9 @@
393#define VERSATILE_TIMER4_EnSel 21 227#define VERSATILE_TIMER4_EnSel 21
394 228
395 229
396#define VERSATILE_CSR_BASE 0x10000000
397#define VERSATILE_CSR_SIZE 0x10000000
398
399#ifdef CONFIG_MACH_VERSATILE_AB
400/* 230/*
401 * IB2 Versatile/AB expansion board definitions 231 * IB2 Versatile/AB expansion board definitions
402 */ 232 */
403#define VERSATILE_IB2_CAMERA_BANK VERSATILE_IB2_BASE
404#define VERSATILE_IB2_KBD_DATAREG (VERSATILE_IB2_BASE + 0x01000000)
405
406/* VICINTSOURCE27 */ 233/* VICINTSOURCE27 */
407#define VERSATILE_IB2_INT_BASE (VERSATILE_IB2_BASE + 0x02000000) 234#define VERSATILE_IB2_INT_BASE (VERSATILE_IB2_BASE + 0x02000000)
408#define VERSATILE_IB2_IER (VERSATILE_IB2_INT_BASE + 0) 235#define VERSATILE_IB2_IER (VERSATILE_IB2_INT_BASE + 0)
@@ -411,6 +238,5 @@
411#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000) 238#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
412#define VERSATILE_IB2_CTRL (VERSATILE_IB2_CTL_BASE + 0) 239#define VERSATILE_IB2_CTRL (VERSATILE_IB2_CTL_BASE + 0)
413#define VERSATILE_IB2_STAT (VERSATILE_IB2_CTL_BASE + 4) 240#define VERSATILE_IB2_STAT (VERSATILE_IB2_CTL_BASE + 4)
414#endif
415 241
416#endif 242#endif
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
deleted file mode 100644
index c97be4ea76d2..000000000000
--- a/arch/arm/mach-versatile/pci.c
+++ /dev/null
@@ -1,368 +0,0 @@
1/*
2 * linux/arch/arm/mach-versatile/pci.c
3 *
4 * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
5 * You can redistribute and/or modify this software under the terms of version 2
6 * of the GNU General Public License as published by the Free Software Foundation.
7 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
8 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9 * General Public License for more details.
10 * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
11 *
12 * ARM Versatile PCI driver.
13 *
14 * 14/04/2005 Initial version, colin.king@philips.com
15 *
16 */
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/init.h>
23#include <linux/io.h>
24
25#include <mach/hardware.h>
26#include <mach/irqs.h>
27#include <asm/irq.h>
28#include <asm/mach/pci.h>
29
30/*
31 * these spaces are mapped using the following base registers:
32 *
33 * Usage Local Bus Memory Base/Map registers used
34 *
35 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
36 * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
37 * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
38 * Cfg 42000000 - 42FFFFFF PCI config
39 *
40 */
41#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
42#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
43#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
44#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
45#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
46#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
47#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
48#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x1c)
49#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
50
51#define DEVICE_ID_OFFSET 0x00
52#define CSR_OFFSET 0x04
53#define CLASS_ID_OFFSET 0x08
54
55#define VP_PCI_DEVICE_ID 0x030010ee
56#define VP_PCI_CLASS_ID 0x0b400000
57
58static unsigned long pci_slot_ignore = 0;
59
60static int __init versatile_pci_slot_ignore(char *str)
61{
62 int retval;
63 int slot;
64
65 while ((retval = get_option(&str,&slot))) {
66 if ((slot < 0) || (slot > 31)) {
67 printk("Illegal slot value: %d\n",slot);
68 } else {
69 pci_slot_ignore |= (1 << slot);
70 }
71 }
72 return 1;
73}
74
75__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
76
77
78static void __iomem *__pci_addr(struct pci_bus *bus,
79 unsigned int devfn, int offset)
80{
81 unsigned int busnr = bus->number;
82
83 /*
84 * Trap out illegal values
85 */
86 if (offset > 255)
87 BUG();
88 if (busnr > 255)
89 BUG();
90 if (devfn > 255)
91 BUG();
92
93 return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
94 (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
95}
96
97static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
98 int size, u32 *val)
99{
100 void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
101 u32 v;
102 int slot = PCI_SLOT(devfn);
103
104 if (pci_slot_ignore & (1 << slot)) {
105 /* Ignore this slot */
106 switch (size) {
107 case 1:
108 v = 0xff;
109 break;
110 case 2:
111 v = 0xffff;
112 break;
113 default:
114 v = 0xffffffff;
115 }
116 } else {
117 switch (size) {
118 case 1:
119 v = __raw_readl(addr);
120 if (where & 2) v >>= 16;
121 if (where & 1) v >>= 8;
122 v &= 0xff;
123 break;
124
125 case 2:
126 v = __raw_readl(addr);
127 if (where & 2) v >>= 16;
128 v &= 0xffff;
129 break;
130
131 default:
132 v = __raw_readl(addr);
133 break;
134 }
135 }
136
137 *val = v;
138 return PCIBIOS_SUCCESSFUL;
139}
140
141static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
142 int size, u32 val)
143{
144 void __iomem *addr = __pci_addr(bus, devfn, where);
145 int slot = PCI_SLOT(devfn);
146
147 if (pci_slot_ignore & (1 << slot)) {
148 return PCIBIOS_SUCCESSFUL;
149 }
150
151 switch (size) {
152 case 1:
153 __raw_writeb((u8)val, addr);
154 break;
155
156 case 2:
157 __raw_writew((u16)val, addr);
158 break;
159
160 case 4:
161 __raw_writel(val, addr);
162 break;
163 }
164
165 return PCIBIOS_SUCCESSFUL;
166}
167
168static struct pci_ops pci_versatile_ops = {
169 .read = versatile_read_config,
170 .write = versatile_write_config,
171};
172
173static struct resource unused_mem = {
174 .name = "PCI unused",
175 .start = VERSATILE_PCI_MEM_BASE0,
176 .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
177 .flags = IORESOURCE_MEM,
178};
179
180static struct resource non_mem = {
181 .name = "PCI non-prefetchable",
182 .start = VERSATILE_PCI_MEM_BASE1,
183 .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
184 .flags = IORESOURCE_MEM,
185};
186
187static struct resource pre_mem = {
188 .name = "PCI prefetchable",
189 .start = VERSATILE_PCI_MEM_BASE2,
190 .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
191 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
192};
193
194static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
195{
196 int ret = 0;
197
198 ret = request_resource(&iomem_resource, &unused_mem);
199 if (ret) {
200 printk(KERN_ERR "PCI: unable to allocate unused "
201 "memory region (%d)\n", ret);
202 goto out;
203 }
204 ret = request_resource(&iomem_resource, &non_mem);
205 if (ret) {
206 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
207 "memory region (%d)\n", ret);
208 goto release_unused_mem;
209 }
210 ret = request_resource(&iomem_resource, &pre_mem);
211 if (ret) {
212 printk(KERN_ERR "PCI: unable to allocate prefetchable "
213 "memory region (%d)\n", ret);
214 goto release_non_mem;
215 }
216
217 /*
218 * the mem resource for this bus
219 * the prefetch mem resource for this bus
220 */
221 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
222 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
223
224 goto out;
225
226 release_non_mem:
227 release_resource(&non_mem);
228 release_unused_mem:
229 release_resource(&unused_mem);
230 out:
231 return ret;
232}
233
234int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
235{
236 int ret = 0;
237 int i;
238 int myslot = -1;
239 unsigned long val;
240 void __iomem *local_pci_cfg_base;
241
242 val = __raw_readl(SYS_PCICTL);
243 if (!(val & 1)) {
244 printk("Not plugged into PCI backplane!\n");
245 ret = -EIO;
246 goto out;
247 }
248
249 ret = pci_ioremap_io(0, VERSATILE_PCI_IO_BASE);
250 if (ret)
251 goto out;
252
253 if (nr == 0) {
254 ret = pci_versatile_setup_resources(sys);
255 if (ret < 0) {
256 printk("pci_versatile_setup: resources... oops?\n");
257 goto out;
258 }
259 } else {
260 printk("pci_versatile_setup: resources... nr == 0??\n");
261 goto out;
262 }
263
264 /*
265 * We need to discover the PCI core first to configure itself
266 * before the main PCI probing is performed
267 */
268 for (i=0; i<32; i++)
269 if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
270 (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
271 myslot = i;
272 break;
273 }
274
275 if (myslot == -1) {
276 printk("Cannot find PCI core!\n");
277 ret = -EIO;
278 goto out;
279 }
280
281 printk("PCI core found (slot %d)\n",myslot);
282
283 __raw_writel(myslot, PCI_SELFID);
284 local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
285
286 val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
287 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
288 __raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
289
290 /*
291 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
292 */
293 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
294 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
295 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
296
297 /*
298 * For many years the kernel and QEMU were symbiotically buggy
299 * in that they both assumed the same broken IRQ mapping.
300 * QEMU therefore attempts to auto-detect old broken kernels
301 * so that they still work on newer QEMU as they did on old
302 * QEMU. Since we now use the correct (ie matching-hardware)
303 * IRQ mapping we write a definitely different value to a
304 * PCI_INTERRUPT_LINE register to tell QEMU that we expect
305 * real hardware behaviour and it need not be backwards
306 * compatible for us. This write is harmless on real hardware.
307 */
308 __raw_writel(0, VERSATILE_PCI_VIRT_BASE+PCI_INTERRUPT_LINE);
309
310 /*
311 * Do not to map Versatile FPGA PCI device into memory space
312 */
313 pci_slot_ignore |= (1 << myslot);
314 ret = 1;
315
316 out:
317 return ret;
318}
319
320
321void __init pci_versatile_preinit(void)
322{
323 pcibios_min_mem = 0x50000000;
324
325 __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
326 __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
327 __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
328
329 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
330 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
331 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
332
333 __raw_writel(1, SYS_PCICTL);
334}
335
336/*
337 * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
338 */
339static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
340{
341 int irq;
342
343 /*
344 * Slot INTA INTB INTC INTD
345 * 31 PCI1 PCI2 PCI3 PCI0
346 * 30 PCI0 PCI1 PCI2 PCI3
347 * 29 PCI3 PCI0 PCI1 PCI2
348 */
349 irq = IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3);
350
351 return irq;
352}
353
354static struct hw_pci versatile_pci __initdata = {
355 .map_irq = versatile_map_irq,
356 .nr_controllers = 1,
357 .ops = &pci_versatile_ops,
358 .setup = pci_versatile_setup,
359 .preinit = pci_versatile_preinit,
360};
361
362static int __init versatile_pci_init(void)
363{
364 pci_common_init(&versatile_pci);
365 return 0;
366}
367
368subsys_initcall(versatile_pci_init);
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
deleted file mode 100644
index 1caef1093793..000000000000
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * linux/arch/arm/mach-versatile/versatile_ab.c
3 *
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/device.h>
24#include <linux/amba/bus.h>
25#include <linux/io.h>
26
27#include <mach/hardware.h>
28#include <asm/irq.h>
29#include <asm/mach-types.h>
30
31#include <asm/mach/arch.h>
32
33#include "core.h"
34
35MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
36 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
37 .atag_offset = 0x100,
38 .map_io = versatile_map_io,
39 .init_early = versatile_init_early,
40 .init_irq = versatile_init_irq,
41 .init_time = versatile_timer_init,
42 .init_machine = versatile_init,
43 .restart = versatile_restart,
44MACHINE_END
diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c
index a58575832fa3..86fa2d35a019 100644
--- a/arch/arm/mach-versatile/versatile_dt.c
+++ b/arch/arm/mach-versatile/versatile_dt.c
@@ -81,6 +81,7 @@ static void __init versatile_dt_init(void)
81 81
82 versatile_dt_pci_init(); 82 versatile_dt_pci_init();
83 83
84 platform_device_register(&versatile_flash_device);
84 of_platform_populate(NULL, of_default_bus_match_table, 85 of_platform_populate(NULL, of_default_bus_match_table,
85 versatile_auxdata_lookup, NULL); 86 versatile_auxdata_lookup, NULL);
86} 87}
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
deleted file mode 100644
index 9a53d0bd9144..000000000000
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * linux/arch/arm/mach-versatile/versatile_pb.c
3 *
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/device.h>
24#include <linux/amba/bus.h>
25#include <linux/amba/pl061.h>
26#include <linux/amba/mmci.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31#include <asm/mach-types.h>
32
33#include <asm/mach/arch.h>
34
35#include "core.h"
36
37#if 1
38#define IRQ_MMCI1A IRQ_VICSOURCE23
39#else
40#define IRQ_MMCI1A IRQ_SIC_MMCI1A
41#endif
42
43static struct mmci_platform_data mmc1_plat_data = {
44 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
45 .status = mmc_status,
46 .gpio_wp = -1,
47 .gpio_cd = -1,
48};
49
50#define UART3_IRQ { IRQ_SIC_UART3 }
51#define SCI1_IRQ { IRQ_SIC_SCI3 }
52#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
53
54/*
55 * These devices are connected via the DMA APB bridge
56 */
57
58/* FPGA Primecells */
59APB_DEVICE(uart3, "fpga:09", UART3, NULL);
60APB_DEVICE(sci1, "fpga:0a", SCI1, NULL);
61APB_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data);
62
63
64static struct amba_device *amba_devs[] __initdata = {
65 &uart3_device,
66 &sci1_device,
67 &mmc1_device,
68};
69
70static void __init versatile_pb_init(void)
71{
72 int i;
73
74 versatile_init();
75
76 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
77 struct amba_device *d = amba_devs[i];
78 amba_device_register(d, &iomem_resource);
79 }
80}
81
82MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
83 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
84 .atag_offset = 0x100,
85 .map_io = versatile_map_io,
86 .init_early = versatile_init_early,
87 .init_irq = versatile_init_irq,
88 .init_time = versatile_timer_init,
89 .init_machine = versatile_pb_init,
90 .restart = versatile_restart,
91MACHINE_END
diff --git a/drivers/clk/versatile/Kconfig b/drivers/clk/versatile/Kconfig
index fc50b6264bed..369a2dc50f74 100644
--- a/drivers/clk/versatile/Kconfig
+++ b/drivers/clk/versatile/Kconfig
@@ -1,6 +1,8 @@
1config COMMON_CLK_VERSATILE 1config COMMON_CLK_VERSATILE
2 bool "Clock driver for ARM Reference designs" 2 bool "Clock driver for ARM Reference designs"
3 depends on ARCH_INTEGRATOR || ARCH_REALVIEW || ARCH_VEXPRESS || ARM64 || COMPILE_TEST 3 depends on ARCH_INTEGRATOR || ARCH_REALVIEW || \
4 ARCH_VERSATILE || ARCH_VEXPRESS || ARM64 || \
5 COMPILE_TEST
4 ---help--- 6 ---help---
5 Supports clocking on ARM Reference designs: 7 Supports clocking on ARM Reference designs:
6 - Integrator/AP and Integrator/CP 8 - Integrator/AP and Integrator/CP
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 08:28:54 -0400