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authorAlex Deucher <alexander.deucher@amd.com>2015-11-11 20:18:52 -0500
committerAlex Deucher <alexander.deucher@amd.com>2015-12-21 16:42:30 -0500
commit16881da6c0b9db5fca95b96b0f02720e94c92629 (patch)
treee8d219593c42cbad730938bd66f4151c4aa1e695
parent74c577b0313d4140ec8b61745c6ade3a4d735d33 (diff)
drm/amdgpu: extract pcie helpers to common header
These will be used by multiple powerplay drivers and other IP modules. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/include/amd_pcie.h50
-rw-r--r--drivers/gpu/drm/amd/include/amd_pcie_helpers.h141
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c1
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c112
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h24
6 files changed, 193 insertions, 137 deletions
diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
new file mode 100644
index 000000000000..7c2a916c1e63
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/amd_pcie.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_PCIE_H__
24#define __AMD_PCIE_H__
25
26/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
27#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
28#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
29#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
30#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
31#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
32
33/* Following flags shows PCIe link speed supported by ASIC H/W.*/
34#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
35#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
36#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
37#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
38#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
39
40/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
41#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000
42#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000
43#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000
44#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000
45#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000
46#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000
47#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000
48#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16
49
50#endif
diff --git a/drivers/gpu/drm/amd/include/amd_pcie_helpers.h b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h
new file mode 100644
index 000000000000..2cfdf054953b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h
@@ -0,0 +1,141 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_PCIE_HELPERS_H__
24#define __AMD_PCIE_HELPERS_H__
25
26#include "amd_pcie.h"
27
28static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
29{
30 if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
31 return 1;
32
33 return 0;
34}
35
36static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
37{
38 if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
39 return 1;
40
41 return 0;
42}
43
44/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
45static inline uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap,
46 uint16_t ns_pcie_gen)
47{
48 uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
49 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
50 uint32_t sys_pcie_link_speed_cap = (pcie_link_speed_cap &
51 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
52
53 switch (asic_pcie_link_speed_cap) {
54 case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
55 return PP_PCIEGen1;
56
57 case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
58 return PP_PCIEGen2;
59
60 case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
61 return PP_PCIEGen3;
62
63 default:
64 if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
65 (ns_pcie_gen == PP_PCIEGen3)) {
66 return PP_PCIEGen3;
67 } else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
68 ((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
69 return PP_PCIEGen2;
70 }
71 }
72
73 return PP_PCIEGen1;
74}
75
76static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap,
77 uint16_t ns_pcie_lanes)
78{
79 int i, j;
80 uint16_t new_pcie_lanes = ns_pcie_lanes;
81 uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
82
83 switch (pcie_lane_width_cap) {
84 case 0:
85 printk(KERN_ERR "No valid PCIE lane width reported");
86 break;
87 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
88 new_pcie_lanes = 1;
89 break;
90 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
91 new_pcie_lanes = 2;
92 break;
93 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
94 new_pcie_lanes = 4;
95 break;
96 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
97 new_pcie_lanes = 8;
98 break;
99 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
100 new_pcie_lanes = 12;
101 break;
102 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
103 new_pcie_lanes = 16;
104 break;
105 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
106 new_pcie_lanes = 32;
107 break;
108 default:
109 for (i = 0; i < 7; i++) {
110 if (ns_pcie_lanes == pcie_lanes[i]) {
111 if (pcie_lane_width_cap & (0x10000 << i)) {
112 break;
113 } else {
114 for (j = i - 1; j >= 0; j--) {
115 if (pcie_lane_width_cap & (0x10000 << j)) {
116 new_pcie_lanes = pcie_lanes[j];
117 break;
118 }
119 }
120
121 if (j < 0) {
122 for (j = i + 1; j < 7; j++) {
123 if (pcie_lane_width_cap & (0x10000 << j)) {
124 new_pcie_lanes = pcie_lanes[j];
125 break;
126 }
127 }
128 if (j > 7)
129 printk(KERN_ERR "Cannot find a valid PCIE lane width!");
130 }
131 }
132 break;
133 }
134 }
135 break;
136 }
137
138 return new_pcie_lanes;
139}
140
141#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index adcc2f097999..ccbdbef50e1d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -49,6 +49,7 @@
49#include "tonga_pptable.h" 49#include "tonga_pptable.h"
50#include "pp_debug.h" 50#include "pp_debug.h"
51#include "pp_acpi.h" 51#include "pp_acpi.h"
52#include "amd_pcie_helpers.h"
52 53
53#define VOLTAGE_SCALE 4 54#define VOLTAGE_SCALE 4
54#define SMC_RAM_END 0x40000 55#define SMC_RAM_END 0x40000
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
index 38dbe498394b..22d985e2c63a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
@@ -339,8 +339,6 @@ enum Fiji_I2CLineID {
339extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); 339extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
340extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); 340extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
341extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr); 341extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
342extern uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen);
343extern uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes);
344 342
345#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X) 343#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
346#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X) 344#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index a9cc7868ca14..9442313d7557 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -53,6 +53,7 @@
53 53
54#include "cgs_linux.h" 54#include "cgs_linux.h"
55#include "eventmgr.h" 55#include "eventmgr.h"
56#include "amd_pcie_helpers.h"
56 57
57#define MC_CG_ARB_FREQ_F0 0x0a 58#define MC_CG_ARB_FREQ_F0 0x0a
58#define MC_CG_ARB_FREQ_F1 0x0b 59#define MC_CG_ARB_FREQ_F1 0x0b
@@ -2651,117 +2652,6 @@ static void tonga_setup_pcie_table_entry(
2651 dpm_table->dpm_levels[index].enabled = 1; 2652 dpm_table->dpm_levels[index].enabled = 1;
2652} 2653}
2653 2654
2654bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
2655{
2656 if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2657 return 1;
2658
2659 return 0;
2660}
2661
2662bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
2663{
2664 if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
2665 return 1;
2666
2667 return 0;
2668}
2669
2670/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
2671uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen)
2672{
2673 uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
2674 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
2675 uint32_t sys_pcie_link_speed_cap = (pcie_link_speed_cap &
2676 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
2677
2678 switch (asic_pcie_link_speed_cap) {
2679 case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
2680 return PP_PCIEGen1;
2681
2682 case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
2683 return PP_PCIEGen2;
2684
2685 case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
2686 return PP_PCIEGen3;
2687
2688 default:
2689 if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
2690 (ns_pcie_gen == PP_PCIEGen3)) {
2691 return PP_PCIEGen3;
2692 } else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
2693 ((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
2694 return PP_PCIEGen2;
2695 }
2696 }
2697
2698 return PP_PCIEGen1;
2699}
2700
2701uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes)
2702{
2703 int i, j;
2704 uint16_t new_pcie_lanes = ns_pcie_lanes;
2705 uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
2706
2707 switch (pcie_lane_width_cap) {
2708 case 0:
2709 printk(KERN_ERR "[ powerplay ] No valid PCIE lane width reported by CAIL!");
2710 break;
2711 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
2712 new_pcie_lanes = 1;
2713 break;
2714 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
2715 new_pcie_lanes = 2;
2716 break;
2717 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
2718 new_pcie_lanes = 4;
2719 break;
2720 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
2721 new_pcie_lanes = 8;
2722 break;
2723 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
2724 new_pcie_lanes = 12;
2725 break;
2726 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
2727 new_pcie_lanes = 16;
2728 break;
2729 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
2730 new_pcie_lanes = 32;
2731 break;
2732 default:
2733 for (i = 0; i < 7; i++) {
2734 if (ns_pcie_lanes == pcie_lanes[i]) {
2735 if (pcie_lane_width_cap & (0x10000 << i)) {
2736 break;
2737 } else {
2738 for (j = i - 1; j >= 0; j--) {
2739 if (pcie_lane_width_cap & (0x10000 << j)) {
2740 new_pcie_lanes = pcie_lanes[j];
2741 break;
2742 }
2743 }
2744
2745 if (j < 0) {
2746 for (j = i + 1; j < 7; j++) {
2747 if (pcie_lane_width_cap & (0x10000 << j)) {
2748 new_pcie_lanes = pcie_lanes[j];
2749 break;
2750 }
2751 }
2752 if (j > 7)
2753 printk(KERN_ERR "[ powerplay ] Cannot find a valid PCIE lane width!");
2754 }
2755 }
2756 break;
2757 }
2758 }
2759 break;
2760 }
2761
2762 return new_pcie_lanes;
2763}
2764
2765static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr) 2655static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
2766{ 2656{
2767 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); 2657 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
index 44b985a92bb4..49168d262ccc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
@@ -386,30 +386,6 @@ typedef struct tonga_hwmgr tonga_hwmgr;
386 386
387#define TONGA_UNUSED_GPIO_PIN 0x7F 387#define TONGA_UNUSED_GPIO_PIN 0x7F
388 388
389/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
390#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
391#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
392#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
393#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
394#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
395
396/* Following flags shows PCIe link speed supported by ASIC H/W.*/
397#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
398#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
399#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
400#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
401#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
402
403/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
404#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000
405#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000
406#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000
407#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000
408#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000
409#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000
410#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000
411#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16
412
413#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X) 389#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
414#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X) 390#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
415 391
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 18:34:09 -0400