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authorDave Airlie <airlied@redhat.com>2016-07-27 15:51:39 -0400
committerDave Airlie <airlied@redhat.com>2016-07-27 15:51:39 -0400
commit162b20d2f9ef9dfa833cc329b1e8957beb672349 (patch)
tree5d043eae378bfb89d6bb9b2018c28537aa28387a
parentc3f8d8645ea56e57cbd35ea20a7655be512efaa9 (diff)
parent5ef8292925047ad290205af5f3ae13d0a36d774d (diff)
Merge branch 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few more patches for 4.8. Mostly bug fixes and some prep work for iceland powerplay support. I have a couple polaris patches and Edward's misc cleanups that require a merge with Linus'. I don't know if you are planning a merge anytime soon. [airlied: fixed up endian vs 32-bit change in ppatomctrl] * 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux: (26 commits) drm/amdgpu: comment out unused defaults_bonaire_pro static const structures to fix the build drm/amdgpu: temporary comment out unused static const structures to fix the build drm/amdgpu: S3 resume fail on Polaris10 drm/amd/powerplay: add pp_tables_get_response_times function in process pptables drm/amd/powerplay: fix the incorrect return value drm/amd/powerplay: add atomctrl_get_voltage_evv function in ppatomctrl drm/amdgpu: add new definitions into ppsmc.h for iceland drm/amd/powerplay: add SMU register macro for future use drm/amdgpu: add ucode_start_address into cgs_firmware_info drm/amdgpu: no need load microcode at sdma if powerplay is enabled drm/amdgpu: rename smumgr to smum for dpm drm/amdgpu: disable GFX PG on CZ/BR/ST drivers: gpu: drm: amd: powerplay: hwmgr: Remove unused variable drm/amdgpu: return -ENOSPC when running out of UVD handles drm/amdgpu: trace need_flush in grab_vm as well drm/amdgpu: always signal all fences drm/amdgpu: check flush fence context instead of same ring v2 drm/radeon: support backlight control for UNIPHY3 drm/amdgpu: support backlight control for UNIPHY3 drm/amdgpu: remove usec timeout loop from IB tests ...
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c17
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_job.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c104
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c13
-rw-r--r--drivers/gpu/drm/amd/amdgpu/atombios_encoders.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_dpm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_smc.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_smum.h (renamed from drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h)0
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ppsmc.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c43
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c143
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c14
-rw-r--r--drivers/gpu/drm/amd/include/cgs_common.h4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c9
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c299
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c13
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h17
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smumgr.h29
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c1
30 files changed, 469 insertions, 360 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 5556ce979199..ee95e950a19b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -752,6 +752,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
752 752
753 if (!adev->pm.fw) { 753 if (!adev->pm.fw) {
754 switch (adev->asic_type) { 754 switch (adev->asic_type) {
755 case CHIP_TOPAZ:
756 strcpy(fw_name, "amdgpu/topaz_smc.bin");
757 break;
755 case CHIP_TONGA: 758 case CHIP_TONGA:
756 strcpy(fw_name, "amdgpu/tonga_smc.bin"); 759 strcpy(fw_name, "amdgpu/tonga_smc.bin");
757 break; 760 break;
@@ -800,6 +803,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
800 803
801 info->version = adev->pm.fw_version; 804 info->version = adev->pm.fw_version;
802 info->image_size = ucode_size; 805 info->image_size = ucode_size;
806 info->ucode_start_address = ucode_start_address;
803 info->kptr = (void *)src; 807 info->kptr = (void *)src;
804 } 808 }
805 return 0; 809 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index d1558768cfb7..0b109aebfec6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -204,16 +204,25 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
204 if (seq != ring->fence_drv.sync_seq) 204 if (seq != ring->fence_drv.sync_seq)
205 amdgpu_fence_schedule_fallback(ring); 205 amdgpu_fence_schedule_fallback(ring);
206 206
207 while (last_seq != seq) { 207 if (unlikely(seq == last_seq))
208 return;
209
210 last_seq &= drv->num_fences_mask;
211 seq &= drv->num_fences_mask;
212
213 do {
208 struct fence *fence, **ptr; 214 struct fence *fence, **ptr;
209 215
210 ptr = &drv->fences[++last_seq & drv->num_fences_mask]; 216 ++last_seq;
217 last_seq &= drv->num_fences_mask;
218 ptr = &drv->fences[last_seq];
211 219
212 /* There is always exactly one thread signaling this fence slot */ 220 /* There is always exactly one thread signaling this fence slot */
213 fence = rcu_dereference_protected(*ptr, 1); 221 fence = rcu_dereference_protected(*ptr, 1);
214 RCU_INIT_POINTER(*ptr, NULL); 222 RCU_INIT_POINTER(*ptr, NULL);
215 223
216 BUG_ON(!fence); 224 if (!fence)
225 continue;
217 226
218 r = fence_signal(fence); 227 r = fence_signal(fence);
219 if (!r) 228 if (!r)
@@ -222,7 +231,7 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
222 BUG(); 231 BUG();
223 232
224 fence_put(fence); 233 fence_put(fence);
225 } 234 } while (last_seq != seq);
226} 235}
227 236
228/** 237/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 46c3097c5224..428ebf3a4387 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -122,7 +122,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
122 bool skip_preamble, need_ctx_switch; 122 bool skip_preamble, need_ctx_switch;
123 unsigned patch_offset = ~0; 123 unsigned patch_offset = ~0;
124 struct amdgpu_vm *vm; 124 struct amdgpu_vm *vm;
125 struct fence *hwf;
126 uint64_t ctx; 125 uint64_t ctx;
127 126
128 unsigned i; 127 unsigned i;
@@ -190,7 +189,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
190 if (ring->funcs->emit_hdp_invalidate) 189 if (ring->funcs->emit_hdp_invalidate)
191 amdgpu_ring_emit_hdp_invalidate(ring); 190 amdgpu_ring_emit_hdp_invalidate(ring);
192 191
193 r = amdgpu_fence_emit(ring, &hwf); 192 r = amdgpu_fence_emit(ring, f);
194 if (r) { 193 if (r) {
195 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 194 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
196 if (job && job->vm_id) 195 if (job && job->vm_id)
@@ -205,9 +204,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
205 AMDGPU_FENCE_FLAG_64BIT); 204 AMDGPU_FENCE_FLAG_64BIT);
206 } 205 }
207 206
208 if (f)
209 *f = fence_get(hwf);
210
211 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 207 if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
212 amdgpu_ring_patch_cond_exec(ring, patch_offset); 208 amdgpu_ring_patch_cond_exec(ring, patch_offset);
213 209
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index aaee0c8f6731..6674d40eb3ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -172,15 +172,13 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
172 trace_amdgpu_sched_run_job(job); 172 trace_amdgpu_sched_run_job(job);
173 r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, 173 r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
174 job->sync.last_vm_update, job, &fence); 174 job->sync.last_vm_update, job, &fence);
175 if (r) { 175 if (r)
176 DRM_ERROR("Error scheduling IBs (%d)\n", r); 176 DRM_ERROR("Error scheduling IBs (%d)\n", r);
177 goto err;
178 }
179 177
180err:
181 /* if gpu reset, hw fence will be replaced here */ 178 /* if gpu reset, hw fence will be replaced here */
182 fence_put(job->fence); 179 fence_put(job->fence);
183 job->fence = fence; 180 job->fence = fence_get(fence);
181 amdgpu_job_free_resources(job);
184 return fence; 182 return fence;
185} 183}
186 184
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 499803f3ce3a..0d8d65eb46cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -149,24 +149,26 @@ TRACE_EVENT(amdgpu_sched_run_job,
149 149
150 150
151TRACE_EVENT(amdgpu_vm_grab_id, 151TRACE_EVENT(amdgpu_vm_grab_id,
152 TP_PROTO(struct amdgpu_vm *vm, int ring, unsigned vmid, 152 TP_PROTO(struct amdgpu_vm *vm, int ring, struct amdgpu_job *job),
153 uint64_t pd_addr), 153 TP_ARGS(vm, ring, job),
154 TP_ARGS(vm, ring, vmid, pd_addr),
155 TP_STRUCT__entry( 154 TP_STRUCT__entry(
156 __field(struct amdgpu_vm *, vm) 155 __field(struct amdgpu_vm *, vm)
157 __field(u32, ring) 156 __field(u32, ring)
158 __field(u32, vmid) 157 __field(u32, vmid)
159 __field(u64, pd_addr) 158 __field(u64, pd_addr)
159 __field(u32, needs_flush)
160 ), 160 ),
161 161
162 TP_fast_assign( 162 TP_fast_assign(
163 __entry->vm = vm; 163 __entry->vm = vm;
164 __entry->ring = ring; 164 __entry->ring = ring;
165 __entry->vmid = vmid; 165 __entry->vmid = job->vm_id;
166 __entry->pd_addr = pd_addr; 166 __entry->pd_addr = job->vm_pd_addr;
167 __entry->needs_flush = job->vm_needs_flush;
167 ), 168 ),
168 TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx", __entry->vm, 169 TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx needs_flush=%u",
169 __entry->ring, __entry->vmid, __entry->pd_addr) 170 __entry->vm, __entry->ring, __entry->vmid,
171 __entry->pd_addr, __entry->needs_flush)
170); 172);
171 173
172TRACE_EVENT(amdgpu_vm_bo_map, 174TRACE_EVENT(amdgpu_vm_bo_map,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index d9c88d13f8db..a46a64c125d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -40,7 +40,7 @@
40#include "uvd/uvd_4_2_d.h" 40#include "uvd/uvd_4_2_d.h"
41 41
42/* 1 second timeout */ 42/* 1 second timeout */
43#define UVD_IDLE_TIMEOUT_MS 1000 43#define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
44/* Polaris10/11 firmware version */ 44/* Polaris10/11 firmware version */
45#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 45#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
46 46
@@ -662,7 +662,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
662 } 662 }
663 663
664 DRM_ERROR("No more free UVD handles!\n"); 664 DRM_ERROR("No more free UVD handles!\n");
665 return -EINVAL; 665 return -ENOSPC;
666 666
667 case 1: 667 case 1:
668 /* it's a decode msg, calc buffer sizes */ 668 /* it's a decode msg, calc buffer sizes */
@@ -968,7 +968,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
968 968
969 if (direct) { 969 if (direct) {
970 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); 970 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
971 job->fence = f; 971 job->fence = fence_get(f);
972 if (r) 972 if (r)
973 goto err_free; 973 goto err_free;
974 974
@@ -1114,8 +1114,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1114 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1114 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1115 } 1115 }
1116 } else { 1116 } else {
1117 schedule_delayed_work(&adev->uvd.idle_work, 1117 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1118 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1119 } 1118 }
1120} 1119}
1121 1120
@@ -1123,7 +1122,7 @@ static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
1123{ 1122{
1124 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1123 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1125 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work, 1124 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1126 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 1125 UVD_IDLE_TIMEOUT);
1127 1126
1128 if (set_clocks) { 1127 if (set_clocks) {
1129 if (adev->pm.dpm_enabled) { 1128 if (adev->pm.dpm_enabled) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 875626a2eccb..aeeeb72ebbc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -36,7 +36,7 @@
36#include "cikd.h" 36#include "cikd.h"
37 37
38/* 1 second timeout */ 38/* 1 second timeout */
39#define VCE_IDLE_TIMEOUT_MS 1000 39#define VCE_IDLE_TIMEOUT msecs_to_jiffies(1000)
40 40
41/* Firmware Names */ 41/* Firmware Names */
42#ifdef CONFIG_DRM_AMDGPU_CIK 42#ifdef CONFIG_DRM_AMDGPU_CIK
@@ -310,8 +310,7 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work)
310 amdgpu_asic_set_vce_clocks(adev, 0, 0); 310 amdgpu_asic_set_vce_clocks(adev, 0, 0);
311 } 311 }
312 } else { 312 } else {
313 schedule_delayed_work(&adev->vce.idle_work, 313 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
314 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
315 } 314 }
316} 315}
317 316
@@ -324,17 +323,12 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work)
324 */ 323 */
325static void amdgpu_vce_note_usage(struct amdgpu_device *adev) 324static void amdgpu_vce_note_usage(struct amdgpu_device *adev)
326{ 325{
327 bool streams_changed = false;
328 bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work); 326 bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
329 set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
330 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
331 327
332 if (adev->pm.dpm_enabled) { 328 set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
333 /* XXX figure out if the streams changed */ 329 VCE_IDLE_TIMEOUT);
334 streams_changed = false;
335 }
336 330
337 if (set_clocks || streams_changed) { 331 if (set_clocks) {
338 if (adev->pm.dpm_enabled) { 332 if (adev->pm.dpm_enabled) {
339 amdgpu_dpm_enable_vce(adev, true); 333 amdgpu_dpm_enable_vce(adev, true);
340 } else { 334 } else {
@@ -357,6 +351,7 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
357 int i, r; 351 int i, r;
358 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { 352 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
359 uint32_t handle = atomic_read(&adev->vce.handles[i]); 353 uint32_t handle = atomic_read(&adev->vce.handles[i]);
354
360 if (!handle || adev->vce.filp[i] != filp) 355 if (!handle || adev->vce.filp[i] != filp)
361 continue; 356 continue;
362 357
@@ -437,7 +432,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
437 ib->ptr[i] = 0x0; 432 ib->ptr[i] = 0x0;
438 433
439 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); 434 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
440 job->fence = f; 435 job->fence = fence_get(f);
441 if (r) 436 if (r)
442 goto err; 437 goto err;
443 438
@@ -499,7 +494,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
499 494
500 if (direct) { 495 if (direct) {
501 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); 496 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
502 job->fence = f; 497 job->fence = fence_get(f);
503 if (r) 498 if (r)
504 goto err; 499 goto err;
505 500
@@ -580,12 +575,10 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
580 * we we don't have another free session index. 575 * we we don't have another free session index.
581 */ 576 */
582static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p, 577static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
583 uint32_t handle, bool *allocated) 578 uint32_t handle, uint32_t *allocated)
584{ 579{
585 unsigned i; 580 unsigned i;
586 581
587 *allocated = false;
588
589 /* validate the handle */ 582 /* validate the handle */
590 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { 583 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
591 if (atomic_read(&p->adev->vce.handles[i]) == handle) { 584 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
@@ -602,7 +595,7 @@ static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
602 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) { 595 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
603 p->adev->vce.filp[i] = p->filp; 596 p->adev->vce.filp[i] = p->filp;
604 p->adev->vce.img_size[i] = 0; 597 p->adev->vce.img_size[i] = 0;
605 *allocated = true; 598 *allocated |= 1 << i;
606 return i; 599 return i;
607 } 600 }
608 } 601 }
@@ -622,9 +615,9 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
622 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 615 struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
623 unsigned fb_idx = 0, bs_idx = 0; 616 unsigned fb_idx = 0, bs_idx = 0;
624 int session_idx = -1; 617 int session_idx = -1;
625 bool destroyed = false; 618 uint32_t destroyed = 0;
626 bool created = false; 619 uint32_t created = 0;
627 bool allocated = false; 620 uint32_t allocated = 0;
628 uint32_t tmp, handle = 0; 621 uint32_t tmp, handle = 0;
629 uint32_t *size = &tmp; 622 uint32_t *size = &tmp;
630 int i, r = 0, idx = 0; 623 int i, r = 0, idx = 0;
@@ -641,30 +634,30 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
641 goto out; 634 goto out;
642 } 635 }
643 636
644 if (destroyed) {
645 DRM_ERROR("No other command allowed after destroy!\n");
646 r = -EINVAL;
647 goto out;
648 }
649
650 switch (cmd) { 637 switch (cmd) {
651 case 0x00000001: // session 638 case 0x00000001: /* session */
652 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2); 639 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
653 session_idx = amdgpu_vce_validate_handle(p, handle, 640 session_idx = amdgpu_vce_validate_handle(p, handle,
654 &allocated); 641 &allocated);
655 if (session_idx < 0) 642 if (session_idx < 0) {
656 return session_idx; 643 r = session_idx;
644 goto out;
645 }
657 size = &p->adev->vce.img_size[session_idx]; 646 size = &p->adev->vce.img_size[session_idx];
658 break; 647 break;
659 648
660 case 0x00000002: // task info 649 case 0x00000002: /* task info */
661 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6); 650 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
662 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7); 651 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
663 break; 652 break;
664 653
665 case 0x01000001: // create 654 case 0x01000001: /* create */
666 created = true; 655 created |= 1 << session_idx;
667 if (!allocated) { 656 if (destroyed & (1 << session_idx)) {
657 destroyed &= ~(1 << session_idx);
658 allocated |= 1 << session_idx;
659
660 } else if (!(allocated & (1 << session_idx))) {
668 DRM_ERROR("Handle already in use!\n"); 661 DRM_ERROR("Handle already in use!\n");
669 r = -EINVAL; 662 r = -EINVAL;
670 goto out; 663 goto out;
@@ -675,16 +668,16 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
675 8 * 3 / 2; 668 8 * 3 / 2;
676 break; 669 break;
677 670
678 case 0x04000001: // config extension 671 case 0x04000001: /* config extension */
679 case 0x04000002: // pic control 672 case 0x04000002: /* pic control */
680 case 0x04000005: // rate control 673 case 0x04000005: /* rate control */
681 case 0x04000007: // motion estimation 674 case 0x04000007: /* motion estimation */
682 case 0x04000008: // rdo 675 case 0x04000008: /* rdo */
683 case 0x04000009: // vui 676 case 0x04000009: /* vui */
684 case 0x05000002: // auxiliary buffer 677 case 0x05000002: /* auxiliary buffer */
685 break; 678 break;
686 679
687 case 0x03000001: // encode 680 case 0x03000001: /* encode */
688 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9, 681 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
689 *size, 0); 682 *size, 0);
690 if (r) 683 if (r)
@@ -696,18 +689,18 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
696 goto out; 689 goto out;
697 break; 690 break;
698 691
699 case 0x02000001: // destroy 692 case 0x02000001: /* destroy */
700 destroyed = true; 693 destroyed |= 1 << session_idx;
701 break; 694 break;
702 695
703 case 0x05000001: // context buffer 696 case 0x05000001: /* context buffer */
704 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2, 697 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
705 *size * 2, 0); 698 *size * 2, 0);
706 if (r) 699 if (r)
707 goto out; 700 goto out;
708 break; 701 break;
709 702
710 case 0x05000004: // video bitstream buffer 703 case 0x05000004: /* video bitstream buffer */
711 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4); 704 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
712 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2, 705 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
713 tmp, bs_idx); 706 tmp, bs_idx);
@@ -715,7 +708,7 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
715 goto out; 708 goto out;
716 break; 709 break;
717 710
718 case 0x05000005: // feedback buffer 711 case 0x05000005: /* feedback buffer */
719 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2, 712 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
720 4096, fb_idx); 713 4096, fb_idx);
721 if (r) 714 if (r)
@@ -737,21 +730,24 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
737 idx += len / 4; 730 idx += len / 4;
738 } 731 }
739 732
740 if (allocated && !created) { 733 if (allocated & ~created) {
741 DRM_ERROR("New session without create command!\n"); 734 DRM_ERROR("New session without create command!\n");
742 r = -ENOENT; 735 r = -ENOENT;
743 } 736 }
744 737
745out: 738out:
746 if ((!r && destroyed) || (r && allocated)) { 739 if (!r) {
747 /* 740 /* No error, free all destroyed handle slots */
748 * IB contains a destroy msg or we have allocated an 741 tmp = destroyed;
749 * handle and got an error, anyway free the handle 742 } else {
750 */ 743 /* Error during parsing, free all allocated handle slots */
751 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) 744 tmp = allocated;
752 atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0);
753 } 745 }
754 746
747 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
748 if (tmp & (1 << i))
749 atomic_set(&p->adev->vce.handles[i], 0);
750
755 return r; 751 return r;
756} 752}
757 753
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 2f8496d48c94..8e642fc48df4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -195,6 +195,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
195 struct amdgpu_job *job) 195 struct amdgpu_job *job)
196{ 196{
197 struct amdgpu_device *adev = ring->adev; 197 struct amdgpu_device *adev = ring->adev;
198 uint64_t fence_context = adev->fence_context + ring->idx;
198 struct fence *updates = sync->last_vm_update; 199 struct fence *updates = sync->last_vm_update;
199 struct amdgpu_vm_id *id, *idle; 200 struct amdgpu_vm_id *id, *idle;
200 struct fence **fences; 201 struct fence **fences;
@@ -254,7 +255,6 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
254 i = ring->idx; 255 i = ring->idx;
255 do { 256 do {
256 struct fence *flushed; 257 struct fence *flushed;
257 bool same_ring = ring->idx == i;
258 258
259 id = vm->ids[i++]; 259 id = vm->ids[i++];
260 if (i == AMDGPU_MAX_RINGS) 260 if (i == AMDGPU_MAX_RINGS)
@@ -272,8 +272,11 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
272 if (job->vm_pd_addr != id->pd_gpu_addr) 272 if (job->vm_pd_addr != id->pd_gpu_addr)
273 continue; 273 continue;
274 274
275 if (!same_ring && 275 if (!id->last_flush)
276 (!id->last_flush || !fence_is_signaled(id->last_flush))) 276 continue;
277
278 if (id->last_flush->context != fence_context &&
279 !fence_is_signaled(id->last_flush))
277 continue; 280 continue;
278 281
279 flushed = id->flushed_updates; 282 flushed = id->flushed_updates;
@@ -294,7 +297,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
294 297
295 job->vm_id = id - adev->vm_manager.ids; 298 job->vm_id = id - adev->vm_manager.ids;
296 job->vm_needs_flush = false; 299 job->vm_needs_flush = false;
297 trace_amdgpu_vm_grab_id(vm, ring->idx, job->vm_id, job->vm_pd_addr); 300 trace_amdgpu_vm_grab_id(vm, ring->idx, job);
298 301
299 mutex_unlock(&adev->vm_manager.lock); 302 mutex_unlock(&adev->vm_manager.lock);
300 return 0; 303 return 0;
@@ -325,7 +328,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
325 vm->ids[ring->idx] = id; 328 vm->ids[ring->idx] = id;
326 329
327 job->vm_id = id - adev->vm_manager.ids; 330 job->vm_id = id - adev->vm_manager.ids;
328 trace_amdgpu_vm_grab_id(vm, ring->idx, job->vm_id, job->vm_pd_addr); 331 trace_amdgpu_vm_grab_id(vm, ring->idx, job);
329 332
330error: 333error:
331 mutex_unlock(&adev->vm_manager.lock); 334 mutex_unlock(&adev->vm_manager.lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index 48b6bd671cda..c32eca26155c 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -98,6 +98,7 @@ amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encode
98 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 98 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
99 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 99 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
101 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
101 if (dig->backlight_level == 0) 102 if (dig->backlight_level == 0)
102 amdgpu_atombios_encoder_setup_dig_transmitter(encoder, 103 amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
103 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 104 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 5c33ed862695..573bc973d692 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -86,12 +86,14 @@ static const struct ci_pt_defaults defaults_bonaire_xt =
86 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } 86 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
87}; 87};
88 88
89#if 0
89static const struct ci_pt_defaults defaults_bonaire_pro = 90static const struct ci_pt_defaults defaults_bonaire_pro =
90{ 91{
91 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062, 92 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
92 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F }, 93 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
93 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB } 94 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
94}; 95};
96#endif
95 97
96static const struct ci_pt_defaults defaults_saturn_xt = 98static const struct ci_pt_defaults defaults_saturn_xt =
97{ 99{
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 46aca16a40aa..6507a7ee75e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -622,7 +622,6 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
622 struct amdgpu_device *adev = ring->adev; 622 struct amdgpu_device *adev = ring->adev;
623 struct amdgpu_ib ib; 623 struct amdgpu_ib ib;
624 struct fence *f = NULL; 624 struct fence *f = NULL;
625 unsigned i;
626 unsigned index; 625 unsigned index;
627 int r; 626 int r;
628 u32 tmp = 0; 627 u32 tmp = 0;
@@ -644,7 +643,8 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
644 goto err0; 643 goto err0;
645 } 644 }
646 645
647 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 646 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
647 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
648 ib.ptr[1] = lower_32_bits(gpu_addr); 648 ib.ptr[1] = lower_32_bits(gpu_addr);
649 ib.ptr[2] = upper_32_bits(gpu_addr); 649 ib.ptr[2] = upper_32_bits(gpu_addr);
650 ib.ptr[3] = 1; 650 ib.ptr[3] = 1;
@@ -659,23 +659,15 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
659 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 659 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
660 goto err1; 660 goto err1;
661 } 661 }
662 for (i = 0; i < adev->usec_timeout; i++) { 662 tmp = le32_to_cpu(adev->wb.wb[index]);
663 tmp = le32_to_cpu(adev->wb.wb[index]); 663 if (tmp == 0xDEADBEEF) {
664 if (tmp == 0xDEADBEEF) 664 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
665 break;
666 DRM_UDELAY(1);
667 }
668 if (i < adev->usec_timeout) {
669 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
670 ring->idx, i);
671 goto err1;
672 } else { 665 } else {
673 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 666 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
674 r = -EINVAL; 667 r = -EINVAL;
675 } 668 }
676 669
677err1: 670err1:
678 fence_put(f);
679 amdgpu_ib_free(adev, &ib, NULL); 671 amdgpu_ib_free(adev, &ib, NULL);
680 fence_put(f); 672 fence_put(f);
681err0: 673err0:
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index f6bd9465dbdc..1ac5ad01bf58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2112,7 +2112,6 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2112 struct fence *f = NULL; 2112 struct fence *f = NULL;
2113 uint32_t scratch; 2113 uint32_t scratch;
2114 uint32_t tmp = 0; 2114 uint32_t tmp = 0;
2115 unsigned i;
2116 int r; 2115 int r;
2117 2116
2118 r = amdgpu_gfx_scratch_get(adev, &scratch); 2117 r = amdgpu_gfx_scratch_get(adev, &scratch);
@@ -2141,16 +2140,9 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2141 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 2140 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
2142 goto err2; 2141 goto err2;
2143 } 2142 }
2144 for (i = 0; i < adev->usec_timeout; i++) { 2143 tmp = RREG32(scratch);
2145 tmp = RREG32(scratch); 2144 if (tmp == 0xDEADBEEF) {
2146 if (tmp == 0xDEADBEEF) 2145 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
2147 break;
2148 DRM_UDELAY(1);
2149 }
2150 if (i < adev->usec_timeout) {
2151 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
2152 ring->idx, i);
2153 goto err2;
2154 } else { 2146 } else {
2155 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 2147 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2156 scratch, tmp); 2148 scratch, tmp);
@@ -2158,7 +2150,6 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2158 } 2150 }
2159 2151
2160err2: 2152err2:
2161 fence_put(f);
2162 amdgpu_ib_free(adev, &ib, NULL); 2153 amdgpu_ib_free(adev, &ib, NULL);
2163 fence_put(f); 2154 fence_put(f);
2164err1: 2155err1:
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index aabaf2f92575..d97b962bc3de 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -794,7 +794,6 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
794 struct fence *f = NULL; 794 struct fence *f = NULL;
795 uint32_t scratch; 795 uint32_t scratch;
796 uint32_t tmp = 0; 796 uint32_t tmp = 0;
797 unsigned i;
798 int r; 797 int r;
799 798
800 r = amdgpu_gfx_scratch_get(adev, &scratch); 799 r = amdgpu_gfx_scratch_get(adev, &scratch);
@@ -823,23 +822,15 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
823 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 822 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
824 goto err2; 823 goto err2;
825 } 824 }
826 for (i = 0; i < adev->usec_timeout; i++) { 825 tmp = RREG32(scratch);
827 tmp = RREG32(scratch); 826 if (tmp == 0xDEADBEEF) {
828 if (tmp == 0xDEADBEEF) 827 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
829 break;
830 DRM_UDELAY(1);
831 }
832 if (i < adev->usec_timeout) {
833 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
834 ring->idx, i);
835 goto err2;
836 } else { 828 } else {
837 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 829 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
838 scratch, tmp); 830 scratch, tmp);
839 r = -EINVAL; 831 r = -EINVAL;
840 } 832 }
841err2: 833err2:
842 fence_put(f);
843 amdgpu_ib_free(adev, &ib, NULL); 834 amdgpu_ib_free(adev, &ib, NULL);
844 fence_put(f); 835 fence_put(f);
845err1: 836err1:
@@ -1729,7 +1720,6 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1729 RREG32(sec_ded_counter_registers[i]); 1720 RREG32(sec_ded_counter_registers[i]);
1730 1721
1731fail: 1722fail:
1732 fence_put(f);
1733 amdgpu_ib_free(adev, &ib, NULL); 1723 amdgpu_ib_free(adev, &ib, NULL);
1734 fence_put(f); 1724 fence_put(f);
1735 1725
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
index 825ccd63f2dc..2f078ad6095c 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
@@ -24,7 +24,7 @@
24#include <linux/firmware.h> 24#include <linux/firmware.h>
25#include "drmP.h" 25#include "drmP.h"
26#include "amdgpu.h" 26#include "amdgpu.h"
27#include "iceland_smumgr.h" 27#include "iceland_smum.h"
28 28
29MODULE_FIRMWARE("amdgpu/topaz_smc.bin"); 29MODULE_FIRMWARE("amdgpu/topaz_smc.bin");
30 30
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
index 52ee08193295..528571285e69 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
@@ -25,7 +25,7 @@
25#include "drmP.h" 25#include "drmP.h"
26#include "amdgpu.h" 26#include "amdgpu.h"
27#include "ppsmc.h" 27#include "ppsmc.h"
28#include "iceland_smumgr.h" 28#include "iceland_smum.h"
29#include "smu_ucode_xfer_vi.h" 29#include "smu_ucode_xfer_vi.h"
30#include "amdgpu_ucode.h" 30#include "amdgpu_ucode.h"
31 31
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h b/drivers/gpu/drm/amd/amdgpu/iceland_smum.h
index 1e0769e110fa..1e0769e110fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_smum.h
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 5a0e245771ce..a845e883f5fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -191,6 +191,7 @@ static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
191 vid_mapping_table->num_entries = i; 191 vid_mapping_table->num_entries = i;
192} 192}
193 193
194#if 0
194static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] = 195static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
195{ 196{
196 { 0, 4, 1 }, 197 { 0, 4, 1 },
@@ -289,6 +290,7 @@ static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
289{ 290{
290 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 291 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
291}; 292};
293#endif
292 294
293static const struct kv_pt_config_reg didt_config_kv[] = 295static const struct kv_pt_config_reg didt_config_kv[] =
294{ 296{
diff --git a/drivers/gpu/drm/amd/amdgpu/ppsmc.h b/drivers/gpu/drm/amd/amdgpu/ppsmc.h
index 7837f2ecc357..8463245f424f 100644
--- a/drivers/gpu/drm/amd/amdgpu/ppsmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/ppsmc.h
@@ -90,7 +90,9 @@ typedef uint8_t PPSMC_Result;
90#define PPSMC_StartFanControl ((uint8_t)0x5B) 90#define PPSMC_StartFanControl ((uint8_t)0x5B)
91#define PPSMC_StopFanControl ((uint8_t)0x5C) 91#define PPSMC_StopFanControl ((uint8_t)0x5C)
92#define PPSMC_MSG_NoDisplay ((uint8_t)0x5D) 92#define PPSMC_MSG_NoDisplay ((uint8_t)0x5D)
93#define PPSMC_NoDisplay ((uint8_t)0x5D)
93#define PPSMC_MSG_HasDisplay ((uint8_t)0x5E) 94#define PPSMC_MSG_HasDisplay ((uint8_t)0x5E)
95#define PPSMC_HasDisplay ((uint8_t)0x5E)
94#define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60) 96#define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60)
95#define PPSMC_MSG_UVDPowerON ((uint8_t)0x61) 97#define PPSMC_MSG_UVDPowerON ((uint8_t)0x61)
96#define PPSMC_MSG_EnableULV ((uint8_t)0x62) 98#define PPSMC_MSG_EnableULV ((uint8_t)0x62)
@@ -108,6 +110,7 @@ typedef uint8_t PPSMC_Result;
108#define PPSMC_MSG_DisableDTE ((uint8_t)0x88) 110#define PPSMC_MSG_DisableDTE ((uint8_t)0x88)
109#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96) 111#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96)
110#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97) 112#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97)
113#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149)
111 114
112/* CI/KV/KB */ 115/* CI/KV/KB */
113#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) 116#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D)
@@ -161,6 +164,7 @@ typedef uint8_t PPSMC_Result;
161#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) 164#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190)
162#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) 165#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191)
163#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) 166#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A)
167#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205)
164 168
165#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) 169#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C)
166#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) 170#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index ac3730a6e49f..0111d153411b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -567,19 +567,21 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
567{ 567{
568 int r; 568 int r;
569 569
570 if (!adev->firmware.smu_load) { 570 if (!adev->pp_enabled) {
571 r = sdma_v2_4_load_microcode(adev); 571 if (!adev->firmware.smu_load) {
572 if (r) 572 r = sdma_v2_4_load_microcode(adev);
573 return r; 573 if (r)
574 } else { 574 return r;
575 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 575 } else {
576 AMDGPU_UCODE_ID_SDMA0); 576 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
577 if (r) 577 AMDGPU_UCODE_ID_SDMA0);
578 return -EINVAL; 578 if (r)
579 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 579 return -EINVAL;
580 AMDGPU_UCODE_ID_SDMA1); 580 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
581 if (r) 581 AMDGPU_UCODE_ID_SDMA1);
582 return -EINVAL; 582 if (r)
583 return -EINVAL;
584 }
583 } 585 }
584 586
585 /* halt the engine before programing */ 587 /* halt the engine before programing */
@@ -671,7 +673,6 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
671 struct amdgpu_device *adev = ring->adev; 673 struct amdgpu_device *adev = ring->adev;
672 struct amdgpu_ib ib; 674 struct amdgpu_ib ib;
673 struct fence *f = NULL; 675 struct fence *f = NULL;
674 unsigned i;
675 unsigned index; 676 unsigned index;
676 int r; 677 int r;
677 u32 tmp = 0; 678 u32 tmp = 0;
@@ -713,23 +714,15 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
713 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 714 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
714 goto err1; 715 goto err1;
715 } 716 }
716 for (i = 0; i < adev->usec_timeout; i++) { 717 tmp = le32_to_cpu(adev->wb.wb[index]);
717 tmp = le32_to_cpu(adev->wb.wb[index]); 718 if (tmp == 0xDEADBEEF) {
718 if (tmp == 0xDEADBEEF) 719 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
719 break;
720 DRM_UDELAY(1);
721 }
722 if (i < adev->usec_timeout) {
723 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
724 ring->idx, i);
725 goto err1;
726 } else { 720 } else {
727 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 721 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
728 r = -EINVAL; 722 r = -EINVAL;
729 } 723 }
730 724
731err1: 725err1:
732 fence_put(f);
733 amdgpu_ib_free(adev, &ib, NULL); 726 amdgpu_ib_free(adev, &ib, NULL);
734 fence_put(f); 727 fence_put(f);
735err0: 728err0:
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index f00db6f4c04c..2b8ce5808a14 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -901,7 +901,6 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
901 struct amdgpu_device *adev = ring->adev; 901 struct amdgpu_device *adev = ring->adev;
902 struct amdgpu_ib ib; 902 struct amdgpu_ib ib;
903 struct fence *f = NULL; 903 struct fence *f = NULL;
904 unsigned i;
905 unsigned index; 904 unsigned index;
906 int r; 905 int r;
907 u32 tmp = 0; 906 u32 tmp = 0;
@@ -943,22 +942,14 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
943 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 942 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
944 goto err1; 943 goto err1;
945 } 944 }
946 for (i = 0; i < adev->usec_timeout; i++) { 945 tmp = le32_to_cpu(adev->wb.wb[index]);
947 tmp = le32_to_cpu(adev->wb.wb[index]); 946 if (tmp == 0xDEADBEEF) {
948 if (tmp == 0xDEADBEEF) 947 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
949 break;
950 DRM_UDELAY(1);
951 }
952 if (i < adev->usec_timeout) {
953 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
954 ring->idx, i);
955 goto err1;
956 } else { 948 } else {
957 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 949 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
958 r = -EINVAL; 950 r = -EINVAL;
959 } 951 }
960err1: 952err1:
961 fence_put(f);
962 amdgpu_ib_free(adev, &ib, NULL); 953 amdgpu_ib_free(adev, &ib, NULL);
963 fence_put(f); 954 fence_put(f);
964err0: 955err0:
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 30e8099e94c5..d7b8da433fe2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -43,6 +43,7 @@
43#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616 43#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616
44#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617 44#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617
45#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618 45#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618
46#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
46 47
47#define VCE_V3_0_FW_SIZE (384 * 1024) 48#define VCE_V3_0_FW_SIZE (384 * 1024)
48#define VCE_V3_0_STACK_SIZE (64 * 1024) 49#define VCE_V3_0_STACK_SIZE (64 * 1024)
@@ -51,6 +52,7 @@
51static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx); 52static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
52static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); 53static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
53static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); 54static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
55static int vce_v3_0_wait_for_idle(void *handle);
54 56
55/** 57/**
56 * vce_v3_0_ring_get_rptr - get read pointer 58 * vce_v3_0_ring_get_rptr - get read pointer
@@ -205,6 +207,32 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
205 vce_v3_0_override_vce_clock_gating(adev, false); 207 vce_v3_0_override_vce_clock_gating(adev, false);
206} 208}
207 209
210static int vce_v3_0_firmware_loaded(struct amdgpu_device *adev)
211{
212 int i, j;
213 uint32_t status = 0;
214
215 for (i = 0; i < 10; ++i) {
216 for (j = 0; j < 100; ++j) {
217 status = RREG32(mmVCE_STATUS);
218 if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
219 return 0;
220 mdelay(10);
221 }
222
223 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
224 WREG32_P(mmVCE_SOFT_RESET,
225 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
226 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
227 mdelay(10);
228 WREG32_P(mmVCE_SOFT_RESET, 0,
229 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
230 mdelay(10);
231 }
232
233 return -ETIMEDOUT;
234}
235
208/** 236/**
209 * vce_v3_0_start - start VCE block 237 * vce_v3_0_start - start VCE block
210 * 238 *
@@ -215,11 +243,24 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
215static int vce_v3_0_start(struct amdgpu_device *adev) 243static int vce_v3_0_start(struct amdgpu_device *adev)
216{ 244{
217 struct amdgpu_ring *ring; 245 struct amdgpu_ring *ring;
218 int idx, i, j, r; 246 int idx, r;
247
248 ring = &adev->vce.ring[0];
249 WREG32(mmVCE_RB_RPTR, ring->wptr);
250 WREG32(mmVCE_RB_WPTR, ring->wptr);
251 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
252 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
253 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
254
255 ring = &adev->vce.ring[1];
256 WREG32(mmVCE_RB_RPTR2, ring->wptr);
257 WREG32(mmVCE_RB_WPTR2, ring->wptr);
258 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
259 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
260 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
219 261
220 mutex_lock(&adev->grbm_idx_mutex); 262 mutex_lock(&adev->grbm_idx_mutex);
221 for (idx = 0; idx < 2; ++idx) { 263 for (idx = 0; idx < 2; ++idx) {
222
223 if (adev->vce.harvest_config & (1 << idx)) 264 if (adev->vce.harvest_config & (1 << idx))
224 continue; 265 continue;
225 266
@@ -233,48 +274,24 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
233 274
234 vce_v3_0_mc_resume(adev, idx); 275 vce_v3_0_mc_resume(adev, idx);
235 276
236 /* set BUSY flag */ 277 WREG32_P(mmVCE_STATUS, VCE_STATUS__JOB_BUSY_MASK,
237 WREG32_P(mmVCE_STATUS, 1, ~1); 278 ~VCE_STATUS__JOB_BUSY_MASK);
279
238 if (adev->asic_type >= CHIP_STONEY) 280 if (adev->asic_type >= CHIP_STONEY)
239 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); 281 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
240 else 282 else
241 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, 283 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
242 ~VCE_VCPU_CNTL__CLK_EN_MASK); 284 ~VCE_VCPU_CNTL__CLK_EN_MASK);
243 285
244 WREG32_P(mmVCE_SOFT_RESET,
245 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
246 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
247
248 mdelay(100);
249
250 WREG32_P(mmVCE_SOFT_RESET, 0, 286 WREG32_P(mmVCE_SOFT_RESET, 0,
251 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); 287 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
252 288
253 for (i = 0; i < 10; ++i) { 289 mdelay(100);
254 uint32_t status; 290
255 for (j = 0; j < 100; ++j) { 291 r = vce_v3_0_firmware_loaded(adev);
256 status = RREG32(mmVCE_STATUS);
257 if (status & 2)
258 break;
259 mdelay(10);
260 }
261 r = 0;
262 if (status & 2)
263 break;
264
265 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
266 WREG32_P(mmVCE_SOFT_RESET,
267 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
268 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
269 mdelay(10);
270 WREG32_P(mmVCE_SOFT_RESET, 0,
271 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
272 mdelay(10);
273 r = -1;
274 }
275 292
276 /* clear BUSY flag */ 293 /* clear BUSY flag */
277 WREG32_P(mmVCE_STATUS, 0, ~1); 294 WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
278 295
279 /* Set Clock-Gating off */ 296 /* Set Clock-Gating off */
280 if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG) 297 if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
@@ -290,19 +307,46 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
290 WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); 307 WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
291 mutex_unlock(&adev->grbm_idx_mutex); 308 mutex_unlock(&adev->grbm_idx_mutex);
292 309
293 ring = &adev->vce.ring[0]; 310 return 0;
294 WREG32(mmVCE_RB_RPTR, ring->wptr); 311}
295 WREG32(mmVCE_RB_WPTR, ring->wptr);
296 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
297 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
298 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
299 312
300 ring = &adev->vce.ring[1]; 313static int vce_v3_0_stop(struct amdgpu_device *adev)
301 WREG32(mmVCE_RB_RPTR2, ring->wptr); 314{
302 WREG32(mmVCE_RB_WPTR2, ring->wptr); 315 int idx;
303 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); 316
304 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 317 mutex_lock(&adev->grbm_idx_mutex);
305 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); 318 for (idx = 0; idx < 2; ++idx) {
319 if (adev->vce.harvest_config & (1 << idx))
320 continue;
321
322 if (idx == 0)
323 WREG32_P(mmGRBM_GFX_INDEX, 0,
324 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
325 else
326 WREG32_P(mmGRBM_GFX_INDEX,
327 GRBM_GFX_INDEX__VCE_INSTANCE_MASK,
328 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
329
330 if (adev->asic_type >= CHIP_STONEY)
331 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);
332 else
333 WREG32_P(mmVCE_VCPU_CNTL, 0,
334 ~VCE_VCPU_CNTL__CLK_EN_MASK);
335 /* hold on ECPU */
336 WREG32_P(mmVCE_SOFT_RESET,
337 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
338 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
339
340 /* clear BUSY flag */
341 WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
342
343 /* Set Clock-Gating off */
344 if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
345 vce_v3_0_set_vce_sw_clock_gating(adev, false);
346 }
347
348 WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
349 mutex_unlock(&adev->grbm_idx_mutex);
306 350
307 return 0; 351 return 0;
308} 352}
@@ -441,7 +485,14 @@ static int vce_v3_0_hw_init(void *handle)
441 485
442static int vce_v3_0_hw_fini(void *handle) 486static int vce_v3_0_hw_fini(void *handle)
443{ 487{
444 return 0; 488 int r;
489 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
490
491 r = vce_v3_0_wait_for_idle(handle);
492 if (r)
493 return r;
494
495 return vce_v3_0_stop(adev);
445} 496}
446 497
447static int vce_v3_0_suspend(void *handle) 498static int vce_v3_0_suspend(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index cda7def9dc2c..03a31c53aec3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1249,15 +1249,7 @@ static int vi_common_early_init(void *handle)
1249 AMD_CG_SUPPORT_HDP_LS | 1249 AMD_CG_SUPPORT_HDP_LS |
1250 AMD_CG_SUPPORT_SDMA_MGCG | 1250 AMD_CG_SUPPORT_SDMA_MGCG |
1251 AMD_CG_SUPPORT_SDMA_LS; 1251 AMD_CG_SUPPORT_SDMA_LS;
1252 /* rev0 hardware doesn't support PG */
1253 adev->pg_flags = 0; 1252 adev->pg_flags = 0;
1254 if (adev->rev_id != 0x00)
1255 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1256 AMD_PG_SUPPORT_GFX_SMG |
1257 AMD_PG_SUPPORT_GFX_DMG |
1258 AMD_PG_SUPPORT_CP |
1259 AMD_PG_SUPPORT_RLC_SMU_HS |
1260 AMD_PG_SUPPORT_GFX_PIPELINE;
1261 adev->external_rev_id = adev->rev_id + 0x1; 1253 adev->external_rev_id = adev->rev_id + 0x1;
1262 break; 1254 break;
1263 case CHIP_STONEY: 1255 case CHIP_STONEY:
@@ -1276,12 +1268,6 @@ static int vi_common_early_init(void *handle)
1276 AMD_CG_SUPPORT_HDP_LS | 1268 AMD_CG_SUPPORT_HDP_LS |
1277 AMD_CG_SUPPORT_SDMA_MGCG | 1269 AMD_CG_SUPPORT_SDMA_MGCG |
1278 AMD_CG_SUPPORT_SDMA_LS; 1270 AMD_CG_SUPPORT_SDMA_LS;
1279 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1280 AMD_PG_SUPPORT_GFX_SMG |
1281 AMD_PG_SUPPORT_GFX_DMG |
1282 AMD_PG_SUPPORT_GFX_PIPELINE |
1283 AMD_PG_SUPPORT_CP |
1284 AMD_PG_SUPPORT_RLC_SMU_HS;
1285 adev->external_rev_id = adev->rev_id + 0x1; 1271 adev->external_rev_id = adev->rev_id + 0x1;
1286 break; 1272 break;
1287 default: 1273 default:
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index 0c8c85d2a2a5..f32af2f2091a 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -160,6 +160,10 @@ struct cgs_firmware_info {
160 uint16_t feature_version; 160 uint16_t feature_version;
161 uint32_t image_size; 161 uint32_t image_size;
162 uint64_t mc_addr; 162 uint64_t mc_addr;
163
164 /* only for smc firmware */
165 uint32_t ucode_start_address;
166
163 void *kptr; 167 void *kptr;
164}; 168};
165 169
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index a6c9b4201e25..d1b528b401e9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -1828,7 +1828,7 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1828{ 1828{
1829 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; 1829 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1830 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); 1830 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1831 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0; 1831 uint8_t i, stretch_amount, volt_offset = 0;
1832 struct phm_ppt_v1_information *table_info = 1832 struct phm_ppt_v1_information *table_info =
1833 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1833 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1834 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 1834 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
@@ -1879,11 +1879,8 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1879 1879
1880 data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6; 1880 data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1881 /* Populate CKS Lookup Table */ 1881 /* Populate CKS Lookup Table */
1882 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5) 1882 if (stretch_amount != 1 && stretch_amount != 2 && stretch_amount != 3 &&
1883 stretch_amount2 = 0; 1883 stretch_amount != 4 && stretch_amount != 5) {
1884 else if (stretch_amount == 3 || stretch_amount == 4)
1885 stretch_amount2 = 1;
1886 else {
1887 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1884 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1888 PHM_PlatformCaps_ClockStretcher); 1885 PHM_PlatformCaps_ClockStretcher);
1889 PP_ASSERT_WITH_CODE(false, 1886 PP_ASSERT_WITH_CODE(false,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index a64db7ba4e0b..e2aece361eb0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -179,13 +179,12 @@ int atomctrl_set_engine_dram_timings_rv770(
179 179
180 /* They are both in 10KHz Units. */ 180 /* They are both in 10KHz Units. */
181 engine_clock_parameters.ulTargetEngineClock = 181 engine_clock_parameters.ulTargetEngineClock =
182 (uint32_t) engine_clock & SET_CLOCK_FREQ_MASK; 182 cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) |
183 engine_clock_parameters.ulTargetEngineClock |= 183 ((COMPUTE_ENGINE_PLL_PARAM << 24)));
184 (COMPUTE_ENGINE_PLL_PARAM << 24);
185 184
186 /* in 10 khz units.*/ 185 /* in 10 khz units.*/
187 engine_clock_parameters.sReserved.ulClock = 186 engine_clock_parameters.sReserved.ulClock =
188 (uint32_t) memory_clock & SET_CLOCK_FREQ_MASK; 187 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK);
189 return cgs_atom_exec_cmd_table(hwmgr->device, 188 return cgs_atom_exec_cmd_table(hwmgr->device,
190 GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings), 189 GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
191 &engine_clock_parameters); 190 &engine_clock_parameters);
@@ -252,7 +251,7 @@ int atomctrl_get_memory_pll_dividers_si(
252 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters; 251 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters;
253 int result; 252 int result;
254 253
255 mpll_parameters.ulClock = (uint32_t) clock_value; 254 mpll_parameters.ulClock = cpu_to_le32(clock_value);
256 mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0); 255 mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0);
257 256
258 result = cgs_atom_exec_cmd_table 257 result = cgs_atom_exec_cmd_table
@@ -262,9 +261,9 @@ int atomctrl_get_memory_pll_dividers_si(
262 261
263 if (0 == result) { 262 if (0 == result) {
264 mpll_param->mpll_fb_divider.clk_frac = 263 mpll_param->mpll_fb_divider.clk_frac =
265 mpll_parameters.ulFbDiv.usFbDivFrac; 264 le16_to_cpu(mpll_parameters.ulFbDiv.usFbDivFrac);
266 mpll_param->mpll_fb_divider.cl_kf = 265 mpll_param->mpll_fb_divider.cl_kf =
267 mpll_parameters.ulFbDiv.usFbDiv; 266 le16_to_cpu(mpll_parameters.ulFbDiv.usFbDiv);
268 mpll_param->mpll_post_divider = 267 mpll_param->mpll_post_divider =
269 (uint32_t)mpll_parameters.ucPostDiv; 268 (uint32_t)mpll_parameters.ucPostDiv;
270 mpll_param->vco_mode = 269 mpll_param->vco_mode =
@@ -300,7 +299,7 @@ int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
300 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters; 299 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters;
301 int result; 300 int result;
302 301
303 mpll_parameters.ulClock.ulClock = (uint32_t)clock_value; 302 mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
304 303
305 result = cgs_atom_exec_cmd_table(hwmgr->device, 304 result = cgs_atom_exec_cmd_table(hwmgr->device,
306 GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam), 305 GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
@@ -320,7 +319,7 @@ int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
320 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters; 319 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;
321 int result; 320 int result;
322 321
323 pll_parameters.ulClock = clock_value; 322 pll_parameters.ulClock = cpu_to_le32(clock_value);
324 323
325 result = cgs_atom_exec_cmd_table 324 result = cgs_atom_exec_cmd_table
326 (hwmgr->device, 325 (hwmgr->device,
@@ -329,7 +328,7 @@ int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
329 328
330 if (0 == result) { 329 if (0 == result) {
331 dividers->pll_post_divider = pll_parameters.ucPostDiv; 330 dividers->pll_post_divider = pll_parameters.ucPostDiv;
332 dividers->real_clock = pll_parameters.ulClock; 331 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock);
333 } 332 }
334 333
335 return result; 334 return result;
@@ -343,7 +342,7 @@ int atomctrl_get_engine_pll_dividers_vi(
343 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters; 342 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
344 int result; 343 int result;
345 344
346 pll_patameters.ulClock.ulClock = clock_value; 345 pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
347 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK; 346 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
348 347
349 result = cgs_atom_exec_cmd_table 348 result = cgs_atom_exec_cmd_table
@@ -355,12 +354,12 @@ int atomctrl_get_engine_pll_dividers_vi(
355 dividers->pll_post_divider = 354 dividers->pll_post_divider =
356 pll_patameters.ulClock.ucPostDiv; 355 pll_patameters.ulClock.ucPostDiv;
357 dividers->real_clock = 356 dividers->real_clock =
358 pll_patameters.ulClock.ulClock; 357 le32_to_cpu(pll_patameters.ulClock.ulClock);
359 358
360 dividers->ul_fb_div.ul_fb_div_frac = 359 dividers->ul_fb_div.ul_fb_div_frac =
361 pll_patameters.ulFbDiv.usFbDivFrac; 360 le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac);
362 dividers->ul_fb_div.ul_fb_div = 361 dividers->ul_fb_div.ul_fb_div =
363 pll_patameters.ulFbDiv.usFbDiv; 362 le16_to_cpu(pll_patameters.ulFbDiv.usFbDiv);
364 363
365 dividers->uc_pll_ref_div = 364 dividers->uc_pll_ref_div =
366 pll_patameters.ucPllRefDiv; 365 pll_patameters.ucPllRefDiv;
@@ -380,7 +379,7 @@ int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr,
380 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters; 379 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters;
381 int result; 380 int result;
382 381
383 pll_patameters.ulClock.ulClock = clock_value; 382 pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
384 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK; 383 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
385 384
386 result = cgs_atom_exec_cmd_table 385 result = cgs_atom_exec_cmd_table
@@ -412,7 +411,7 @@ int atomctrl_get_dfs_pll_dividers_vi(
412 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters; 411 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
413 int result; 412 int result;
414 413
415 pll_patameters.ulClock.ulClock = clock_value; 414 pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
416 pll_patameters.ulClock.ucPostDiv = 415 pll_patameters.ulClock.ucPostDiv =
417 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK; 416 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK;
418 417
@@ -425,12 +424,12 @@ int atomctrl_get_dfs_pll_dividers_vi(
425 dividers->pll_post_divider = 424 dividers->pll_post_divider =
426 pll_patameters.ulClock.ucPostDiv; 425 pll_patameters.ulClock.ucPostDiv;
427 dividers->real_clock = 426 dividers->real_clock =
428 pll_patameters.ulClock.ulClock; 427 le32_to_cpu(pll_patameters.ulClock.ulClock);
429 428
430 dividers->ul_fb_div.ul_fb_div_frac = 429 dividers->ul_fb_div.ul_fb_div_frac =
431 pll_patameters.ulFbDiv.usFbDivFrac; 430 le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac);
432 dividers->ul_fb_div.ul_fb_div = 431 dividers->ul_fb_div.ul_fb_div =
433 pll_patameters.ulFbDiv.usFbDiv; 432 le16_to_cpu(pll_patameters.ulFbDiv.usFbDiv);
434 433
435 dividers->uc_pll_ref_div = 434 dividers->uc_pll_ref_div =
436 pll_patameters.ucPllRefDiv; 435 pll_patameters.ucPllRefDiv;
@@ -519,13 +518,13 @@ int atomctrl_get_voltage_table_v3(
519 518
520 for (i = 0; i < voltage_object->asGpioVoltageObj.ucGpioEntryNum; i++) { 519 for (i = 0; i < voltage_object->asGpioVoltageObj.ucGpioEntryNum; i++) {
521 voltage_table->entries[i].value = 520 voltage_table->entries[i].value =
522 voltage_object->asGpioVoltageObj.asVolGpioLut[i].usVoltageValue; 521 le16_to_cpu(voltage_object->asGpioVoltageObj.asVolGpioLut[i].usVoltageValue);
523 voltage_table->entries[i].smio_low = 522 voltage_table->entries[i].smio_low =
524 voltage_object->asGpioVoltageObj.asVolGpioLut[i].ulVoltageId; 523 le32_to_cpu(voltage_object->asGpioVoltageObj.asVolGpioLut[i].ulVoltageId);
525 } 524 }
526 525
527 voltage_table->mask_low = 526 voltage_table->mask_low =
528 voltage_object->asGpioVoltageObj.ulGpioMaskVal; 527 le32_to_cpu(voltage_object->asGpioVoltageObj.ulGpioMaskVal);
529 voltage_table->count = 528 voltage_table->count =
530 voltage_object->asGpioVoltageObj.ucGpioEntryNum; 529 voltage_object->asGpioVoltageObj.ucGpioEntryNum;
531 voltage_table->phase_delay = 530 voltage_table->phase_delay =
@@ -592,12 +591,12 @@ bool atomctrl_get_pp_assign_pin(
592 const uint32_t pinId, 591 const uint32_t pinId,
593 pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment) 592 pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment)
594{ 593{
595 bool bRet = 0; 594 bool bRet = false;
596 ATOM_GPIO_PIN_LUT *gpio_lookup_table = 595 ATOM_GPIO_PIN_LUT *gpio_lookup_table =
597 get_gpio_lookup_table(hwmgr->device); 596 get_gpio_lookup_table(hwmgr->device);
598 597
599 PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table), 598 PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),
600 "Could not find GPIO lookup Table in BIOS.", return -1); 599 "Could not find GPIO lookup Table in BIOS.", return false);
601 600
602 bRet = atomctrl_lookup_gpio_pin(gpio_lookup_table, pinId, 601 bRet = atomctrl_lookup_gpio_pin(gpio_lookup_table, pinId,
603 gpio_pin_assignment); 602 gpio_pin_assignment);
@@ -650,8 +649,8 @@ int atomctrl_calculate_voltage_evv_on_sclk(
650 return -1; 649 return -1;
651 650
652 if (getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 || 651 if (getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 ||
653 (getASICProfilingInfo->asHeader.ucTableFormatRevision == 3 && 652 (getASICProfilingInfo->asHeader.ucTableFormatRevision == 3 &&
654 getASICProfilingInfo->asHeader.ucTableContentRevision < 4)) 653 getASICProfilingInfo->asHeader.ucTableContentRevision < 4))
655 return -1; 654 return -1;
656 655
657 /*----------------------------------------------------------- 656 /*-----------------------------------------------------------
@@ -662,37 +661,37 @@ int atomctrl_calculate_voltage_evv_on_sclk(
662 661
663 switch (dpm_level) { 662 switch (dpm_level) {
664 case 1: 663 case 1:
665 fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm1); 664 fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm1));
666 fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM1, 1000); 665 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM1), 1000);
667 break; 666 break;
668 case 2: 667 case 2:
669 fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm2); 668 fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm2));
670 fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM2, 1000); 669 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM2), 1000);
671 break; 670 break;
672 case 3: 671 case 3:
673 fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm3); 672 fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm3));
674 fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM3, 1000); 673 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM3), 1000);
675 break; 674 break;
676 case 4: 675 case 4:
677 fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm4); 676 fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm4));
678 fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM4, 1000); 677 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM4), 1000);
679 break; 678 break;
680 case 5: 679 case 5:
681 fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm5); 680 fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm5));
682 fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM5, 1000); 681 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM5), 1000);
683 break; 682 break;
684 case 6: 683 case 6:
685 fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm6); 684 fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm6));
686 fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM6, 1000); 685 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM6), 1000);
687 break; 686 break;
688 case 7: 687 case 7:
689 fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm7); 688 fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm7));
690 fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM7, 1000); 689 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM7), 1000);
691 break; 690 break;
692 default: 691 default:
693 printk(KERN_ERR "DPM Level not supported\n"); 692 printk(KERN_ERR "DPM Level not supported\n");
694 fPowerDPMx = Convert_ULONG_ToFraction(1); 693 fPowerDPMx = Convert_ULONG_ToFraction(1);
695 fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM0, 1000); 694 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM0), 1000);
696 } 695 }
697 696
698 /*------------------------- 697 /*-------------------------
@@ -716,9 +715,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
716 return result; 715 return result;
717 716
718 /* Finally, the actual fuse value */ 717 /* Finally, the actual fuse value */
719 ul_RO_fused = sOutput_FuseValues.ulEfuseValue; 718 ul_RO_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
720 fMin = GetScaledFraction(sRO_fuse.ulEfuseMin, 1); 719 fMin = GetScaledFraction(le32_to_cpu(sRO_fuse.ulEfuseMin), 1);
721 fRange = GetScaledFraction(sRO_fuse.ulEfuseEncodeRange, 1); 720 fRange = GetScaledFraction(le32_to_cpu(sRO_fuse.ulEfuseEncodeRange), 1);
722 fRO_fused = fDecodeLinearFuse(ul_RO_fused, fMin, fRange, sRO_fuse.ucEfuseLength); 721 fRO_fused = fDecodeLinearFuse(ul_RO_fused, fMin, fRange, sRO_fuse.ucEfuseLength);
723 722
724 sCACm_fuse = getASICProfilingInfo->sCACm; 723 sCACm_fuse = getASICProfilingInfo->sCACm;
@@ -736,9 +735,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
736 if (result) 735 if (result)
737 return result; 736 return result;
738 737
739 ul_CACm_fused = sOutput_FuseValues.ulEfuseValue; 738 ul_CACm_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
740 fMin = GetScaledFraction(sCACm_fuse.ulEfuseMin, 1000); 739 fMin = GetScaledFraction(le32_to_cpu(sCACm_fuse.ulEfuseMin), 1000);
741 fRange = GetScaledFraction(sCACm_fuse.ulEfuseEncodeRange, 1000); 740 fRange = GetScaledFraction(le32_to_cpu(sCACm_fuse.ulEfuseEncodeRange), 1000);
742 741
743 fCACm_fused = fDecodeLinearFuse(ul_CACm_fused, fMin, fRange, sCACm_fuse.ucEfuseLength); 742 fCACm_fused = fDecodeLinearFuse(ul_CACm_fused, fMin, fRange, sCACm_fuse.ucEfuseLength);
744 743
@@ -756,9 +755,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
756 if (result) 755 if (result)
757 return result; 756 return result;
758 757
759 ul_CACb_fused = sOutput_FuseValues.ulEfuseValue; 758 ul_CACb_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
760 fMin = GetScaledFraction(sCACb_fuse.ulEfuseMin, 1000); 759 fMin = GetScaledFraction(le32_to_cpu(sCACb_fuse.ulEfuseMin), 1000);
761 fRange = GetScaledFraction(sCACb_fuse.ulEfuseEncodeRange, 1000); 760 fRange = GetScaledFraction(le32_to_cpu(sCACb_fuse.ulEfuseEncodeRange), 1000);
762 761
763 fCACb_fused = fDecodeLinearFuse(ul_CACb_fused, fMin, fRange, sCACb_fuse.ucEfuseLength); 762 fCACb_fused = fDecodeLinearFuse(ul_CACb_fused, fMin, fRange, sCACb_fuse.ucEfuseLength);
764 763
@@ -777,9 +776,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
777 if (result) 776 if (result)
778 return result; 777 return result;
779 778
780 ul_Kt_Beta_fused = sOutput_FuseValues.ulEfuseValue; 779 ul_Kt_Beta_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
781 fAverage = GetScaledFraction(sKt_Beta_fuse.ulEfuseEncodeAverage, 1000); 780 fAverage = GetScaledFraction(le32_to_cpu(sKt_Beta_fuse.ulEfuseEncodeAverage), 1000);
782 fRange = GetScaledFraction(sKt_Beta_fuse.ulEfuseEncodeRange, 1000); 781 fRange = GetScaledFraction(le32_to_cpu(sKt_Beta_fuse.ulEfuseEncodeRange), 1000);
783 782
784 fKt_Beta_fused = fDecodeLogisticFuse(ul_Kt_Beta_fused, 783 fKt_Beta_fused = fDecodeLogisticFuse(ul_Kt_Beta_fused,
785 fAverage, fRange, sKt_Beta_fuse.ucEfuseLength); 784 fAverage, fRange, sKt_Beta_fuse.ucEfuseLength);
@@ -798,9 +797,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
798 if (result) 797 if (result)
799 return result; 798 return result;
800 799
801 ul_Kv_m_fused = sOutput_FuseValues.ulEfuseValue; 800 ul_Kv_m_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
802 fAverage = GetScaledFraction(sKv_m_fuse.ulEfuseEncodeAverage, 1000); 801 fAverage = GetScaledFraction(le32_to_cpu(sKv_m_fuse.ulEfuseEncodeAverage), 1000);
803 fRange = GetScaledFraction((sKv_m_fuse.ulEfuseEncodeRange & 0x7fffffff), 1000); 802 fRange = GetScaledFraction((le32_to_cpu(sKv_m_fuse.ulEfuseEncodeRange) & 0x7fffffff), 1000);
804 fRange = fMultiply(fRange, ConvertToFraction(-1)); 803 fRange = fMultiply(fRange, ConvertToFraction(-1));
805 804
806 fKv_m_fused = fDecodeLogisticFuse(ul_Kv_m_fused, 805 fKv_m_fused = fDecodeLogisticFuse(ul_Kv_m_fused,
@@ -820,9 +819,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
820 if (result) 819 if (result)
821 return result; 820 return result;
822 821
823 ul_Kv_b_fused = sOutput_FuseValues.ulEfuseValue; 822 ul_Kv_b_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
824 fAverage = GetScaledFraction(sKv_b_fuse.ulEfuseEncodeAverage, 1000); 823 fAverage = GetScaledFraction(le32_to_cpu(sKv_b_fuse.ulEfuseEncodeAverage), 1000);
825 fRange = GetScaledFraction(sKv_b_fuse.ulEfuseEncodeRange, 1000); 824 fRange = GetScaledFraction(le32_to_cpu(sKv_b_fuse.ulEfuseEncodeRange), 1000);
826 825
827 fKv_b_fused = fDecodeLogisticFuse(ul_Kv_b_fused, 826 fKv_b_fused = fDecodeLogisticFuse(ul_Kv_b_fused,
828 fAverage, fRange, sKv_b_fuse.ucEfuseLength); 827 fAverage, fRange, sKv_b_fuse.ucEfuseLength);
@@ -851,9 +850,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
851 if (result) 850 if (result)
852 return result; 851 return result;
853 852
854 ul_FT_Lkg_V0NORM = sOutput_FuseValues.ulEfuseValue; 853 ul_FT_Lkg_V0NORM = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
855 fLn_MaxDivMin = GetScaledFraction(getASICProfilingInfo->ulLkgEncodeLn_MaxDivMin, 10000); 854 fLn_MaxDivMin = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLkgEncodeLn_MaxDivMin), 10000);
856 fMin = GetScaledFraction(getASICProfilingInfo->ulLkgEncodeMin, 10000); 855 fMin = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLkgEncodeMin), 10000);
857 856
858 fFT_Lkg_V0NORM = fDecodeLeakageID(ul_FT_Lkg_V0NORM, 857 fFT_Lkg_V0NORM = fDecodeLeakageID(ul_FT_Lkg_V0NORM,
859 fLn_MaxDivMin, fMin, getASICProfilingInfo->ucLkgEfuseLength); 858 fLn_MaxDivMin, fMin, getASICProfilingInfo->ucLkgEfuseLength);
@@ -863,40 +862,40 @@ int atomctrl_calculate_voltage_evv_on_sclk(
863 * PART 2 - Grabbing all required values 862 * PART 2 - Grabbing all required values
864 *------------------------------------------- 863 *-------------------------------------------
865 */ 864 */
866 fSM_A0 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A0, 1000000), 865 fSM_A0 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A0), 1000000),
867 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A0_sign))); 866 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A0_sign)));
868 fSM_A1 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A1, 1000000), 867 fSM_A1 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A1), 1000000),
869 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A1_sign))); 868 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A1_sign)));
870 fSM_A2 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A2, 100000), 869 fSM_A2 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A2), 100000),
871 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A2_sign))); 870 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A2_sign)));
872 fSM_A3 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A3, 1000000), 871 fSM_A3 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A3), 1000000),
873 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A3_sign))); 872 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A3_sign)));
874 fSM_A4 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A4, 1000000), 873 fSM_A4 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A4), 1000000),
875 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A4_sign))); 874 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A4_sign)));
876 fSM_A5 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A5, 1000), 875 fSM_A5 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A5), 1000),
877 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A5_sign))); 876 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A5_sign)));
878 fSM_A6 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A6, 1000), 877 fSM_A6 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A6), 1000),
879 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A6_sign))); 878 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A6_sign)));
880 fSM_A7 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A7, 1000), 879 fSM_A7 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A7), 1000),
881 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A7_sign))); 880 ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A7_sign)));
882 881
883 fMargin_RO_a = ConvertToFraction(getASICProfilingInfo->ulMargin_RO_a); 882 fMargin_RO_a = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_a));
884 fMargin_RO_b = ConvertToFraction(getASICProfilingInfo->ulMargin_RO_b); 883 fMargin_RO_b = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_b));
885 fMargin_RO_c = ConvertToFraction(getASICProfilingInfo->ulMargin_RO_c); 884 fMargin_RO_c = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_c));
886 885
887 fMargin_fixed = ConvertToFraction(getASICProfilingInfo->ulMargin_fixed); 886 fMargin_fixed = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_fixed));
888 887
889 fMargin_FMAX_mean = GetScaledFraction( 888 fMargin_FMAX_mean = GetScaledFraction(
890 getASICProfilingInfo->ulMargin_Fmax_mean, 10000); 889 le32_to_cpu(getASICProfilingInfo->ulMargin_Fmax_mean), 10000);
891 fMargin_Plat_mean = GetScaledFraction( 890 fMargin_Plat_mean = GetScaledFraction(
892 getASICProfilingInfo->ulMargin_plat_mean, 10000); 891 le32_to_cpu(getASICProfilingInfo->ulMargin_plat_mean), 10000);
893 fMargin_FMAX_sigma = GetScaledFraction( 892 fMargin_FMAX_sigma = GetScaledFraction(
894 getASICProfilingInfo->ulMargin_Fmax_sigma, 10000); 893 le32_to_cpu(getASICProfilingInfo->ulMargin_Fmax_sigma), 10000);
895 fMargin_Plat_sigma = GetScaledFraction( 894 fMargin_Plat_sigma = GetScaledFraction(
896 getASICProfilingInfo->ulMargin_plat_sigma, 10000); 895 le32_to_cpu(getASICProfilingInfo->ulMargin_plat_sigma), 10000);
897 896
898 fMargin_DC_sigma = GetScaledFraction( 897 fMargin_DC_sigma = GetScaledFraction(
899 getASICProfilingInfo->ulMargin_DC_sigma, 100); 898 le32_to_cpu(getASICProfilingInfo->ulMargin_DC_sigma), 100);
900 fMargin_DC_sigma = fDivide(fMargin_DC_sigma, ConvertToFraction(1000)); 899 fMargin_DC_sigma = fDivide(fMargin_DC_sigma, ConvertToFraction(1000));
901 900
902 fCACm_fused = fDivide(fCACm_fused, ConvertToFraction(100)); 901 fCACm_fused = fDivide(fCACm_fused, ConvertToFraction(100));
@@ -908,14 +907,14 @@ int atomctrl_calculate_voltage_evv_on_sclk(
908 fSclk = GetScaledFraction(sclk, 100); 907 fSclk = GetScaledFraction(sclk, 100);
909 908
910 fV_max = fDivide(GetScaledFraction( 909 fV_max = fDivide(GetScaledFraction(
911 getASICProfilingInfo->ulMaxVddc, 1000), ConvertToFraction(4)); 910 le32_to_cpu(getASICProfilingInfo->ulMaxVddc), 1000), ConvertToFraction(4));
912 fT_prod = GetScaledFraction(getASICProfilingInfo->ulBoardCoreTemp, 10); 911 fT_prod = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulBoardCoreTemp), 10);
913 fLKG_Factor = GetScaledFraction(getASICProfilingInfo->ulEvvLkgFactor, 100); 912 fLKG_Factor = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulEvvLkgFactor), 100);
914 fT_FT = GetScaledFraction(getASICProfilingInfo->ulLeakageTemp, 10); 913 fT_FT = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLeakageTemp), 10);
915 fV_FT = fDivide(GetScaledFraction( 914 fV_FT = fDivide(GetScaledFraction(
916 getASICProfilingInfo->ulLeakageVoltage, 1000), ConvertToFraction(4)); 915 le32_to_cpu(getASICProfilingInfo->ulLeakageVoltage), 1000), ConvertToFraction(4));
917 fV_min = fDivide(GetScaledFraction( 916 fV_min = fDivide(GetScaledFraction(
918 getASICProfilingInfo->ulMinVddc, 1000), ConvertToFraction(4)); 917 le32_to_cpu(getASICProfilingInfo->ulMinVddc), 1000), ConvertToFraction(4));
919 918
920 /*----------------------- 919 /*-----------------------
921 * PART 3 920 * PART 3
@@ -925,7 +924,7 @@ int atomctrl_calculate_voltage_evv_on_sclk(
925 fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4, fSclk), fSM_A5)); 924 fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4, fSclk), fSM_A5));
926 fB_Term = fAdd(fAdd(fMultiply(fSM_A2, fSclk), fSM_A6), fMargin_RO_b); 925 fB_Term = fAdd(fAdd(fMultiply(fSM_A2, fSclk), fSM_A6), fMargin_RO_b);
927 fC_Term = fAdd(fMargin_RO_c, 926 fC_Term = fAdd(fMargin_RO_c,
928 fAdd(fMultiply(fSM_A0,fLkg_FT), 927 fAdd(fMultiply(fSM_A0, fLkg_FT),
929 fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT, fSclk)), 928 fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT, fSclk)),
930 fAdd(fMultiply(fSM_A3, fSclk), 929 fAdd(fMultiply(fSM_A3, fSclk),
931 fSubtract(fSM_A7, fRO_fused))))); 930 fSubtract(fSM_A7, fRO_fused)))));
@@ -1063,9 +1062,55 @@ int atomctrl_get_voltage_evv_on_sclk(
1063 get_voltage_info_param_space.ucVoltageMode = 1062 get_voltage_info_param_space.ucVoltageMode =
1064 ATOM_GET_VOLTAGE_EVV_VOLTAGE; 1063 ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1065 get_voltage_info_param_space.usVoltageLevel = 1064 get_voltage_info_param_space.usVoltageLevel =
1066 virtual_voltage_Id; 1065 cpu_to_le16(virtual_voltage_Id);
1067 get_voltage_info_param_space.ulSCLKFreq = 1066 get_voltage_info_param_space.ulSCLKFreq =
1068 sclk; 1067 cpu_to_le32(sclk);
1068
1069 result = cgs_atom_exec_cmd_table(hwmgr->device,
1070 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1071 &get_voltage_info_param_space);
1072
1073 if (0 != result)
1074 return result;
1075
1076 *voltage = le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
1077 (&get_voltage_info_param_space))->usVoltageLevel);
1078
1079 return result;
1080}
1081
1082/**
1083 * atomctrl_get_voltage_evv gets voltage via call to ATOM COMMAND table.
1084 * @param hwmgr input: pointer to hwManager
1085 * @param virtual_voltage_id input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08
1086 * @param voltage output: real voltage level in unit of mv
1087 */
1088int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr,
1089 uint16_t virtual_voltage_id,
1090 uint16_t *voltage)
1091{
1092 int result;
1093 int entry_id;
1094 GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
1095
1096 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
1097 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) {
1098 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) {
1099 /* found */
1100 break;
1101 }
1102 }
1103
1104 PP_ASSERT_WITH_CODE(entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count,
1105 "Can't find requested voltage id in vddc_dependency_on_sclk table!",
1106 return -EINVAL;
1107 );
1108
1109 get_voltage_info_param_space.ucVoltageType = VOLTAGE_TYPE_VDDC;
1110 get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1111 get_voltage_info_param_space.usVoltageLevel = virtual_voltage_id;
1112 get_voltage_info_param_space.ulSCLKFreq =
1113 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);
1069 1114
1070 result = cgs_atom_exec_cmd_table(hwmgr->device, 1115 result = cgs_atom_exec_cmd_table(hwmgr->device,
1071 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo), 1116 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
@@ -1074,8 +1119,8 @@ int atomctrl_get_voltage_evv_on_sclk(
1074 if (0 != result) 1119 if (0 != result)
1075 return result; 1120 return result;
1076 1121
1077 *voltage = ((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *) 1122 *voltage = le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
1078 (&get_voltage_info_param_space))->usVoltageLevel; 1123 (&get_voltage_info_param_space))->usVoltageLevel);
1079 1124
1080 return result; 1125 return result;
1081} 1126}
@@ -1165,8 +1210,8 @@ static int asic_internal_ss_get_ss_asignment(struct pp_hwmgr *hwmgr,
1165 1210
1166 if (entry_found) { 1211 if (entry_found) {
1167 ssEntry->speed_spectrum_percentage = 1212 ssEntry->speed_spectrum_percentage =
1168 ssInfo->usSpreadSpectrumPercentage; 1213 le16_to_cpu(ssInfo->usSpreadSpectrumPercentage);
1169 ssEntry->speed_spectrum_rate = ssInfo->usSpreadRateInKhz; 1214 ssEntry->speed_spectrum_rate = le16_to_cpu(ssInfo->usSpreadRateInKhz);
1170 1215
1171 if (((GET_DATA_TABLE_MAJOR_REVISION(table) == 2) && 1216 if (((GET_DATA_TABLE_MAJOR_REVISION(table) == 2) &&
1172 (GET_DATA_TABLE_MINOR_REVISION(table) >= 2)) || 1217 (GET_DATA_TABLE_MINOR_REVISION(table) >= 2)) ||
@@ -1222,7 +1267,7 @@ int atomctrl_read_efuse(void *device, uint16_t start_index,
1222 int result; 1267 int result;
1223 READ_EFUSE_VALUE_PARAMETER efuse_param; 1268 READ_EFUSE_VALUE_PARAMETER efuse_param;
1224 1269
1225 efuse_param.sEfuse.usEfuseIndex = (start_index / 32) * 4; 1270 efuse_param.sEfuse.usEfuseIndex = cpu_to_le16((start_index / 32) * 4);
1226 efuse_param.sEfuse.ucBitShift = (uint8_t) 1271 efuse_param.sEfuse.ucBitShift = (uint8_t)
1227 (start_index - ((start_index / 32) * 32)); 1272 (start_index - ((start_index / 32) * 32));
1228 efuse_param.sEfuse.ucBitLength = (uint8_t) 1273 efuse_param.sEfuse.ucBitLength = (uint8_t)
@@ -1232,19 +1277,21 @@ int atomctrl_read_efuse(void *device, uint16_t start_index,
1232 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), 1277 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
1233 &efuse_param); 1278 &efuse_param);
1234 if (!result) 1279 if (!result)
1235 *efuse = efuse_param.ulEfuseValue & mask; 1280 *efuse = le32_to_cpu(efuse_param.ulEfuseValue) & mask;
1236 1281
1237 return result; 1282 return result;
1238} 1283}
1239 1284
1240int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, 1285int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
1241 uint8_t level) 1286 uint8_t level)
1242{ 1287{
1243 DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters; 1288 DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters;
1244 int result; 1289 int result;
1245 1290
1246 memory_clock_parameters.asDPMMCReg.ulClock.ulClockFreq = memory_clock & SET_CLOCK_FREQ_MASK; 1291 memory_clock_parameters.asDPMMCReg.ulClock.ulClockFreq =
1247 memory_clock_parameters.asDPMMCReg.ulClock.ulComputeClockFlag = ADJUST_MC_SETTING_PARAM; 1292 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK);
1293 memory_clock_parameters.asDPMMCReg.ulClock.ulComputeClockFlag =
1294 cpu_to_le32(ADJUST_MC_SETTING_PARAM);
1248 memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level; 1295 memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level;
1249 1296
1250 result = cgs_atom_exec_cmd_table 1297 result = cgs_atom_exec_cmd_table
@@ -1264,8 +1311,8 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_
1264 1311
1265 get_voltage_info_param_space.ucVoltageType = voltage_type; 1312 get_voltage_info_param_space.ucVoltageType = voltage_type;
1266 get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 1313 get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1267 get_voltage_info_param_space.usVoltageLevel = virtual_voltage_Id; 1314 get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_Id);
1268 get_voltage_info_param_space.ulSCLKFreq = sclk; 1315 get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk);
1269 1316
1270 result = cgs_atom_exec_cmd_table(hwmgr->device, 1317 result = cgs_atom_exec_cmd_table(hwmgr->device,
1271 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo), 1318 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
@@ -1274,7 +1321,7 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_
1274 if (0 != result) 1321 if (0 != result)
1275 return result; 1322 return result;
1276 1323
1277 *voltage = ((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel; 1324 *voltage = le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel);
1278 1325
1279 return result; 1326 return result;
1280} 1327}
@@ -1295,15 +1342,19 @@ int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctr
1295 for (i = 0; i < psmu_info->ucSclkEntryNum; i++) { 1342 for (i = 0; i < psmu_info->ucSclkEntryNum; i++) {
1296 table->entry[i].ucVco_setting = psmu_info->asSclkFcwRangeEntry[i].ucVco_setting; 1343 table->entry[i].ucVco_setting = psmu_info->asSclkFcwRangeEntry[i].ucVco_setting;
1297 table->entry[i].ucPostdiv = psmu_info->asSclkFcwRangeEntry[i].ucPostdiv; 1344 table->entry[i].ucPostdiv = psmu_info->asSclkFcwRangeEntry[i].ucPostdiv;
1298 table->entry[i].usFcw_pcc = psmu_info->asSclkFcwRangeEntry[i].ucFcw_pcc; 1345 table->entry[i].usFcw_pcc =
1299 table->entry[i].usFcw_trans_upper = psmu_info->asSclkFcwRangeEntry[i].ucFcw_trans_upper; 1346 le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucFcw_pcc);
1300 table->entry[i].usRcw_trans_lower = psmu_info->asSclkFcwRangeEntry[i].ucRcw_trans_lower; 1347 table->entry[i].usFcw_trans_upper =
1348 le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucFcw_trans_upper);
1349 table->entry[i].usRcw_trans_lower =
1350 le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucRcw_trans_lower);
1301 } 1351 }
1302 1352
1303 return 0; 1353 return 0;
1304} 1354}
1305 1355
1306int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param) 1356int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
1357 struct pp_atom_ctrl__avfs_parameters *param)
1307{ 1358{
1308 ATOM_ASIC_PROFILING_INFO_V3_6 *profile = NULL; 1359 ATOM_ASIC_PROFILING_INFO_V3_6 *profile = NULL;
1309 1360
@@ -1317,30 +1368,30 @@ int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__a
1317 if (!profile) 1368 if (!profile)
1318 return -1; 1369 return -1;
1319 1370
1320 param->ulAVFS_meanNsigma_Acontant0 = profile->ulAVFS_meanNsigma_Acontant0; 1371 param->ulAVFS_meanNsigma_Acontant0 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant0);
1321 param->ulAVFS_meanNsigma_Acontant1 = profile->ulAVFS_meanNsigma_Acontant1; 1372 param->ulAVFS_meanNsigma_Acontant1 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant1);
1322 param->ulAVFS_meanNsigma_Acontant2 = profile->ulAVFS_meanNsigma_Acontant2; 1373 param->ulAVFS_meanNsigma_Acontant2 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant2);
1323 param->usAVFS_meanNsigma_DC_tol_sigma = profile->usAVFS_meanNsigma_DC_tol_sigma; 1374 param->usAVFS_meanNsigma_DC_tol_sigma = le16_to_cpu(profile->usAVFS_meanNsigma_DC_tol_sigma);
1324 param->usAVFS_meanNsigma_Platform_mean = profile->usAVFS_meanNsigma_Platform_mean; 1375 param->usAVFS_meanNsigma_Platform_mean = le16_to_cpu(profile->usAVFS_meanNsigma_Platform_mean);
1325 param->usAVFS_meanNsigma_Platform_sigma = profile->usAVFS_meanNsigma_Platform_sigma; 1376 param->usAVFS_meanNsigma_Platform_sigma = le16_to_cpu(profile->usAVFS_meanNsigma_Platform_sigma);
1326 param->ulGB_VDROOP_TABLE_CKSOFF_a0 = profile->ulGB_VDROOP_TABLE_CKSOFF_a0; 1377 param->ulGB_VDROOP_TABLE_CKSOFF_a0 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a0);
1327 param->ulGB_VDROOP_TABLE_CKSOFF_a1 = profile->ulGB_VDROOP_TABLE_CKSOFF_a1; 1378 param->ulGB_VDROOP_TABLE_CKSOFF_a1 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a1);
1328 param->ulGB_VDROOP_TABLE_CKSOFF_a2 = profile->ulGB_VDROOP_TABLE_CKSOFF_a2; 1379 param->ulGB_VDROOP_TABLE_CKSOFF_a2 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a2);
1329 param->ulGB_VDROOP_TABLE_CKSON_a0 = profile->ulGB_VDROOP_TABLE_CKSON_a0; 1380 param->ulGB_VDROOP_TABLE_CKSON_a0 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a0);
1330 param->ulGB_VDROOP_TABLE_CKSON_a1 = profile->ulGB_VDROOP_TABLE_CKSON_a1; 1381 param->ulGB_VDROOP_TABLE_CKSON_a1 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a1);
1331 param->ulGB_VDROOP_TABLE_CKSON_a2 = profile->ulGB_VDROOP_TABLE_CKSON_a2; 1382 param->ulGB_VDROOP_TABLE_CKSON_a2 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a2);
1332 param->ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = profile->ulAVFSGB_FUSE_TABLE_CKSOFF_m1; 1383 param->ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1333 param->usAVFSGB_FUSE_TABLE_CKSOFF_m2 = profile->usAVFSGB_FUSE_TABLE_CKSOFF_m2; 1384 param->usAVFSGB_FUSE_TABLE_CKSOFF_m2 = le16_to_cpu(profile->usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1334 param->ulAVFSGB_FUSE_TABLE_CKSOFF_b = profile->ulAVFSGB_FUSE_TABLE_CKSOFF_b; 1385 param->ulAVFSGB_FUSE_TABLE_CKSOFF_b = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1335 param->ulAVFSGB_FUSE_TABLE_CKSON_m1 = profile->ulAVFSGB_FUSE_TABLE_CKSON_m1; 1386 param->ulAVFSGB_FUSE_TABLE_CKSON_m1 = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSON_m1);
1336 param->usAVFSGB_FUSE_TABLE_CKSON_m2 = profile->usAVFSGB_FUSE_TABLE_CKSON_m2; 1387 param->usAVFSGB_FUSE_TABLE_CKSON_m2 = le16_to_cpu(profile->usAVFSGB_FUSE_TABLE_CKSON_m2);
1337 param->ulAVFSGB_FUSE_TABLE_CKSON_b = profile->ulAVFSGB_FUSE_TABLE_CKSON_b; 1388 param->ulAVFSGB_FUSE_TABLE_CKSON_b = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSON_b);
1338 param->usMaxVoltage_0_25mv = profile->usMaxVoltage_0_25mv; 1389 param->usMaxVoltage_0_25mv = le16_to_cpu(profile->usMaxVoltage_0_25mv);
1339 param->ucEnableGB_VDROOP_TABLE_CKSOFF = profile->ucEnableGB_VDROOP_TABLE_CKSOFF; 1390 param->ucEnableGB_VDROOP_TABLE_CKSOFF = profile->ucEnableGB_VDROOP_TABLE_CKSOFF;
1340 param->ucEnableGB_VDROOP_TABLE_CKSON = profile->ucEnableGB_VDROOP_TABLE_CKSON; 1391 param->ucEnableGB_VDROOP_TABLE_CKSON = profile->ucEnableGB_VDROOP_TABLE_CKSON;
1341 param->ucEnableGB_FUSE_TABLE_CKSOFF = profile->ucEnableGB_FUSE_TABLE_CKSOFF; 1392 param->ucEnableGB_FUSE_TABLE_CKSOFF = profile->ucEnableGB_FUSE_TABLE_CKSOFF;
1342 param->ucEnableGB_FUSE_TABLE_CKSON = profile->ucEnableGB_FUSE_TABLE_CKSON; 1393 param->ucEnableGB_FUSE_TABLE_CKSON = profile->ucEnableGB_FUSE_TABLE_CKSON;
1343 param->usPSM_Age_ComFactor = profile->usPSM_Age_ComFactor; 1394 param->usPSM_Age_ComFactor = le16_to_cpu(profile->usPSM_Age_ComFactor);
1344 param->ucEnableApplyAVFS_CKS_OFF_Voltage = profile->ucEnableApplyAVFS_CKS_OFF_Voltage; 1395 param->ucEnableApplyAVFS_CKS_OFF_Voltage = profile->ucEnableApplyAVFS_CKS_OFF_Voltage;
1345 1396
1346 return 0; 1397 return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
index 1e35a9625baf..fc898afce002 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
@@ -281,6 +281,7 @@ struct pp_atom_ctrl__avfs_parameters {
281 281
282extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment); 282extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
283extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); 283extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
284extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage);
284extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr); 285extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
285extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo); 286extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
286extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo); 287extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index 35bc8a29b773..6c321b0d8a1e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -810,6 +810,19 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
810 return (const ATOM_PPLIB_POWERPLAYTABLE *)table_addr; 810 return (const ATOM_PPLIB_POWERPLAYTABLE *)table_addr;
811} 811}
812 812
813int pp_tables_get_response_times(struct pp_hwmgr *hwmgr,
814 uint32_t *vol_rep_time, uint32_t *bb_rep_time)
815{
816 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_tab = get_powerplay_table(hwmgr);
817
818 PP_ASSERT_WITH_CODE(NULL != powerplay_tab,
819 "Missing PowerPlay Table!", return -EINVAL);
820
821 *vol_rep_time = (uint32_t)le16_to_cpu(powerplay_tab->usVoltageTime);
822 *bb_rep_time = (uint32_t)le16_to_cpu(powerplay_tab->usBackbiasTime);
823
824 return 0;
825}
813 826
814int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr, 827int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,
815 unsigned long *num_of_entries) 828 unsigned long *num_of_entries)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h
index 30434802417e..baddaa75693b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h
@@ -32,16 +32,19 @@ struct pp_hw_power_state;
32extern const struct pp_table_func pptable_funcs; 32extern const struct pp_table_func pptable_funcs;
33 33
34typedef int (*pp_tables_hw_clock_info_callback)(struct pp_hwmgr *hwmgr, 34typedef int (*pp_tables_hw_clock_info_callback)(struct pp_hwmgr *hwmgr,
35 struct pp_hw_power_state *hw_ps, 35 struct pp_hw_power_state *hw_ps,
36 unsigned int index, 36 unsigned int index,
37 const void *clock_info); 37 const void *clock_info);
38 38
39int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr, 39int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,
40 unsigned long *num_of_entries); 40 unsigned long *num_of_entries);
41 41
42int pp_tables_get_entry(struct pp_hwmgr *hwmgr, 42int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
43 unsigned long entry_index, 43 unsigned long entry_index,
44 struct pp_power_state *ps, 44 struct pp_power_state *ps,
45 pp_tables_hw_clock_info_callback func); 45 pp_tables_hw_clock_info_callback func);
46
47int pp_tables_get_response_times(struct pp_hwmgr *hwmgr,
48 uint32_t *vol_rep_time, uint32_t *bb_rep_time);
46 49
47#endif 50#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index fc9e3d1dd409..3c235f0177cd 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -131,6 +131,12 @@ extern int smu_free_memory(void *device, void *handle);
131 smum_wait_on_indirect_register(smumgr, \ 131 smum_wait_on_indirect_register(smumgr, \
132 mm##port##_INDEX, index, value, mask) 132 mm##port##_INDEX, index, value, mask)
133 133
134#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
135 SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
136
137#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
138 SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
139 SMUM_FIELD_MASK(reg, field) )
134 140
135#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ 141#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
136 index, value, mask) \ 142 index, value, mask) \
@@ -158,6 +164,10 @@ extern int smu_free_memory(void *device, void *handle);
158 (SMUM_FIELD_MASK(reg, field) & ((field_val) << \ 164 (SMUM_FIELD_MASK(reg, field) & ((field_val) << \
159 SMUM_FIELD_SHIFT(reg, field)))) 165 SMUM_FIELD_SHIFT(reg, field))))
160 166
167#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
168 SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
169 reg, field)
170
161#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \ 171#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
162 port, index, value, mask) \ 172 port, index, value, mask) \
163 smum_wait_on_indirect_register(smumgr, \ 173 smum_wait_on_indirect_register(smumgr, \
@@ -191,6 +201,13 @@ extern int smu_free_memory(void *device, void *handle);
191 SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 201 SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
192 reg, field, fieldval)) 202 reg, field, fieldval))
193 203
204
205#define SMUM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
206 cgs_write_ind_register(device, port, ix##reg, \
207 SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
208 reg, field, fieldval))
209
210
194#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \ 211#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
195 SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \ 212 SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \
196 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ 213 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
@@ -200,4 +217,16 @@ extern int smu_free_memory(void *device, void *handle);
200 SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \ 217 SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \
201 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ 218 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
202 SMUM_FIELD_MASK(reg, field)) 219 SMUM_FIELD_MASK(reg, field))
220
221#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask) \
222 smum_wait_for_indirect_register_unequal(smumgr, \
223 mm##port##_INDEX, index, value, mask)
224
225#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
226 SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
227
228#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
229 SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
230 SMUM_FIELD_MASK(reg, field) )
231
203#endif 232#endif
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 587cae4e73c9..56bb758f4e33 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -120,6 +120,7 @@ atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
123 if (dig->backlight_level == 0) 124 if (dig->backlight_level == 0)
124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125 else { 126 else {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 11:04:40 -0400