diff options
author | Rajendra Nayak <rnayak@codeaurora.org> | 2018-03-07 00:00:02 -0500 |
---|---|---|
committer | Andy Gross <andy.gross@linaro.org> | 2018-03-08 19:36:33 -0500 |
commit | 15ee8f021d9bd64a124829cbe1794491ed070444 (patch) | |
tree | b872b68f184d6e37d2f2c217561d2c63a7aa1ec5 | |
parent | 68ae3d0cac449136407fca8dc7ad2078341d67de (diff) |
arm64: dts: msm8916: Add cpu cooling maps
Add cpu cooling maps for cpu passive trip points. The cpu cooling
device states are mapped to cpufreq based scaling frequencies.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
-rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e4682779eec7..66b318e1de80 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <dt-bindings/clock/qcom,gcc-msm8916.h> | 15 | #include <dt-bindings/clock/qcom,gcc-msm8916.h> |
16 | #include <dt-bindings/reset/qcom,gcc-msm8916.h> | 16 | #include <dt-bindings/reset/qcom,gcc-msm8916.h> |
17 | #include <dt-bindings/clock/qcom,rpmcc.h> | 17 | #include <dt-bindings/clock/qcom,rpmcc.h> |
18 | #include <dt-bindings/thermal/thermal.h> | ||
18 | 19 | ||
19 | / { | 20 | / { |
20 | model = "Qualcomm Technologies, Inc. MSM8916"; | 21 | model = "Qualcomm Technologies, Inc. MSM8916"; |
@@ -115,6 +116,7 @@ | |||
115 | cpu-idle-states = <&CPU_SPC>; | 116 | cpu-idle-states = <&CPU_SPC>; |
116 | clocks = <&apcs 0>; | 117 | clocks = <&apcs 0>; |
117 | operating-points-v2 = <&cpu_opp_table>; | 118 | operating-points-v2 = <&cpu_opp_table>; |
119 | #cooling-cells = <2>; | ||
118 | }; | 120 | }; |
119 | 121 | ||
120 | CPU1: cpu@1 { | 122 | CPU1: cpu@1 { |
@@ -126,6 +128,7 @@ | |||
126 | cpu-idle-states = <&CPU_SPC>; | 128 | cpu-idle-states = <&CPU_SPC>; |
127 | clocks = <&apcs 0>; | 129 | clocks = <&apcs 0>; |
128 | operating-points-v2 = <&cpu_opp_table>; | 130 | operating-points-v2 = <&cpu_opp_table>; |
131 | #cooling-cells = <2>; | ||
129 | }; | 132 | }; |
130 | 133 | ||
131 | CPU2: cpu@2 { | 134 | CPU2: cpu@2 { |
@@ -137,6 +140,7 @@ | |||
137 | cpu-idle-states = <&CPU_SPC>; | 140 | cpu-idle-states = <&CPU_SPC>; |
138 | clocks = <&apcs 0>; | 141 | clocks = <&apcs 0>; |
139 | operating-points-v2 = <&cpu_opp_table>; | 142 | operating-points-v2 = <&cpu_opp_table>; |
143 | #cooling-cells = <2>; | ||
140 | }; | 144 | }; |
141 | 145 | ||
142 | CPU3: cpu@3 { | 146 | CPU3: cpu@3 { |
@@ -148,6 +152,7 @@ | |||
148 | cpu-idle-states = <&CPU_SPC>; | 152 | cpu-idle-states = <&CPU_SPC>; |
149 | clocks = <&apcs 0>; | 153 | clocks = <&apcs 0>; |
150 | operating-points-v2 = <&cpu_opp_table>; | 154 | operating-points-v2 = <&cpu_opp_table>; |
155 | #cooling-cells = <2>; | ||
151 | }; | 156 | }; |
152 | 157 | ||
153 | L2_0: l2-cache { | 158 | L2_0: l2-cache { |
@@ -196,6 +201,13 @@ | |||
196 | type = "critical"; | 201 | type = "critical"; |
197 | }; | 202 | }; |
198 | }; | 203 | }; |
204 | |||
205 | cooling-maps { | ||
206 | map0 { | ||
207 | trip = <&cpu_alert0>; | ||
208 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | ||
209 | }; | ||
210 | }; | ||
199 | }; | 211 | }; |
200 | 212 | ||
201 | cpu-thermal1 { | 213 | cpu-thermal1 { |
@@ -216,6 +228,13 @@ | |||
216 | type = "critical"; | 228 | type = "critical"; |
217 | }; | 229 | }; |
218 | }; | 230 | }; |
231 | |||
232 | cooling-maps { | ||
233 | map0 { | ||
234 | trip = <&cpu_alert1>; | ||
235 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | ||
236 | }; | ||
237 | }; | ||
219 | }; | 238 | }; |
220 | 239 | ||
221 | }; | 240 | }; |