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authorNiklas Cassel <niklas.cassel@axis.com>2018-02-26 16:47:06 -0500
committerDavid S. Miller <davem@davemloft.net>2018-02-27 14:28:10 -0500
commit15d2ee42a3087089e73ad52fd8c1b37ab496b87c (patch)
tree4398ff013da49baba0df9d3ff5ef1a56816a7c15
parentf4155eff1f27076467826cf9bf77723277ead2ec (diff)
net: stmmac: ensure that the MSS desc is the last desc to set the own bit
A dma_wmb() is used to guarantee the ordering, with respect to other writes, to cache coherent DMA memory. There is a dma_wmb() in prepare_tx_desc()/prepare_tso_tx_desc() which ensures that TDES0/1/2 is written before TDES3 (which contains the own bit), for First Desc. However, in the rare case that MSS changes, there will be a MSS context descriptor in front of the regular DMA descriptors: <MSS desc> <- DMA Next Descriptor <First Desc> <desc n> <Last Desc> Thus, for this special case, we need a dma_wmb() after prepare_tso_tx_desc()/before writing the own bit to the MSS desc, so that we flush the write to TDES3 for First Desc, in order to ensure that the MSS descriptor is the last descriptor to set the own bit. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_main.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index c8d86d77e03d..3b5e7b06e796 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2983,8 +2983,15 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2983 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 2983 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2984 2984
2985 /* If context desc is used to change MSS */ 2985 /* If context desc is used to change MSS */
2986 if (mss_desc) 2986 if (mss_desc) {
2987 /* Make sure that first descriptor has been completely
2988 * written, including its own bit. This is because MSS is
2989 * actually before first descriptor, so we need to make
2990 * sure that MSS's own bit is the last thing written.
2991 */
2992 dma_wmb();
2987 priv->hw->desc->set_tx_owner(mss_desc); 2993 priv->hw->desc->set_tx_owner(mss_desc);
2994 }
2988 2995
2989 /* The own bit must be the latest setting done when prepare the 2996 /* The own bit must be the latest setting done when prepare the
2990 * descriptor and then barrier is needed to make sure that 2997 * descriptor and then barrier is needed to make sure that