Merge branch 'for-joerg/arm-smmu/updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu

2 files changed, 292 insertions, 317 deletions

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 3f2f1fc68b52..1d647104bccc 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -22,6 +22,8 @@
 
 #include <linux/acpi.h>
 #include <linux/acpi_iort.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/dma-iommu.h>
 #include <linux/err.h>
@@ -43,18 +45,15 @@
 
 /* MMIO registers */
 #define ARM_SMMU_IDR0                   0x0
-#define IDR0_ST_LVL_SHIFT               27
-#define IDR0_ST_LVL_MASK                0x3
-#define IDR0_ST_LVL_2LVL                (1 << IDR0_ST_LVL_SHIFT)
-#define IDR0_STALL_MODEL_SHIFT          24
-#define IDR0_STALL_MODEL_MASK           0x3
-#define IDR0_STALL_MODEL_STALL          (0 << IDR0_STALL_MODEL_SHIFT)
-#define IDR0_STALL_MODEL_FORCE          (2 << IDR0_STALL_MODEL_SHIFT)
-#define IDR0_TTENDIAN_SHIFT             21
-#define IDR0_TTENDIAN_MASK              0x3
-#define IDR0_TTENDIAN_LE                (2 << IDR0_TTENDIAN_SHIFT)
-#define IDR0_TTENDIAN_BE                (3 << IDR0_TTENDIAN_SHIFT)
-#define IDR0_TTENDIAN_MIXED             (0 << IDR0_TTENDIAN_SHIFT)
+#define IDR0_ST_LVL                     GENMASK(28, 27)
+#define IDR0_ST_LVL_2LVL                1
+#define IDR0_STALL_MODEL                GENMASK(25, 24)
+#define IDR0_STALL_MODEL_STALL          0
+#define IDR0_STALL_MODEL_FORCE          2
+#define IDR0_TTENDIAN                   GENMASK(22, 21)
+#define IDR0_TTENDIAN_MIXED             0
+#define IDR0_TTENDIAN_LE                2
+#define IDR0_TTENDIAN_BE                3
 #define IDR0_CD2L                       (1 << 19)
 #define IDR0_VMID16                     (1 << 18)
 #define IDR0_PRI                        (1 << 16)
@@ -64,10 +63,9 @@
 #define IDR0_ATS                        (1 << 10)
 #define IDR0_HYP                        (1 << 9)
 #define IDR0_COHACC                     (1 << 4)
-#define IDR0_TTF_SHIFT                  2
-#define IDR0_TTF_MASK                   0x3
-#define IDR0_TTF_AARCH64                (2 << IDR0_TTF_SHIFT)
-#define IDR0_TTF_AARCH32_64             (3 << IDR0_TTF_SHIFT)
+#define IDR0_TTF                        GENMASK(3, 2)
+#define IDR0_TTF_AARCH64                2
+#define IDR0_TTF_AARCH32_64             3
 #define IDR0_S1P                        (1 << 1)
 #define IDR0_S2P                        (1 << 0)
 
@@ -75,31 +73,27 @@
 #define IDR1_TABLES_PRESET              (1 << 30)
 #define IDR1_QUEUES_PRESET              (1 << 29)
 #define IDR1_REL                        (1 << 28)
-#define IDR1_CMDQ_SHIFT                 21
-#define IDR1_CMDQ_MASK                  0x1f
-#define IDR1_EVTQ_SHIFT                 16
-#define IDR1_EVTQ_MASK                  0x1f
-#define IDR1_PRIQ_SHIFT                 11
-#define IDR1_PRIQ_MASK                  0x1f
-#define IDR1_SSID_SHIFT                 6
-#define IDR1_SSID_MASK                  0x1f
-#define IDR1_SID_SHIFT                  0
-#define IDR1_SID_MASK                   0x3f
+#define IDR1_CMDQS                      GENMASK(25, 21)
+#define IDR1_EVTQS                      GENMASK(20, 16)
+#define IDR1_PRIQS                      GENMASK(15, 11)
+#define IDR1_SSIDSIZE                   GENMASK(10, 6)
+#define IDR1_SIDSIZE                    GENMASK(5, 0)
 
 #define ARM_SMMU_IDR5                   0x14
-#define IDR5_STALL_MAX_SHIFT            16
-#define IDR5_STALL_MAX_MASK             0xffff
+#define IDR5_STALL_MAX                  GENMASK(31, 16)
 #define IDR5_GRAN64K                    (1 << 6)
 #define IDR5_GRAN16K                    (1 << 5)
 #define IDR5_GRAN4K                     (1 << 4)
-#define IDR5_OAS_SHIFT                  0
-#define IDR5_OAS_MASK                   0x7
-#define IDR5_OAS_32_BIT                 (0 << IDR5_OAS_SHIFT)
-#define IDR5_OAS_36_BIT                 (1 << IDR5_OAS_SHIFT)
-#define IDR5_OAS_40_BIT                 (2 << IDR5_OAS_SHIFT)
-#define IDR5_OAS_42_BIT                 (3 << IDR5_OAS_SHIFT)
-#define IDR5_OAS_44_BIT                 (4 << IDR5_OAS_SHIFT)
-#define IDR5_OAS_48_BIT                 (5 << IDR5_OAS_SHIFT)
+#define IDR5_OAS                        GENMASK(2, 0)
+#define IDR5_OAS_32_BIT                 0
+#define IDR5_OAS_36_BIT                 1
+#define IDR5_OAS_40_BIT                 2
+#define IDR5_OAS_42_BIT                 3
+#define IDR5_OAS_44_BIT                 4
+#define IDR5_OAS_48_BIT                 5
+#define IDR5_OAS_52_BIT                 6
+#define IDR5_VAX                        GENMASK(11, 10)
+#define IDR5_VAX_52_BIT                 1
 
 #define ARM_SMMU_CR0                    0x20
 #define CR0_CMDQEN                      (1 << 3)
@@ -110,18 +104,16 @@
 #define ARM_SMMU_CR0ACK                 0x24
 
 #define ARM_SMMU_CR1                    0x28
-#define CR1_SH_NSH                      0
-#define CR1_SH_OSH                      2
-#define CR1_SH_ISH                      3
+#define CR1_TABLE_SH                    GENMASK(11, 10)
+#define CR1_TABLE_OC                    GENMASK(9, 8)
+#define CR1_TABLE_IC                    GENMASK(7, 6)
+#define CR1_QUEUE_SH                    GENMASK(5, 4)
+#define CR1_QUEUE_OC                    GENMASK(3, 2)
+#define CR1_QUEUE_IC                    GENMASK(1, 0)
+/* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
 #define CR1_CACHE_NC                    0
 #define CR1_CACHE_WB                    1
 #define CR1_CACHE_WT                    2
-#define CR1_TABLE_SH_SHIFT              10
-#define CR1_TABLE_OC_SHIFT              8
-#define CR1_TABLE_IC_SHIFT              6
-#define CR1_QUEUE_SH_SHIFT              4
-#define CR1_QUEUE_OC_SHIFT              2
-#define CR1_QUEUE_IC_SHIFT              0
 
 #define ARM_SMMU_CR2                    0x2c
 #define CR2_PTM                         (1 << 2)
@@ -129,8 +121,8 @@
 #define CR2_E2H                         (1 << 0)
 
 #define ARM_SMMU_GBPA                   0x44
-#define GBPA_ABORT                      (1 << 20)
 #define GBPA_UPDATE                     (1 << 31)
+#define GBPA_ABORT                      (1 << 20)
 
 #define ARM_SMMU_IRQ_CTRL               0x50
 #define IRQ_CTRL_EVTQ_IRQEN             (1 << 2)
@@ -158,18 +150,14 @@
 
 #define ARM_SMMU_STRTAB_BASE            0x80
 #define STRTAB_BASE_RA                  (1UL << 62)
-#define STRTAB_BASE_ADDR_SHIFT          6
-#define STRTAB_BASE_ADDR_MASK           0x3ffffffffffUL
+#define STRTAB_BASE_ADDR_MASK           GENMASK_ULL(51, 6)
 
 #define ARM_SMMU_STRTAB_BASE_CFG        0x88
-#define STRTAB_BASE_CFG_LOG2SIZE_SHIFT  0
-#define STRTAB_BASE_CFG_LOG2SIZE_MASK   0x3f
-#define STRTAB_BASE_CFG_SPLIT_SHIFT     6
-#define STRTAB_BASE_CFG_SPLIT_MASK      0x1f
-#define STRTAB_BASE_CFG_FMT_SHIFT       16
-#define STRTAB_BASE_CFG_FMT_MASK        0x3
-#define STRTAB_BASE_CFG_FMT_LINEAR      (0 << STRTAB_BASE_CFG_FMT_SHIFT)
-#define STRTAB_BASE_CFG_FMT_2LVL        (1 << STRTAB_BASE_CFG_FMT_SHIFT)
+#define STRTAB_BASE_CFG_FMT             GENMASK(17, 16)
+#define STRTAB_BASE_CFG_FMT_LINEAR      0
+#define STRTAB_BASE_CFG_FMT_2LVL        1
+#define STRTAB_BASE_CFG_SPLIT           GENMASK(10, 6)
+#define STRTAB_BASE_CFG_LOG2SIZE        GENMASK(5, 0)
 
 #define ARM_SMMU_CMDQ_BASE              0x90
 #define ARM_SMMU_CMDQ_PROD              0x98
@@ -190,14 +178,16 @@
 #define ARM_SMMU_PRIQ_IRQ_CFG2          0xdc
 
 /* Common MSI config fields */
-#define MSI_CFG0_ADDR_SHIFT             2
-#define MSI_CFG0_ADDR_MASK              0x3fffffffffffUL
-#define MSI_CFG2_SH_SHIFT               4
-#define MSI_CFG2_SH_NSH                 (0UL << MSI_CFG2_SH_SHIFT)
-#define MSI_CFG2_SH_OSH                 (2UL << MSI_CFG2_SH_SHIFT)
-#define MSI_CFG2_SH_ISH                 (3UL << MSI_CFG2_SH_SHIFT)
-#define MSI_CFG2_MEMATTR_SHIFT          0
-#define MSI_CFG2_MEMATTR_DEVICE_nGnRE   (0x1 << MSI_CFG2_MEMATTR_SHIFT)
+#define MSI_CFG0_ADDR_MASK              GENMASK_ULL(51, 2)
+#define MSI_CFG2_SH                     GENMASK(5, 4)
+#define MSI_CFG2_MEMATTR                GENMASK(3, 0)
+
+/* Common memory attribute values */
+#define ARM_SMMU_SH_NSH                 0
+#define ARM_SMMU_SH_OSH                 2
+#define ARM_SMMU_SH_ISH                 3
+#define ARM_SMMU_MEMATTR_DEVICE_nGnRE   0x1
+#define ARM_SMMU_MEMATTR_OIWB           0xf
 
 #define Q_IDX(q, p)                     ((p) & ((1 << (q)->max_n_shift) - 1))
 #define Q_WRP(q, p)                     ((p) & (1 << (q)->max_n_shift))
@@ -207,10 +197,8 @@
                                          Q_IDX(q, p) * (q)->ent_dwords)
 
 #define Q_BASE_RWA                      (1UL << 62)
-#define Q_BASE_ADDR_SHIFT               5
-#define Q_BASE_ADDR_MASK                0xfffffffffffUL
-#define Q_BASE_LOG2SIZE_SHIFT           0
-#define Q_BASE_LOG2SIZE_MASK            0x1fUL
+#define Q_BASE_ADDR_MASK                GENMASK_ULL(51, 5)
+#define Q_BASE_LOG2SIZE                 GENMASK(4, 0)
 
 /*
  * Stream table.
@@ -223,187 +211,143 @@
 #define STRTAB_SPLIT                    8
 
 #define STRTAB_L1_DESC_DWORDS           1
-#define STRTAB_L1_DESC_SPAN_SHIFT       0
-#define STRTAB_L1_DESC_SPAN_MASK        0x1fUL
-#define STRTAB_L1_DESC_L2PTR_SHIFT      6
-#define STRTAB_L1_DESC_L2PTR_MASK       0x3ffffffffffUL
+#define STRTAB_L1_DESC_SPAN             GENMASK_ULL(4, 0)
+#define STRTAB_L1_DESC_L2PTR_MASK       GENMASK_ULL(51, 6)
 
 #define STRTAB_STE_DWORDS               8
 #define STRTAB_STE_0_V                  (1UL << 0)
-#define STRTAB_STE_0_CFG_SHIFT          1
-#define STRTAB_STE_0_CFG_MASK           0x7UL
-#define STRTAB_STE_0_CFG_ABORT          (0UL << STRTAB_STE_0_CFG_SHIFT)
-#define STRTAB_STE_0_CFG_BYPASS         (4UL << STRTAB_STE_0_CFG_SHIFT)
-#define STRTAB_STE_0_CFG_S1_TRANS       (5UL << STRTAB_STE_0_CFG_SHIFT)
-#define STRTAB_STE_0_CFG_S2_TRANS       (6UL << STRTAB_STE_0_CFG_SHIFT)
-
-#define STRTAB_STE_0_S1FMT_SHIFT        4
-#define STRTAB_STE_0_S1FMT_LINEAR       (0UL << STRTAB_STE_0_S1FMT_SHIFT)
-#define STRTAB_STE_0_S1CTXPTR_SHIFT     6
-#define STRTAB_STE_0_S1CTXPTR_MASK      0x3ffffffffffUL
-#define STRTAB_STE_0_S1CDMAX_SHIFT      59
-#define STRTAB_STE_0_S1CDMAX_MASK       0x1fUL
+#define STRTAB_STE_0_CFG                GENMASK_ULL(3, 1)
+#define STRTAB_STE_0_CFG_ABORT          0
+#define STRTAB_STE_0_CFG_BYPASS         4
+#define STRTAB_STE_0_CFG_S1_TRANS       5
+#define STRTAB_STE_0_CFG_S2_TRANS       6
+
+#define STRTAB_STE_0_S1FMT              GENMASK_ULL(5, 4)
+#define STRTAB_STE_0_S1FMT_LINEAR       0
+#define STRTAB_STE_0_S1CTXPTR_MASK      GENMASK_ULL(51, 6)
+#define STRTAB_STE_0_S1CDMAX            GENMASK_ULL(63, 59)
 
 #define STRTAB_STE_1_S1C_CACHE_NC       0UL
 #define STRTAB_STE_1_S1C_CACHE_WBRA     1UL
 #define STRTAB_STE_1_S1C_CACHE_WT       2UL
 #define STRTAB_STE_1_S1C_CACHE_WB       3UL
-#define STRTAB_STE_1_S1C_SH_NSH         0UL
-#define STRTAB_STE_1_S1C_SH_OSH         2UL
-#define STRTAB_STE_1_S1C_SH_ISH         3UL
-#define STRTAB_STE_1_S1CIR_SHIFT        2
-#define STRTAB_STE_1_S1COR_SHIFT        4
-#define STRTAB_STE_1_S1CSH_SHIFT        6
+#define STRTAB_STE_1_S1CIR              GENMASK_ULL(3, 2)
+#define STRTAB_STE_1_S1COR              GENMASK_ULL(5, 4)
+#define STRTAB_STE_1_S1CSH              GENMASK_ULL(7, 6)
 
 #define STRTAB_STE_1_S1STALLD           (1UL << 27)
 
+#define STRTAB_STE_1_EATS               GENMASK_ULL(29, 28)
 #define STRTAB_STE_1_EATS_ABT           0UL
 #define STRTAB_STE_1_EATS_TRANS         1UL
 #define STRTAB_STE_1_EATS_S1CHK         2UL
-#define STRTAB_STE_1_EATS_SHIFT         28
 
+#define STRTAB_STE_1_STRW               GENMASK_ULL(31, 30)
 #define STRTAB_STE_1_STRW_NSEL1         0UL
 #define STRTAB_STE_1_STRW_EL2           2UL
-#define STRTAB_STE_1_STRW_SHIFT         30
 
+#define STRTAB_STE_1_SHCFG              GENMASK_ULL(45, 44)
 #define STRTAB_STE_1_SHCFG_INCOMING     1UL
-#define STRTAB_STE_1_SHCFG_SHIFT        44
 
-#define STRTAB_STE_2_S2VMID_SHIFT       0
-#define STRTAB_STE_2_S2VMID_MASK        0xffffUL
-#define STRTAB_STE_2_VTCR_SHIFT         32
-#define STRTAB_STE_2_VTCR_MASK          0x7ffffUL
+#define STRTAB_STE_2_S2VMID             GENMASK_ULL(15, 0)
+#define STRTAB_STE_2_VTCR               GENMASK_ULL(50, 32)
 #define STRTAB_STE_2_S2AA64             (1UL << 51)
 #define STRTAB_STE_2_S2ENDI             (1UL << 52)
 #define STRTAB_STE_2_S2PTW              (1UL << 54)
 #define STRTAB_STE_2_S2R                (1UL << 58)
 
-#define STRTAB_STE_3_S2TTB_SHIFT        4
-#define STRTAB_STE_3_S2TTB_MASK         0xfffffffffffUL
+#define STRTAB_STE_3_S2TTB_MASK         GENMASK_ULL(51, 4)
 
 /* Context descriptor (stage-1 only) */
 #define CTXDESC_CD_DWORDS               8
-#define CTXDESC_CD_0_TCR_T0SZ_SHIFT     0
-#define ARM64_TCR_T0SZ_SHIFT            0
-#define ARM64_TCR_T0SZ_MASK             0x1fUL
-#define CTXDESC_CD_0_TCR_TG0_SHIFT      6
-#define ARM64_TCR_TG0_SHIFT             14
-#define ARM64_TCR_TG0_MASK              0x3UL
-#define CTXDESC_CD_0_TCR_IRGN0_SHIFT    8
-#define ARM64_TCR_IRGN0_SHIFT           8
-#define ARM64_TCR_IRGN0_MASK            0x3UL
-#define CTXDESC_CD_0_TCR_ORGN0_SHIFT    10
-#define ARM64_TCR_ORGN0_SHIFT           10
-#define ARM64_TCR_ORGN0_MASK            0x3UL
-#define CTXDESC_CD_0_TCR_SH0_SHIFT      12
-#define ARM64_TCR_SH0_SHIFT             12
-#define ARM64_TCR_SH0_MASK              0x3UL
-#define CTXDESC_CD_0_TCR_EPD0_SHIFT     14
-#define ARM64_TCR_EPD0_SHIFT            7
-#define ARM64_TCR_EPD0_MASK             0x1UL
-#define CTXDESC_CD_0_TCR_EPD1_SHIFT     30
-#define ARM64_TCR_EPD1_SHIFT            23
-#define ARM64_TCR_EPD1_MASK             0x1UL
+#define CTXDESC_CD_0_TCR_T0SZ           GENMASK_ULL(5, 0)
+#define ARM64_TCR_T0SZ                  GENMASK_ULL(5, 0)
+#define CTXDESC_CD_0_TCR_TG0            GENMASK_ULL(7, 6)
+#define ARM64_TCR_TG0                   GENMASK_ULL(15, 14)
+#define CTXDESC_CD_0_TCR_IRGN0          GENMASK_ULL(9, 8)
+#define ARM64_TCR_IRGN0                 GENMASK_ULL(9, 8)
+#define CTXDESC_CD_0_TCR_ORGN0          GENMASK_ULL(11, 10)
+#define ARM64_TCR_ORGN0                 GENMASK_ULL(11, 10)
+#define CTXDESC_CD_0_TCR_SH0            GENMASK_ULL(13, 12)
+#define ARM64_TCR_SH0                   GENMASK_ULL(13, 12)
+#define CTXDESC_CD_0_TCR_EPD0           (1ULL << 14)
+#define ARM64_TCR_EPD0                  (1ULL << 7)
+#define CTXDESC_CD_0_TCR_EPD1           (1ULL << 30)
+#define ARM64_TCR_EPD1                  (1ULL << 23)
 
 #define CTXDESC_CD_0_ENDI               (1UL << 15)
 #define CTXDESC_CD_0_V                  (1UL << 31)
 
-#define CTXDESC_CD_0_TCR_IPS_SHIFT      32
-#define ARM64_TCR_IPS_SHIFT             32
-#define ARM64_TCR_IPS_MASK              0x7UL
-#define CTXDESC_CD_0_TCR_TBI0_SHIFT     38
-#define ARM64_TCR_TBI0_SHIFT            37
-#define ARM64_TCR_TBI0_MASK             0x1UL
+#define CTXDESC_CD_0_TCR_IPS            GENMASK_ULL(34, 32)
+#define ARM64_TCR_IPS                   GENMASK_ULL(34, 32)
+#define CTXDESC_CD_0_TCR_TBI0           (1ULL << 38)
+#define ARM64_TCR_TBI0                  (1ULL << 37)
 
 #define CTXDESC_CD_0_AA64               (1UL << 41)
 #define CTXDESC_CD_0_S                  (1UL << 44)
 #define CTXDESC_CD_0_R                  (1UL << 45)
 #define CTXDESC_CD_0_A                  (1UL << 46)
-#define CTXDESC_CD_0_ASET_SHIFT         47
-#define CTXDESC_CD_0_ASET_SHARED        (0UL << CTXDESC_CD_0_ASET_SHIFT)
-#define CTXDESC_CD_0_ASET_PRIVATE       (1UL << CTXDESC_CD_0_ASET_SHIFT)
-#define CTXDESC_CD_0_ASID_SHIFT         48
-#define CTXDESC_CD_0_ASID_MASK          0xffffUL
-
-#define CTXDESC_CD_1_TTB0_SHIFT         4
-#define CTXDESC_CD_1_TTB0_MASK          0xfffffffffffUL
+#define CTXDESC_CD_0_ASET               (1UL << 47)
+#define CTXDESC_CD_0_ASID               GENMASK_ULL(63, 48)
 
-#define CTXDESC_CD_3_MAIR_SHIFT         0
+#define CTXDESC_CD_1_TTB0_MASK          GENMASK_ULL(51, 4)
 
 /* Convert between AArch64 (CPU) TCR format and SMMU CD format */
-#define ARM_SMMU_TCR2CD(tcr, fld)                                       \
-        (((tcr) >> ARM64_TCR_##fld##_SHIFT & ARM64_TCR_##fld##_MASK)    \
-         << CTXDESC_CD_0_TCR_##fld##_SHIFT)
+#define ARM_SMMU_TCR2CD(tcr, fld)       FIELD_PREP(CTXDESC_CD_0_TCR_##fld, \
+                                        FIELD_GET(ARM64_TCR_##fld, tcr))
 
 /* Command queue */
 #define CMDQ_ENT_DWORDS                 2
 #define CMDQ_MAX_SZ_SHIFT               8
 
-#define CMDQ_ERR_SHIFT                  24
-#define CMDQ_ERR_MASK                   0x7f
+#define CMDQ_CONS_ERR                   GENMASK(30, 24)
 #define CMDQ_ERR_CERROR_NONE_IDX        0
 #define CMDQ_ERR_CERROR_ILL_IDX         1
 #define CMDQ_ERR_CERROR_ABT_IDX         2
 
-#define CMDQ_0_OP_SHIFT                 0
-#define CMDQ_0_OP_MASK                  0xffUL
+#define CMDQ_0_OP                       GENMASK_ULL(7, 0)
 #define CMDQ_0_SSV                      (1UL << 11)
 
-#define CMDQ_PREFETCH_0_SID_SHIFT       32
-#define CMDQ_PREFETCH_1_SIZE_SHIFT      0
-#define CMDQ_PREFETCH_1_ADDR_MASK       ~0xfffUL
+#define CMDQ_PREFETCH_0_SID             GENMASK_ULL(63, 32)
+#define CMDQ_PREFETCH_1_SIZE            GENMASK_ULL(4, 0)
+#define CMDQ_PREFETCH_1_ADDR_MASK       GENMASK_ULL(63, 12)
 
-#define CMDQ_CFGI_0_SID_SHIFT           32
-#define CMDQ_CFGI_0_SID_MASK            0xffffffffUL
+#define CMDQ_CFGI_0_SID                 GENMASK_ULL(63, 32)
 #define CMDQ_CFGI_1_LEAF                (1UL << 0)
-#define CMDQ_CFGI_1_RANGE_SHIFT         0
-#define CMDQ_CFGI_1_RANGE_MASK          0x1fUL
+#define CMDQ_CFGI_1_RANGE               GENMASK_ULL(4, 0)
 
-#define CMDQ_TLBI_0_VMID_SHIFT          32
-#define CMDQ_TLBI_0_ASID_SHIFT          48
+#define CMDQ_TLBI_0_VMID                GENMASK_ULL(47, 32)
+#define CMDQ_TLBI_0_ASID                GENMASK_ULL(63, 48)
 #define CMDQ_TLBI_1_LEAF                (1UL << 0)
-#define CMDQ_TLBI_1_VA_MASK             ~0xfffUL
-#define CMDQ_TLBI_1_IPA_MASK            0xfffffffff000UL
-
-#define CMDQ_PRI_0_SSID_SHIFT           12
-#define CMDQ_PRI_0_SSID_MASK            0xfffffUL
-#define CMDQ_PRI_0_SID_SHIFT            32
-#define CMDQ_PRI_0_SID_MASK             0xffffffffUL
-#define CMDQ_PRI_1_GRPID_SHIFT          0
-#define CMDQ_PRI_1_GRPID_MASK           0x1ffUL
-#define CMDQ_PRI_1_RESP_SHIFT           12
-#define CMDQ_PRI_1_RESP_DENY            (0UL << CMDQ_PRI_1_RESP_SHIFT)
-#define CMDQ_PRI_1_RESP_FAIL            (1UL << CMDQ_PRI_1_RESP_SHIFT)
-#define CMDQ_PRI_1_RESP_SUCC            (2UL << CMDQ_PRI_1_RESP_SHIFT)
-
-#define CMDQ_SYNC_0_CS_SHIFT            12
-#define CMDQ_SYNC_0_CS_NONE             (0UL << CMDQ_SYNC_0_CS_SHIFT)
-#define CMDQ_SYNC_0_CS_IRQ              (1UL << CMDQ_SYNC_0_CS_SHIFT)
-#define CMDQ_SYNC_0_CS_SEV              (2UL << CMDQ_SYNC_0_CS_SHIFT)
-#define CMDQ_SYNC_0_MSH_SHIFT           22
-#define CMDQ_SYNC_0_MSH_ISH             (3UL << CMDQ_SYNC_0_MSH_SHIFT)
-#define CMDQ_SYNC_0_MSIATTR_SHIFT       24
-#define CMDQ_SYNC_0_MSIATTR_OIWB        (0xfUL << CMDQ_SYNC_0_MSIATTR_SHIFT)
-#define CMDQ_SYNC_0_MSIDATA_SHIFT       32
-#define CMDQ_SYNC_0_MSIDATA_MASK        0xffffffffUL
-#define CMDQ_SYNC_1_MSIADDR_SHIFT       0
-#define CMDQ_SYNC_1_MSIADDR_MASK        0xffffffffffffcUL
+#define CMDQ_TLBI_1_VA_MASK             GENMASK_ULL(63, 12)
+#define CMDQ_TLBI_1_IPA_MASK            GENMASK_ULL(51, 12)
+
+#define CMDQ_PRI_0_SSID                 GENMASK_ULL(31, 12)
+#define CMDQ_PRI_0_SID                  GENMASK_ULL(63, 32)
+#define CMDQ_PRI_1_GRPID                GENMASK_ULL(8, 0)
+#define CMDQ_PRI_1_RESP                 GENMASK_ULL(13, 12)
+
+#define CMDQ_SYNC_0_CS                  GENMASK_ULL(13, 12)
+#define CMDQ_SYNC_0_CS_NONE             0
+#define CMDQ_SYNC_0_CS_IRQ              1
+#define CMDQ_SYNC_0_CS_SEV              2
+#define CMDQ_SYNC_0_MSH                 GENMASK_ULL(23, 22)
+#define CMDQ_SYNC_0_MSIATTR             GENMASK_ULL(27, 24)
+#define CMDQ_SYNC_0_MSIDATA             GENMASK_ULL(63, 32)
+#define CMDQ_SYNC_1_MSIADDR_MASK        GENMASK_ULL(51, 2)
 
 /* Event queue */
 #define EVTQ_ENT_DWORDS                 4
 #define EVTQ_MAX_SZ_SHIFT               7
 
-#define EVTQ_0_ID_SHIFT                 0
-#define EVTQ_0_ID_MASK                  0xffUL
+#define EVTQ_0_ID                       GENMASK_ULL(7, 0)
 
 /* PRI queue */
 #define PRIQ_ENT_DWORDS                 2
 #define PRIQ_MAX_SZ_SHIFT               8
 
-#define PRIQ_0_SID_SHIFT                0
-#define PRIQ_0_SID_MASK                 0xffffffffUL
-#define PRIQ_0_SSID_SHIFT               32
-#define PRIQ_0_SSID_MASK                0xfffffUL
+#define PRIQ_0_SID                      GENMASK_ULL(31, 0)
+#define PRIQ_0_SSID                     GENMASK_ULL(51, 32)
 #define PRIQ_0_PERM_PRIV                (1UL << 58)
 #define PRIQ_0_PERM_EXEC                (1UL << 59)
 #define PRIQ_0_PERM_READ                (1UL << 60)
@@ -411,10 +355,8 @@
 #define PRIQ_0_PRG_LAST                 (1UL << 62)
 #define PRIQ_0_SSID_V                   (1UL << 63)
 
-#define PRIQ_1_PRG_IDX_SHIFT            0
-#define PRIQ_1_PRG_IDX_MASK             0x1ffUL
-#define PRIQ_1_ADDR_SHIFT               12
-#define PRIQ_1_ADDR_MASK                0xfffffffffffffUL
+#define PRIQ_1_PRG_IDX                  GENMASK_ULL(8, 0)
+#define PRIQ_1_ADDR_MASK                GENMASK_ULL(63, 12)
 
 /* High-level queue structures */
 #define ARM_SMMU_POLL_TIMEOUT_US        100
@@ -430,9 +372,9 @@ MODULE_PARM_DESC(disable_bypass,
         "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
 
 enum pri_resp {
-        PRI_RESP_DENY,
-        PRI_RESP_FAIL,
-        PRI_RESP_SUCC,
+        PRI_RESP_DENY = 0,
+        PRI_RESP_FAIL = 1,
+        PRI_RESP_SUCC = 2,
 };
 
 enum arm_smmu_msi_index {
@@ -611,6 +553,7 @@ struct arm_smmu_device {
 #define ARM_SMMU_FEAT_STALLS            (1 << 11)
 #define ARM_SMMU_FEAT_HYP               (1 << 12)
 #define ARM_SMMU_FEAT_STALL_FORCE       (1 << 13)
+#define ARM_SMMU_FEAT_VAX               (1 << 14)
         u32                             features;
 
 #define ARM_SMMU_OPT_SKIP_PREFETCH      (1 << 0)
@@ -836,67 +779,64 @@ static int queue_remove_raw(struct arm_smmu_queue *q, u64 *ent)
 static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
 {
         memset(cmd, 0, CMDQ_ENT_DWORDS << 3);
-        cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT;
+        cmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode);
 
         switch (ent->opcode) {
         case CMDQ_OP_TLBI_EL2_ALL:
         case CMDQ_OP_TLBI_NSNH_ALL:
                 break;
         case CMDQ_OP_PREFETCH_CFG:
-                cmd[0] |= (u64)ent->prefetch.sid << CMDQ_PREFETCH_0_SID_SHIFT;
-                cmd[1] |= ent->prefetch.size << CMDQ_PREFETCH_1_SIZE_SHIFT;
+                cmd[0] |= FIELD_PREP(CMDQ_PREFETCH_0_SID, ent->prefetch.sid);
+                cmd[1] |= FIELD_PREP(CMDQ_PREFETCH_1_SIZE, ent->prefetch.size);
                 cmd[1] |= ent->prefetch.addr & CMDQ_PREFETCH_1_ADDR_MASK;
                 break;
         case CMDQ_OP_CFGI_STE:
-                cmd[0] |= (u64)ent->cfgi.sid << CMDQ_CFGI_0_SID_SHIFT;
-                cmd[1] |= ent->cfgi.leaf ? CMDQ_CFGI_1_LEAF : 0;
+                cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);
+                cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf);
                 break;
         case CMDQ_OP_CFGI_ALL:
                 /* Cover the entire SID range */
-                cmd[1] |= CMDQ_CFGI_1_RANGE_MASK << CMDQ_CFGI_1_RANGE_SHIFT;
+                cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31);
                 break;
         case CMDQ_OP_TLBI_NH_VA:
-                cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;
-                cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;
+                cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);
+                cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);
                 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK;
                 break;
         case CMDQ_OP_TLBI_S2_IPA:
-                cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT;
-                cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;
+                cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);
+                cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);
                 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK;
                 break;
         case CMDQ_OP_TLBI_NH_ASID:
-                cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;
+                cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);
                 /* Fallthrough */
         case CMDQ_OP_TLBI_S12_VMALL:
-                cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT;
+                cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);
                 break;
         case CMDQ_OP_PRI_RESP:
-                cmd[0] |= ent->substream_valid ? CMDQ_0_SSV : 0;
-                cmd[0] |= ent->pri.ssid << CMDQ_PRI_0_SSID_SHIFT;
-                cmd[0] |= (u64)ent->pri.sid << CMDQ_PRI_0_SID_SHIFT;
-                cmd[1] |= ent->pri.grpid << CMDQ_PRI_1_GRPID_SHIFT;
+                cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid);
+                cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SSID, ent->pri.ssid);
+                cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SID, ent->pri.sid);
+                cmd[1] |= FIELD_PREP(CMDQ_PRI_1_GRPID, ent->pri.grpid);
                 switch (ent->pri.resp) {
                 case PRI_RESP_DENY:
-                        cmd[1] |= CMDQ_PRI_1_RESP_DENY;
-                        break;
                 case PRI_RESP_FAIL:
-                        cmd[1] |= CMDQ_PRI_1_RESP_FAIL;
-                        break;
                 case PRI_RESP_SUCC:
-                        cmd[1] |= CMDQ_PRI_1_RESP_SUCC;
                         break;
                 default:
                         return -EINVAL;
                 }
+                cmd[1] |= FIELD_PREP(CMDQ_PRI_1_RESP, ent->pri.resp);
                 break;
         case CMDQ_OP_CMD_SYNC:
                 if (ent->sync.msiaddr)
-                        cmd[0] |= CMDQ_SYNC_0_CS_IRQ;
+                        cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ);
                 else
-                        cmd[0] |= CMDQ_SYNC_0_CS_SEV;
-                cmd[0] |= CMDQ_SYNC_0_MSH_ISH | CMDQ_SYNC_0_MSIATTR_OIWB;
-                cmd[0] |= (u64)ent->sync.msidata << CMDQ_SYNC_0_MSIDATA_SHIFT;
+                        cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV);
+                cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH);
+                cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB);
+                cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIDATA, ent->sync.msidata);
                 cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK;
                 break;
         default:
@@ -918,7 +858,7 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
         u64 cmd[CMDQ_ENT_DWORDS];
         struct arm_smmu_queue *q = &smmu->cmdq.q;
         u32 cons = readl_relaxed(q->cons_reg);
-        u32 idx = cons >> CMDQ_ERR_SHIFT & CMDQ_ERR_MASK;
+        u32 idx = FIELD_GET(CMDQ_CONS_ERR, cons);
         struct arm_smmu_cmdq_ent cmd_sync = {
                 .opcode = CMDQ_OP_CMD_SYNC,
         };
@@ -1083,8 +1023,8 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
 #ifdef __BIG_ENDIAN
               CTXDESC_CD_0_ENDI |
 #endif
-              CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET_PRIVATE |
-              CTXDESC_CD_0_AA64 | (u64)cfg->cd.asid << CTXDESC_CD_0_ASID_SHIFT |
+              CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET |
+              CTXDESC_CD_0_AA64 | FIELD_PREP(CTXDESC_CD_0_ASID, cfg->cd.asid) |
               CTXDESC_CD_0_V;
 
         /* STALL_MODEL==0b10 && CD.S==0 is ILLEGAL */
@@ -1093,10 +1033,10 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
 
         cfg->cdptr[0] = cpu_to_le64(val);
 
-        val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK << CTXDESC_CD_1_TTB0_SHIFT;
+        val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK;
         cfg->cdptr[1] = cpu_to_le64(val);
 
-        cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair << CTXDESC_CD_3_MAIR_SHIFT);
+        cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair);
 }
 
 /* Stream table manipulation functions */
@@ -1105,10 +1045,8 @@ arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc)
 {
         u64 val = 0;
 
-        val |= (desc->span & STRTAB_L1_DESC_SPAN_MASK)
-                << STRTAB_L1_DESC_SPAN_SHIFT;
-        val |= desc->l2ptr_dma &
-               STRTAB_L1_DESC_L2PTR_MASK << STRTAB_L1_DESC_L2PTR_SHIFT;
+        val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span);
+        val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK;
 
         *dst = cpu_to_le64(val);
 }
@@ -1156,10 +1094,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
         };
 
         if (val & STRTAB_STE_0_V) {
-                u64 cfg;
-
-                cfg = val & STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT;
-                switch (cfg) {
+                switch (FIELD_GET(STRTAB_STE_0_CFG, val)) {
                 case STRTAB_STE_0_CFG_BYPASS:
                         break;
                 case STRTAB_STE_0_CFG_S1_TRANS:
@@ -1180,13 +1115,13 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
         /* Bypass/fault */
         if (!ste->assigned || !(ste->s1_cfg || ste->s2_cfg)) {
                 if (!ste->assigned && disable_bypass)
-                        val |= STRTAB_STE_0_CFG_ABORT;
+                        val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
                 else
-                        val |= STRTAB_STE_0_CFG_BYPASS;
+                        val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
 
                 dst[0] = cpu_to_le64(val);
-                dst[1] = cpu_to_le64(STRTAB_STE_1_SHCFG_INCOMING
-                         << STRTAB_STE_1_SHCFG_SHIFT);
+                dst[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
+                                                STRTAB_STE_1_SHCFG_INCOMING));
                 dst[2] = 0; /* Nuke the VMID */
                 /*
                  * The SMMU can perform negative caching, so we must sync
@@ -1200,41 +1135,36 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
         if (ste->s1_cfg) {
                 BUG_ON(ste_live);
                 dst[1] = cpu_to_le64(
-                         STRTAB_STE_1_S1C_CACHE_WBRA
-                         << STRTAB_STE_1_S1CIR_SHIFT |
-                         STRTAB_STE_1_S1C_CACHE_WBRA
-                         << STRTAB_STE_1_S1COR_SHIFT |
-                         STRTAB_STE_1_S1C_SH_ISH << STRTAB_STE_1_S1CSH_SHIFT |
+                         FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
+                         FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
+                         FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) |
 #ifdef CONFIG_PCI_ATS
-                         STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT |
+                         FIELD_PREP(STRTAB_STE_1_EATS, STRTAB_STE_1_EATS_TRANS) |
 #endif
-                         STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT);
+                         FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1));
 
                 if (smmu->features & ARM_SMMU_FEAT_STALLS &&
                    !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE))
                         dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
 
-                val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK
-                        << STRTAB_STE_0_S1CTXPTR_SHIFT) |
-                        STRTAB_STE_0_CFG_S1_TRANS;
+                val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) |
+                        FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS);
         }
 
         if (ste->s2_cfg) {
                 BUG_ON(ste_live);
                 dst[2] = cpu_to_le64(
-                         ste->s2_cfg->vmid << STRTAB_STE_2_S2VMID_SHIFT |
-                         (ste->s2_cfg->vtcr & STRTAB_STE_2_VTCR_MASK)
-                          << STRTAB_STE_2_VTCR_SHIFT |
+                         FIELD_PREP(STRTAB_STE_2_S2VMID, ste->s2_cfg->vmid) |
+                         FIELD_PREP(STRTAB_STE_2_VTCR, ste->s2_cfg->vtcr) |
 #ifdef __BIG_ENDIAN
                          STRTAB_STE_2_S2ENDI |
 #endif
                          STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |
                          STRTAB_STE_2_S2R);
 
-                dst[3] = cpu_to_le64(ste->s2_cfg->vttbr &
-                         STRTAB_STE_3_S2TTB_MASK << STRTAB_STE_3_S2TTB_SHIFT);
+                dst[3] = cpu_to_le64(ste->s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
 
-                val |= STRTAB_STE_0_CFG_S2_TRANS;
+                val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);
         }
 
         arm_smmu_sync_ste_for_sid(smmu, sid);
@@ -1295,7 +1225,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev)
 
         do {
                 while (!queue_remove_raw(q, evt)) {
-                        u8 id = evt[0] >> EVTQ_0_ID_SHIFT & EVTQ_0_ID_MASK;
+                        u8 id = FIELD_GET(EVTQ_0_ID, evt[0]);
 
                         dev_info(smmu->dev, "event 0x%02x received:\n", id);
                         for (i = 0; i < ARRAY_SIZE(evt); ++i)
@@ -1323,11 +1253,11 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)
         u16 grpid;
         bool ssv, last;
 
-        sid = evt[0] >> PRIQ_0_SID_SHIFT & PRIQ_0_SID_MASK;
-        ssv = evt[0] & PRIQ_0_SSID_V;
-        ssid = ssv ? evt[0] >> PRIQ_0_SSID_SHIFT & PRIQ_0_SSID_MASK : 0;
-        last = evt[0] & PRIQ_0_PRG_LAST;
-        grpid = evt[1] >> PRIQ_1_PRG_IDX_SHIFT & PRIQ_1_PRG_IDX_MASK;
+        sid = FIELD_GET(PRIQ_0_SID, evt[0]);
+        ssv = FIELD_GET(PRIQ_0_SSID_V, evt[0]);
+        ssid = ssv ? FIELD_GET(PRIQ_0_SSID, evt[0]) : 0;
+        last = FIELD_GET(PRIQ_0_PRG_LAST, evt[0]);
+        grpid = FIELD_GET(PRIQ_1_PRG_IDX, evt[1]);
 
         dev_info(smmu->dev, "unexpected PRI request received:\n");
         dev_info(smmu->dev,
@@ -1337,7 +1267,7 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)
                  evt[0] & PRIQ_0_PERM_READ ? "R" : "",
                  evt[0] & PRIQ_0_PERM_WRITE ? "W" : "",
                  evt[0] & PRIQ_0_PERM_EXEC ? "X" : "",
-                 evt[1] & PRIQ_1_ADDR_MASK << PRIQ_1_ADDR_SHIFT);
+                 evt[1] & PRIQ_1_ADDR_MASK);
 
         if (last) {
                 struct arm_smmu_cmdq_ent cmd = {
@@ -1664,7 +1594,8 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)
 
         switch (smmu_domain->stage) {
         case ARM_SMMU_DOMAIN_S1:
-                ias = VA_BITS;
+                ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48;
+                ias = min_t(unsigned long, ias, VA_BITS);
                 oas = smmu->ias;
                 fmt = ARM_64_LPAE_S1;
                 finalise_stage_fn = arm_smmu_domain_finalise_s1;
@@ -1696,7 +1627,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)
                 return -ENOMEM;
 
         domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
-        domain->geometry.aperture_end = (1UL << ias) - 1;
+        domain->geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1;
         domain->geometry.force_aperture = true;
 
         ret = finalise_stage_fn(smmu_domain, &pgtbl_cfg);
@@ -2102,9 +2033,8 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
         q->ent_dwords   = dwords;
 
         q->q_base  = Q_BASE_RWA;
-        q->q_base |= q->base_dma & Q_BASE_ADDR_MASK << Q_BASE_ADDR_SHIFT;
-        q->q_base |= (q->max_n_shift & Q_BASE_LOG2SIZE_MASK)
-                     << Q_BASE_LOG2SIZE_SHIFT;
+        q->q_base |= q->base_dma & Q_BASE_ADDR_MASK;
+        q->q_base |= FIELD_PREP(Q_BASE_LOG2SIZE, q->max_n_shift);
 
         q->prod = q->cons = 0;
         return 0;
@@ -2186,11 +2116,9 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
         cfg->strtab = strtab;
 
         /* Configure strtab_base_cfg for 2 levels */
-        reg  = STRTAB_BASE_CFG_FMT_2LVL;
-        reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK)
-                << STRTAB_BASE_CFG_LOG2SIZE_SHIFT;
-        reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK)
-                << STRTAB_BASE_CFG_SPLIT_SHIFT;
+        reg  = FIELD_PREP(STRTAB_BASE_CFG_FMT, STRTAB_BASE_CFG_FMT_2LVL);
+        reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, size);
+        reg |= FIELD_PREP(STRTAB_BASE_CFG_SPLIT, STRTAB_SPLIT);
         cfg->strtab_base_cfg = reg;
 
         return arm_smmu_init_l1_strtab(smmu);
@@ -2216,9 +2144,8 @@ static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu)
         cfg->num_l1_ents = 1 << smmu->sid_bits;
 
         /* Configure strtab_base_cfg for a linear table covering all SIDs */
-        reg  = STRTAB_BASE_CFG_FMT_LINEAR;
-        reg |= (smmu->sid_bits & STRTAB_BASE_CFG_LOG2SIZE_MASK)
-                << STRTAB_BASE_CFG_LOG2SIZE_SHIFT;
+        reg  = FIELD_PREP(STRTAB_BASE_CFG_FMT, STRTAB_BASE_CFG_FMT_LINEAR);
+        reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits);
         cfg->strtab_base_cfg = reg;
 
         arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents);
@@ -2239,8 +2166,7 @@ static int arm_smmu_init_strtab(struct arm_smmu_device *smmu)
                 return ret;
 
         /* Set the strtab base address */
-        reg  = smmu->strtab_cfg.strtab_dma &
-               STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT;
+        reg  = smmu->strtab_cfg.strtab_dma & STRTAB_BASE_ADDR_MASK;
         reg |= STRTAB_BASE_RA;
         smmu->strtab_cfg.strtab_base = reg;
 
@@ -2303,11 +2229,11 @@ static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
         phys_addr_t *cfg = arm_smmu_msi_cfg[desc->platform.msi_index];
 
         doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
-        doorbell &= MSI_CFG0_ADDR_MASK << MSI_CFG0_ADDR_SHIFT;
+        doorbell &= MSI_CFG0_ADDR_MASK;
 
         writeq_relaxed(doorbell, smmu->base + cfg[0]);
         writel_relaxed(msg->data, smmu->base + cfg[1]);
-        writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);
+        writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);
 }
 
 static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
@@ -2328,10 +2254,15 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
         if (!(smmu->features & ARM_SMMU_FEAT_MSI))
                 return;
 
+        if (!dev->msi_domain) {
+                dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\n");
+                return;
+        }
+
         /* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */
         ret = platform_msi_domain_alloc_irqs(dev, nvec, arm_smmu_write_msi_msg);
         if (ret) {
-                dev_warn(dev, "failed to allocate MSIs\n");
+                dev_warn(dev, "failed to allocate MSIs - falling back to wired irqs\n");
                 return;
         }
 
@@ -2370,6 +2301,8 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
                                                 "arm-smmu-v3-evtq", smmu);
                 if (ret < 0)
                         dev_warn(smmu->dev, "failed to enable evtq irq\n");
+        } else {
+                dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n");
         }
 
         irq = smmu->gerr_irq;
@@ -2378,6 +2311,8 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
                                        0, "arm-smmu-v3-gerror", smmu);
                 if (ret < 0)
                         dev_warn(smmu->dev, "failed to enable gerror irq\n");
+        } else {
+                dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n");
         }
 
         if (smmu->features & ARM_SMMU_FEAT_PRI) {
@@ -2391,6 +2326,8 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
                         if (ret < 0)
                                 dev_warn(smmu->dev,
                                          "failed to enable priq irq\n");
+                } else {
+                        dev_warn(smmu->dev, "no priq irq - PRI will be broken\n");
                 }
         }
 }
@@ -2463,12 +2400,12 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
                 return ret;
 
         /* CR1 (table and queue memory attributes) */
-        reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) |
-              (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) |
-              (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) |
-              (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) |
-              (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) |
-              (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT);
+        reg = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) |
+              FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) |
+              FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) |
+              FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) |
+              FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) |
+              FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB);
         writel_relaxed(reg, smmu->base + ARM_SMMU_CR1);
 
         /* CR2 (random crap) */
@@ -2578,7 +2515,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
         reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0);
 
         /* 2-level structures */
-        if ((reg & IDR0_ST_LVL_MASK << IDR0_ST_LVL_SHIFT) == IDR0_ST_LVL_2LVL)
+        if (FIELD_GET(IDR0_ST_LVL, reg) == IDR0_ST_LVL_2LVL)
                 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB;
 
         if (reg & IDR0_CD2L)
@@ -2589,7 +2526,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
          * We currently require the same endianness as the CPU, but this
          * could be changed later by adding a new IO_PGTABLE_QUIRK.
          */
-        switch (reg & IDR0_TTENDIAN_MASK << IDR0_TTENDIAN_SHIFT) {
+        switch (FIELD_GET(IDR0_TTENDIAN, reg)) {
         case IDR0_TTENDIAN_MIXED:
                 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE;
                 break;
@@ -2631,7 +2568,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
                 dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n",
                          coherent ? "true" : "false");
 
-        switch (reg & IDR0_STALL_MODEL_MASK << IDR0_STALL_MODEL_SHIFT) {
+        switch (FIELD_GET(IDR0_STALL_MODEL, reg)) {
         case IDR0_STALL_MODEL_FORCE:
                 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE;
                 /* Fallthrough */
@@ -2651,7 +2588,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
         }
 
         /* We only support the AArch64 table format at present */
-        switch (reg & IDR0_TTF_MASK << IDR0_TTF_SHIFT) {
+        switch (FIELD_GET(IDR0_TTF, reg)) {
         case IDR0_TTF_AARCH32_64:
                 smmu->ias = 40;
                 /* Fallthrough */
@@ -2674,22 +2611,22 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
         }
 
         /* Queue sizes, capped at 4k */
-        smmu->cmdq.q.max_n_shift = min((u32)CMDQ_MAX_SZ_SHIFT,
-                                       reg >> IDR1_CMDQ_SHIFT & IDR1_CMDQ_MASK);
+        smmu->cmdq.q.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT,
+                                         FIELD_GET(IDR1_CMDQS, reg));
         if (!smmu->cmdq.q.max_n_shift) {
                 /* Odd alignment restrictions on the base, so ignore for now */
                 dev_err(smmu->dev, "unit-length command queue not supported\n");
                 return -ENXIO;
         }
 
-        smmu->evtq.q.max_n_shift = min((u32)EVTQ_MAX_SZ_SHIFT,
-                                       reg >> IDR1_EVTQ_SHIFT & IDR1_EVTQ_MASK);
-        smmu->priq.q.max_n_shift = min((u32)PRIQ_MAX_SZ_SHIFT,
-                                       reg >> IDR1_PRIQ_SHIFT & IDR1_PRIQ_MASK);
+        smmu->evtq.q.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT,
+                                         FIELD_GET(IDR1_EVTQS, reg));
+        smmu->priq.q.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT,
+                                         FIELD_GET(IDR1_PRIQS, reg));
 
         /* SID/SSID sizes */
-        smmu->ssid_bits = reg >> IDR1_SSID_SHIFT & IDR1_SSID_MASK;
-        smmu->sid_bits = reg >> IDR1_SID_SHIFT & IDR1_SID_MASK;
+        smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg);
+        smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg);
 
         /*
          * If the SMMU supports fewer bits than would fill a single L2 stream
@@ -2702,8 +2639,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
         reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5);
 
         /* Maximum number of outstanding stalls */
-        smmu->evtq.max_stalls = reg >> IDR5_STALL_MAX_SHIFT
-                                & IDR5_STALL_MAX_MASK;
+        smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg);
 
         /* Page sizes */
         if (reg & IDR5_GRAN64K)
@@ -2713,13 +2649,12 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
         if (reg & IDR5_GRAN4K)
                 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
 
-        if (arm_smmu_ops.pgsize_bitmap == -1UL)
-                arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
-        else
-                arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
+        /* Input address size */
+        if (FIELD_GET(IDR5_VAX, reg) == IDR5_VAX_52_BIT)
+                smmu->features |= ARM_SMMU_FEAT_VAX;
 
         /* Output address size */
-        switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) {
+        switch (FIELD_GET(IDR5_OAS, reg)) {
         case IDR5_OAS_32_BIT:
                 smmu->oas = 32;
                 break;
@@ -2735,6 +2670,10 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
         case IDR5_OAS_44_BIT:
                 smmu->oas = 44;
                 break;
+        case IDR5_OAS_52_BIT:
+                smmu->oas = 52;
+                smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */
+                break;
         default:
                 dev_info(smmu->dev,
                         "unknown output address size. Truncating to 48-bit\n");
@@ -2743,6 +2682,11 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
                 smmu->oas = 48;
         }
 
+        if (arm_smmu_ops.pgsize_bitmap == -1UL)
+                arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
+        else
+                arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
+
         /* Set the DMA mask for our table walker */
         if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas)))
                 dev_warn(smmu->dev,
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 51e5c43caed1..a5be4c92c5c8 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -21,6 +21,7 @@
 #define pr_fmt(fmt)     "arm-lpae io-pgtable: " fmt
 
 #include <linux/atomic.h>
+#include <linux/bitops.h>
 #include <linux/iommu.h>
 #include <linux/kernel.h>
 #include <linux/sizes.h>
@@ -32,7 +33,7 @@
 
 #include "io-pgtable.h"
 
-#define ARM_LPAE_MAX_ADDR_BITS          48
+#define ARM_LPAE_MAX_ADDR_BITS          52
 #define ARM_LPAE_S2_MAX_CONCAT_PAGES    16
 #define ARM_LPAE_MAX_LEVELS             4
 
@@ -86,6 +87,8 @@
 #define ARM_LPAE_PTE_TYPE_TABLE         3
 #define ARM_LPAE_PTE_TYPE_PAGE          3
 
+#define ARM_LPAE_PTE_ADDR_MASK          GENMASK_ULL(47,12)
+
 #define ARM_LPAE_PTE_NSTABLE            (((arm_lpae_iopte)1) << 63)
 #define ARM_LPAE_PTE_XN                 (((arm_lpae_iopte)3) << 53)
 #define ARM_LPAE_PTE_AF                 (((arm_lpae_iopte)1) << 10)
@@ -159,6 +162,7 @@
 #define ARM_LPAE_TCR_PS_42_BIT          0x3ULL
 #define ARM_LPAE_TCR_PS_44_BIT          0x4ULL
 #define ARM_LPAE_TCR_PS_48_BIT          0x5ULL
+#define ARM_LPAE_TCR_PS_52_BIT          0x6ULL
 
 #define ARM_LPAE_MAIR_ATTR_SHIFT(n)     ((n) << 3)
 #define ARM_LPAE_MAIR_ATTR_MASK         0xff
@@ -170,9 +174,7 @@
 #define ARM_LPAE_MAIR_ATTR_IDX_DEV      2
 
 /* IOPTE accessors */
-#define iopte_deref(pte,d)                                      \
-        (__va((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1)    \
-        & ~(ARM_LPAE_GRANULE(d) - 1ULL)))
+#define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
 
 #define iopte_type(pte,l)                                       \
         (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
@@ -184,12 +186,6 @@
                 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \
                 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK))
 
-#define iopte_to_pfn(pte,d)                                     \
-        (((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1)) >> (d)->pg_shift)
-
-#define pfn_to_iopte(pfn,d)                                     \
-        (((pfn) << (d)->pg_shift) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1))
-
 struct arm_lpae_io_pgtable {
         struct io_pgtable       iop;
 
@@ -203,6 +199,27 @@ struct arm_lpae_io_pgtable {
 
 typedef u64 arm_lpae_iopte;
 
+static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
+                                     struct arm_lpae_io_pgtable *data)
+{
+        arm_lpae_iopte pte = paddr;
+
+        /* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */
+        return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK;
+}
+
+static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte,
+                                  struct arm_lpae_io_pgtable *data)
+{
+        phys_addr_t paddr = pte & ARM_LPAE_PTE_ADDR_MASK;
+
+        if (data->pg_shift < 16)
+                return paddr;
+
+        /* Rotate the packed high-order bits back to the top */
+        return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4);
+}
+
 static bool selftest_running = false;
 
 static dma_addr_t __arm_lpae_dma_addr(void *pages)
@@ -287,7 +304,7 @@ static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
                 pte |= ARM_LPAE_PTE_TYPE_BLOCK;
 
         pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS;
-        pte |= pfn_to_iopte(paddr >> data->pg_shift, data);
+        pte |= paddr_to_iopte(paddr, data);
 
         __arm_lpae_set_pte(ptep, pte, &data->iop.cfg);
 }
@@ -528,7 +545,7 @@ static int arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
         if (size == split_sz)
                 unmap_idx = ARM_LPAE_LVL_IDX(iova, lvl, data);
 
-        blk_paddr = iopte_to_pfn(blk_pte, data) << data->pg_shift;
+        blk_paddr = iopte_to_paddr(blk_pte, data);
         pte = iopte_prot(blk_pte);
 
         for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) {
@@ -652,12 +669,13 @@ static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
 
 found_translation:
         iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
-        return ((phys_addr_t)iopte_to_pfn(pte,data) << data->pg_shift) | iova;
+        return iopte_to_paddr(pte, data) | iova;
 }
 
 static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
 {
-        unsigned long granule;
+        unsigned long granule, page_sizes;
+        unsigned int max_addr_bits = 48;
 
         /*
          * We need to restrict the supported page sizes to match the
@@ -677,17 +695,24 @@ static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
 
         switch (granule) {
         case SZ_4K:
-                cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
+                page_sizes = (SZ_4K | SZ_2M | SZ_1G);
                 break;
         case SZ_16K:
-                cfg->pgsize_bitmap &= (SZ_16K | SZ_32M);
+                page_sizes = (SZ_16K | SZ_32M);
                 break;
         case SZ_64K:
-                cfg->pgsize_bitmap &= (SZ_64K | SZ_512M);
+                max_addr_bits = 52;
+                page_sizes = (SZ_64K | SZ_512M);
+                if (cfg->oas > 48)
+                        page_sizes |= 1ULL << 42; /* 4TB */
                 break;
         default:
-                cfg->pgsize_bitmap = 0;
+                page_sizes = 0;
         }
+
+        cfg->pgsize_bitmap &= page_sizes;
+        cfg->ias = min(cfg->ias, max_addr_bits);
+        cfg->oas = min(cfg->oas, max_addr_bits);
 }
 
 static struct arm_lpae_io_pgtable *
@@ -784,6 +809,9 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
         case 48:
                 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT);
                 break;
+        case 52:
+                reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_IPS_SHIFT);
+                break;
         default:
                 goto out_free_data;
         }
@@ -891,6 +919,9 @@ arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
         case 48:
                 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT);
                 break;
+        case 52:
+                reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_PS_SHIFT);
+                break;
         default:
                 goto out_free_data;
         }