drm/i915: Assert dpll running in intel_crtc_load_lut() on pre-PCH platforms

Adding more context from Ville's reply to Rodrigo's question why we
need this:

"The spec says that on some hardware you need to PLL running before you
can poke at the palette registers. I didn't actually try to anger the
hardware so I'm not really sure what would happen otherwise, but IIRC
Jesse said something about a hard system hang..."

And generally documenting such ordering constraints with asserts is
Just Good.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Spruce up the commit message a lot.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c593ed0ca1b9..0e1f82810f58 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6311,6 +6311,9 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
         if (!crtc->enabled || !intel_crtc->active)
                 return;
 
+        if (!HAS_PCH_SPLIT(dev_priv->dev))
+                assert_pll_enabled(dev_priv, pipe);
+
         /* use legacy palette for Ironlake */
         if (HAS_PCH_SPLIT(dev))
                 palreg = LGC_PALETTE(pipe);