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authorSean Wang <sean.wang@mediatek.com>2018-02-17 14:54:42 -0500
committerMatthias Brugger <matthias.bgg@gmail.com>2018-03-11 15:28:33 -0400
commit13f36c326cef1aaf373b83f46df95fa42b70f426 (patch)
tree070a8ce72e1237bd726b3ca70ad7d093b1dec995
parenta5a80f78657f7d7b9b73bc67d0a18d5997c91168 (diff)
arm64: dts: mt7622: turn uart0 clock to real ones
This patch also cleans up two oscillators that provide clocks for MT7623. Switch the uart clocks to the real ones while at it. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7622.dtsi15
1 files changed, 2 insertions, 13 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index b4e5d49f9193..10ad69c02da8 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -91,18 +91,6 @@
91 }; 91 };
92 }; 92 };
93 93
94 uart_clk: dummy25m {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <25000000>;
98 };
99
100 bus_clk: dummy280m {
101 compatible = "fixed-clock";
102 #clock-cells = <0>;
103 clock-frequency = <280000000>;
104 };
105
106 pwrap_clk: dummy40m { 94 pwrap_clk: dummy40m {
107 compatible = "fixed-clock"; 95 compatible = "fixed-clock";
108 clock-frequency = <40000000>; 96 clock-frequency = <40000000>;
@@ -234,7 +222,8 @@
234 "mediatek,mt6577-uart"; 222 "mediatek,mt6577-uart";
235 reg = <0 0x11002000 0 0x400>; 223 reg = <0 0x11002000 0 0x400>;
236 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 224 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
237 clocks = <&uart_clk>, <&bus_clk>; 225 clocks = <&topckgen CLK_TOP_UART_SEL>,
226 <&pericfg CLK_PERI_UART1_PD>;
238 clock-names = "baud", "bus"; 227 clock-names = "baud", "bus";
239 status = "disabled"; 228 status = "disabled";
240 }; 229 };