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authorBen Skeggs <bskeggs@redhat.com>2015-08-20 00:54:22 -0400
committerBen Skeggs <bskeggs@redhat.com>2015-08-27 22:40:46 -0400
commit13de7f462902d1a452d501cdb2d06ef02cabbfff (patch)
tree47b8d40610627f41c98cd9ca2d7d1543faadba53
parent70aa8670e5229766f12c4b818a68aa61913df0b6 (diff)
drm/nouveau/fifo: convert to new-style nvkm_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h83
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c136
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c9
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c7
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c14
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/falcon.c3
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c128
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c71
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c162
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c198
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h24
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c30
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c30
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c32
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c30
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c92
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h10
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c45
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c57
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c59
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c103
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h19
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c4
56 files changed, 640 insertions, 801 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
index d9e494ba5033..84cc3e9cfed7 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
@@ -1,7 +1,5 @@
1#ifndef __NVKM_FIFO_H__ 1#ifndef __NVKM_FIFO_H__
2#define __NVKM_FIFO_H__ 2#define __NVKM_FIFO_H__
3#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object)
4#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine)
5#include <core/engine.h> 3#include <core/engine.h>
6#include <core/event.h> 4#include <core/event.h>
7 5
@@ -33,46 +31,21 @@ struct nvkm_fifo_chan {
33 31
34extern const struct nvkm_object_func nvkm_fifo_chan_func; 32extern const struct nvkm_object_func nvkm_fifo_chan_func;
35 33
36#include <core/gpuobj.h>
37struct nvkm_fifo_base {
38 struct nvkm_gpuobj gpuobj;
39};
40
41#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d) \
42 nvkm_gpuobj_create((p), (e), (c), NV_ENGCTX_CLASS, (g), (s), (a), (f), (d))
43#define nvkm_fifo_context_destroy(p) \
44 nvkm_gpuobj_destroy(&(p)->gpuobj)
45#define nvkm_fifo_context_init(p) \
46 nvkm_gpuobj_init(&(p)->gpuobj)
47#define nvkm_fifo_context_fini(p,s) \
48 nvkm_gpuobj_fini(&(p)->gpuobj, (s))
49
50#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor
51#define _nvkm_fifo_context_init _nvkm_gpuobj_init
52#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini
53#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32
54#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32
55
56struct nvkm_fifo { 34struct nvkm_fifo {
57 struct nvkm_engine engine;
58 const struct nvkm_fifo_func *func; 35 const struct nvkm_fifo_func *func;
59 36 struct nvkm_engine engine;
60 struct nvkm_event cevent; /* channel creation event */
61 struct nvkm_event uevent; /* async user trigger */
62 37
63 DECLARE_BITMAP(mask, NVKM_FIFO_CHID_NR); 38 DECLARE_BITMAP(mask, NVKM_FIFO_CHID_NR);
64 int nr; 39 int nr;
65 struct list_head chan; 40 struct list_head chan;
66 spinlock_t lock; 41 spinlock_t lock;
67 42
68 void (*pause)(struct nvkm_fifo *, unsigned long *); 43 struct nvkm_event uevent; /* async user trigger */
69 void (*start)(struct nvkm_fifo *, unsigned long *); 44 struct nvkm_event cevent; /* channel creation event */
70}; 45};
71 46
72struct nvkm_fifo_func { 47void nvkm_fifo_pause(struct nvkm_fifo *, unsigned long *);
73 void *(*dtor)(struct nvkm_fifo *); 48void nvkm_fifo_start(struct nvkm_fifo *, unsigned long *);
74 const struct nvkm_fifo_chan_oclass *chan[];
75};
76 49
77void nvkm_fifo_chan_put(struct nvkm_fifo *, unsigned long flags, 50void nvkm_fifo_chan_put(struct nvkm_fifo *, unsigned long flags,
78 struct nvkm_fifo_chan **); 51 struct nvkm_fifo_chan **);
@@ -81,38 +54,16 @@ nvkm_fifo_chan_inst(struct nvkm_fifo *, u64 inst, unsigned long *flags);
81struct nvkm_fifo_chan * 54struct nvkm_fifo_chan *
82nvkm_fifo_chan_chid(struct nvkm_fifo *, int chid, unsigned long *flags); 55nvkm_fifo_chan_chid(struct nvkm_fifo *, int chid, unsigned long *flags);
83 56
84#define nvkm_fifo_create(o,e,c,fc,lc,d) \ 57int nv04_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
85 nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d) 58int nv10_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
86#define nvkm_fifo_init(p) \ 59int nv17_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
87 nvkm_engine_init_old(&(p)->engine) 60int nv40_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
88#define nvkm_fifo_fini(p,s) \ 61int nv50_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
89 nvkm_engine_fini_old(&(p)->engine, (s)) 62int g84_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
90 63int gf100_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
91int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *, 64int gk104_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
92 struct nvkm_oclass *, int min, int max, 65int gk208_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
93 int size, void **); 66int gk20a_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
94void nvkm_fifo_destroy(struct nvkm_fifo *); 67int gm204_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
95 68int gm20b_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
96#define _nvkm_fifo_init _nvkm_engine_init
97#define _nvkm_fifo_fini _nvkm_engine_fini
98
99extern struct nvkm_oclass *nv04_fifo_oclass;
100extern struct nvkm_oclass *nv10_fifo_oclass;
101extern struct nvkm_oclass *nv17_fifo_oclass;
102extern struct nvkm_oclass *nv40_fifo_oclass;
103extern struct nvkm_oclass *nv50_fifo_oclass;
104extern struct nvkm_oclass *g84_fifo_oclass;
105extern struct nvkm_oclass *gf100_fifo_oclass;
106extern struct nvkm_oclass *gk104_fifo_oclass;
107extern struct nvkm_oclass *gk20a_fifo_oclass;
108extern struct nvkm_oclass *gk208_fifo_oclass;
109extern struct nvkm_oclass *gm204_fifo_oclass;
110extern struct nvkm_oclass *gm20b_fifo_oclass;
111
112int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,
113 struct nvkm_notify *);
114void nvkm_fifo_uevent(struct nvkm_fifo *);
115
116void nv04_fifo_intr(struct nvkm_subdev *);
117int nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *);
118#endif 69#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
index e056f7afc35c..b8fc539e0a99 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
@@ -231,7 +231,7 @@ nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj)
231 nvkm_object_destroy(&gpuobj->object); 231 nvkm_object_destroy(&gpuobj->object);
232} 232}
233 233
234#include <engine/fifo.h> 234#include <engine/fifo/chan.h>
235 235
236int 236int
237nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, 237nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
index 764b46751eb9..03763268248f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
@@ -26,6 +26,7 @@
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/enum.h> 28#include <core/enum.h>
29#include <core/gpuobj.h>
29#include <engine/fifo.h> 30#include <engine/fifo.h>
30 31
31#include <nvif/class.h> 32#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index ea3e8902f458..62395ab742c5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -88,7 +88,7 @@ nv4_chipset = {
88 .timer = nv04_timer_new, 88 .timer = nv04_timer_new,
89 .disp = nv04_disp_new, 89 .disp = nv04_disp_new,
90 .dma = nv04_dma_new, 90 .dma = nv04_dma_new,
91// .fifo = nv04_fifo_new, 91 .fifo = nv04_fifo_new,
92// .gr = nv04_gr_new, 92// .gr = nv04_gr_new,
93// .sw = nv04_sw_new, 93// .sw = nv04_sw_new,
94}; 94};
@@ -108,7 +108,7 @@ nv5_chipset = {
108 .timer = nv04_timer_new, 108 .timer = nv04_timer_new,
109 .disp = nv04_disp_new, 109 .disp = nv04_disp_new,
110 .dma = nv04_dma_new, 110 .dma = nv04_dma_new,
111// .fifo = nv04_fifo_new, 111 .fifo = nv04_fifo_new,
112// .gr = nv04_gr_new, 112// .gr = nv04_gr_new,
113// .sw = nv04_sw_new, 113// .sw = nv04_sw_new,
114}; 114};
@@ -148,7 +148,7 @@ nv11_chipset = {
148 .timer = nv04_timer_new, 148 .timer = nv04_timer_new,
149 .disp = nv04_disp_new, 149 .disp = nv04_disp_new,
150 .dma = nv04_dma_new, 150 .dma = nv04_dma_new,
151// .fifo = nv10_fifo_new, 151 .fifo = nv10_fifo_new,
152// .gr = nv10_gr_new, 152// .gr = nv10_gr_new,
153// .sw = nv10_sw_new, 153// .sw = nv10_sw_new,
154}; 154};
@@ -169,7 +169,7 @@ nv15_chipset = {
169 .timer = nv04_timer_new, 169 .timer = nv04_timer_new,
170 .disp = nv04_disp_new, 170 .disp = nv04_disp_new,
171 .dma = nv04_dma_new, 171 .dma = nv04_dma_new,
172// .fifo = nv10_fifo_new, 172 .fifo = nv10_fifo_new,
173// .gr = nv10_gr_new, 173// .gr = nv10_gr_new,
174// .sw = nv10_sw_new, 174// .sw = nv10_sw_new,
175}; 175};
@@ -190,7 +190,7 @@ nv17_chipset = {
190 .timer = nv04_timer_new, 190 .timer = nv04_timer_new,
191 .disp = nv04_disp_new, 191 .disp = nv04_disp_new,
192 .dma = nv04_dma_new, 192 .dma = nv04_dma_new,
193// .fifo = nv17_fifo_new, 193 .fifo = nv17_fifo_new,
194// .gr = nv10_gr_new, 194// .gr = nv10_gr_new,
195// .sw = nv10_sw_new, 195// .sw = nv10_sw_new,
196}; 196};
@@ -211,7 +211,7 @@ nv18_chipset = {
211 .timer = nv04_timer_new, 211 .timer = nv04_timer_new,
212 .disp = nv04_disp_new, 212 .disp = nv04_disp_new,
213 .dma = nv04_dma_new, 213 .dma = nv04_dma_new,
214// .fifo = nv17_fifo_new, 214 .fifo = nv17_fifo_new,
215// .gr = nv10_gr_new, 215// .gr = nv10_gr_new,
216// .sw = nv10_sw_new, 216// .sw = nv10_sw_new,
217}; 217};
@@ -232,7 +232,7 @@ nv1a_chipset = {
232 .timer = nv04_timer_new, 232 .timer = nv04_timer_new,
233 .disp = nv04_disp_new, 233 .disp = nv04_disp_new,
234 .dma = nv04_dma_new, 234 .dma = nv04_dma_new,
235// .fifo = nv10_fifo_new, 235 .fifo = nv10_fifo_new,
236// .gr = nv10_gr_new, 236// .gr = nv10_gr_new,
237// .sw = nv10_sw_new, 237// .sw = nv10_sw_new,
238}; 238};
@@ -253,7 +253,7 @@ nv1f_chipset = {
253 .timer = nv04_timer_new, 253 .timer = nv04_timer_new,
254 .disp = nv04_disp_new, 254 .disp = nv04_disp_new,
255 .dma = nv04_dma_new, 255 .dma = nv04_dma_new,
256// .fifo = nv17_fifo_new, 256 .fifo = nv17_fifo_new,
257// .gr = nv10_gr_new, 257// .gr = nv10_gr_new,
258// .sw = nv10_sw_new, 258// .sw = nv10_sw_new,
259}; 259};
@@ -274,7 +274,7 @@ nv20_chipset = {
274 .timer = nv04_timer_new, 274 .timer = nv04_timer_new,
275 .disp = nv04_disp_new, 275 .disp = nv04_disp_new,
276 .dma = nv04_dma_new, 276 .dma = nv04_dma_new,
277// .fifo = nv17_fifo_new, 277 .fifo = nv17_fifo_new,
278// .gr = nv20_gr_new, 278// .gr = nv20_gr_new,
279// .sw = nv10_sw_new, 279// .sw = nv10_sw_new,
280}; 280};
@@ -295,7 +295,7 @@ nv25_chipset = {
295 .timer = nv04_timer_new, 295 .timer = nv04_timer_new,
296 .disp = nv04_disp_new, 296 .disp = nv04_disp_new,
297 .dma = nv04_dma_new, 297 .dma = nv04_dma_new,
298// .fifo = nv17_fifo_new, 298 .fifo = nv17_fifo_new,
299// .gr = nv25_gr_new, 299// .gr = nv25_gr_new,
300// .sw = nv10_sw_new, 300// .sw = nv10_sw_new,
301}; 301};
@@ -316,7 +316,7 @@ nv28_chipset = {
316 .timer = nv04_timer_new, 316 .timer = nv04_timer_new,
317 .disp = nv04_disp_new, 317 .disp = nv04_disp_new,
318 .dma = nv04_dma_new, 318 .dma = nv04_dma_new,
319// .fifo = nv17_fifo_new, 319 .fifo = nv17_fifo_new,
320// .gr = nv25_gr_new, 320// .gr = nv25_gr_new,
321// .sw = nv10_sw_new, 321// .sw = nv10_sw_new,
322}; 322};
@@ -337,7 +337,7 @@ nv2a_chipset = {
337 .timer = nv04_timer_new, 337 .timer = nv04_timer_new,
338 .disp = nv04_disp_new, 338 .disp = nv04_disp_new,
339 .dma = nv04_dma_new, 339 .dma = nv04_dma_new,
340// .fifo = nv17_fifo_new, 340 .fifo = nv17_fifo_new,
341// .gr = nv2a_gr_new, 341// .gr = nv2a_gr_new,
342// .sw = nv10_sw_new, 342// .sw = nv10_sw_new,
343}; 343};
@@ -358,7 +358,7 @@ nv30_chipset = {
358 .timer = nv04_timer_new, 358 .timer = nv04_timer_new,
359 .disp = nv04_disp_new, 359 .disp = nv04_disp_new,
360 .dma = nv04_dma_new, 360 .dma = nv04_dma_new,
361// .fifo = nv17_fifo_new, 361 .fifo = nv17_fifo_new,
362// .gr = nv30_gr_new, 362// .gr = nv30_gr_new,
363// .sw = nv10_sw_new, 363// .sw = nv10_sw_new,
364}; 364};
@@ -379,7 +379,7 @@ nv31_chipset = {
379 .timer = nv04_timer_new, 379 .timer = nv04_timer_new,
380 .disp = nv04_disp_new, 380 .disp = nv04_disp_new,
381 .dma = nv04_dma_new, 381 .dma = nv04_dma_new,
382// .fifo = nv17_fifo_new, 382 .fifo = nv17_fifo_new,
383// .gr = nv30_gr_new, 383// .gr = nv30_gr_new,
384// .mpeg = nv31_mpeg_new, 384// .mpeg = nv31_mpeg_new,
385// .sw = nv10_sw_new, 385// .sw = nv10_sw_new,
@@ -401,7 +401,7 @@ nv34_chipset = {
401 .timer = nv04_timer_new, 401 .timer = nv04_timer_new,
402 .disp = nv04_disp_new, 402 .disp = nv04_disp_new,
403 .dma = nv04_dma_new, 403 .dma = nv04_dma_new,
404// .fifo = nv17_fifo_new, 404 .fifo = nv17_fifo_new,
405// .gr = nv34_gr_new, 405// .gr = nv34_gr_new,
406// .mpeg = nv31_mpeg_new, 406// .mpeg = nv31_mpeg_new,
407// .sw = nv10_sw_new, 407// .sw = nv10_sw_new,
@@ -423,7 +423,7 @@ nv35_chipset = {
423 .timer = nv04_timer_new, 423 .timer = nv04_timer_new,
424 .disp = nv04_disp_new, 424 .disp = nv04_disp_new,
425 .dma = nv04_dma_new, 425 .dma = nv04_dma_new,
426// .fifo = nv17_fifo_new, 426 .fifo = nv17_fifo_new,
427// .gr = nv35_gr_new, 427// .gr = nv35_gr_new,
428// .sw = nv10_sw_new, 428// .sw = nv10_sw_new,
429}; 429};
@@ -444,7 +444,7 @@ nv36_chipset = {
444 .timer = nv04_timer_new, 444 .timer = nv04_timer_new,
445 .disp = nv04_disp_new, 445 .disp = nv04_disp_new,
446 .dma = nv04_dma_new, 446 .dma = nv04_dma_new,
447// .fifo = nv17_fifo_new, 447 .fifo = nv17_fifo_new,
448// .gr = nv35_gr_new, 448// .gr = nv35_gr_new,
449// .mpeg = nv31_mpeg_new, 449// .mpeg = nv31_mpeg_new,
450// .sw = nv10_sw_new, 450// .sw = nv10_sw_new,
@@ -468,7 +468,7 @@ nv40_chipset = {
468 .volt = nv40_volt_new, 468 .volt = nv40_volt_new,
469 .disp = nv04_disp_new, 469 .disp = nv04_disp_new,
470 .dma = nv04_dma_new, 470 .dma = nv04_dma_new,
471// .fifo = nv40_fifo_new, 471 .fifo = nv40_fifo_new,
472// .gr = nv40_gr_new, 472// .gr = nv40_gr_new,
473// .mpeg = nv40_mpeg_new, 473// .mpeg = nv40_mpeg_new,
474// .pm = nv40_pm_new, 474// .pm = nv40_pm_new,
@@ -493,7 +493,7 @@ nv41_chipset = {
493 .volt = nv40_volt_new, 493 .volt = nv40_volt_new,
494 .disp = nv04_disp_new, 494 .disp = nv04_disp_new,
495 .dma = nv04_dma_new, 495 .dma = nv04_dma_new,
496// .fifo = nv40_fifo_new, 496 .fifo = nv40_fifo_new,
497// .gr = nv40_gr_new, 497// .gr = nv40_gr_new,
498// .mpeg = nv40_mpeg_new, 498// .mpeg = nv40_mpeg_new,
499// .pm = nv40_pm_new, 499// .pm = nv40_pm_new,
@@ -518,7 +518,7 @@ nv42_chipset = {
518 .volt = nv40_volt_new, 518 .volt = nv40_volt_new,
519 .disp = nv04_disp_new, 519 .disp = nv04_disp_new,
520 .dma = nv04_dma_new, 520 .dma = nv04_dma_new,
521// .fifo = nv40_fifo_new, 521 .fifo = nv40_fifo_new,
522// .gr = nv40_gr_new, 522// .gr = nv40_gr_new,
523// .mpeg = nv40_mpeg_new, 523// .mpeg = nv40_mpeg_new,
524// .pm = nv40_pm_new, 524// .pm = nv40_pm_new,
@@ -543,7 +543,7 @@ nv43_chipset = {
543 .volt = nv40_volt_new, 543 .volt = nv40_volt_new,
544 .disp = nv04_disp_new, 544 .disp = nv04_disp_new,
545 .dma = nv04_dma_new, 545 .dma = nv04_dma_new,
546// .fifo = nv40_fifo_new, 546 .fifo = nv40_fifo_new,
547// .gr = nv40_gr_new, 547// .gr = nv40_gr_new,
548// .mpeg = nv40_mpeg_new, 548// .mpeg = nv40_mpeg_new,
549// .pm = nv40_pm_new, 549// .pm = nv40_pm_new,
@@ -568,7 +568,7 @@ nv44_chipset = {
568 .volt = nv40_volt_new, 568 .volt = nv40_volt_new,
569 .disp = nv04_disp_new, 569 .disp = nv04_disp_new,
570 .dma = nv04_dma_new, 570 .dma = nv04_dma_new,
571// .fifo = nv40_fifo_new, 571 .fifo = nv40_fifo_new,
572// .gr = nv40_gr_new, 572// .gr = nv40_gr_new,
573// .mpeg = nv44_mpeg_new, 573// .mpeg = nv44_mpeg_new,
574// .pm = nv40_pm_new, 574// .pm = nv40_pm_new,
@@ -593,7 +593,7 @@ nv45_chipset = {
593 .volt = nv40_volt_new, 593 .volt = nv40_volt_new,
594 .disp = nv04_disp_new, 594 .disp = nv04_disp_new,
595 .dma = nv04_dma_new, 595 .dma = nv04_dma_new,
596// .fifo = nv40_fifo_new, 596 .fifo = nv40_fifo_new,
597// .gr = nv40_gr_new, 597// .gr = nv40_gr_new,
598// .mpeg = nv44_mpeg_new, 598// .mpeg = nv44_mpeg_new,
599// .pm = nv40_pm_new, 599// .pm = nv40_pm_new,
@@ -618,7 +618,7 @@ nv46_chipset = {
618 .volt = nv40_volt_new, 618 .volt = nv40_volt_new,
619 .disp = nv04_disp_new, 619 .disp = nv04_disp_new,
620 .dma = nv04_dma_new, 620 .dma = nv04_dma_new,
621// .fifo = nv40_fifo_new, 621 .fifo = nv40_fifo_new,
622// .gr = nv40_gr_new, 622// .gr = nv40_gr_new,
623// .mpeg = nv44_mpeg_new, 623// .mpeg = nv44_mpeg_new,
624// .pm = nv40_pm_new, 624// .pm = nv40_pm_new,
@@ -643,7 +643,7 @@ nv47_chipset = {
643 .volt = nv40_volt_new, 643 .volt = nv40_volt_new,
644 .disp = nv04_disp_new, 644 .disp = nv04_disp_new,
645 .dma = nv04_dma_new, 645 .dma = nv04_dma_new,
646// .fifo = nv40_fifo_new, 646 .fifo = nv40_fifo_new,
647// .gr = nv40_gr_new, 647// .gr = nv40_gr_new,
648// .mpeg = nv44_mpeg_new, 648// .mpeg = nv44_mpeg_new,
649// .pm = nv40_pm_new, 649// .pm = nv40_pm_new,
@@ -668,7 +668,7 @@ nv49_chipset = {
668 .volt = nv40_volt_new, 668 .volt = nv40_volt_new,
669 .disp = nv04_disp_new, 669 .disp = nv04_disp_new,
670 .dma = nv04_dma_new, 670 .dma = nv04_dma_new,
671// .fifo = nv40_fifo_new, 671 .fifo = nv40_fifo_new,
672// .gr = nv40_gr_new, 672// .gr = nv40_gr_new,
673// .mpeg = nv44_mpeg_new, 673// .mpeg = nv44_mpeg_new,
674// .pm = nv40_pm_new, 674// .pm = nv40_pm_new,
@@ -693,7 +693,7 @@ nv4a_chipset = {
693 .volt = nv40_volt_new, 693 .volt = nv40_volt_new,
694 .disp = nv04_disp_new, 694 .disp = nv04_disp_new,
695 .dma = nv04_dma_new, 695 .dma = nv04_dma_new,
696// .fifo = nv40_fifo_new, 696 .fifo = nv40_fifo_new,
697// .gr = nv40_gr_new, 697// .gr = nv40_gr_new,
698// .mpeg = nv44_mpeg_new, 698// .mpeg = nv44_mpeg_new,
699// .pm = nv40_pm_new, 699// .pm = nv40_pm_new,
@@ -718,7 +718,7 @@ nv4b_chipset = {
718 .volt = nv40_volt_new, 718 .volt = nv40_volt_new,
719 .disp = nv04_disp_new, 719 .disp = nv04_disp_new,
720 .dma = nv04_dma_new, 720 .dma = nv04_dma_new,
721// .fifo = nv40_fifo_new, 721 .fifo = nv40_fifo_new,
722// .gr = nv40_gr_new, 722// .gr = nv40_gr_new,
723// .mpeg = nv44_mpeg_new, 723// .mpeg = nv44_mpeg_new,
724// .pm = nv40_pm_new, 724// .pm = nv40_pm_new,
@@ -743,7 +743,7 @@ nv4c_chipset = {
743 .volt = nv40_volt_new, 743 .volt = nv40_volt_new,
744 .disp = nv04_disp_new, 744 .disp = nv04_disp_new,
745 .dma = nv04_dma_new, 745 .dma = nv04_dma_new,
746// .fifo = nv40_fifo_new, 746 .fifo = nv40_fifo_new,
747// .gr = nv40_gr_new, 747// .gr = nv40_gr_new,
748// .mpeg = nv44_mpeg_new, 748// .mpeg = nv44_mpeg_new,
749// .pm = nv40_pm_new, 749// .pm = nv40_pm_new,
@@ -768,7 +768,7 @@ nv4e_chipset = {
768 .volt = nv40_volt_new, 768 .volt = nv40_volt_new,
769 .disp = nv04_disp_new, 769 .disp = nv04_disp_new,
770 .dma = nv04_dma_new, 770 .dma = nv04_dma_new,
771// .fifo = nv40_fifo_new, 771 .fifo = nv40_fifo_new,
772// .gr = nv40_gr_new, 772// .gr = nv40_gr_new,
773// .mpeg = nv44_mpeg_new, 773// .mpeg = nv44_mpeg_new,
774// .pm = nv40_pm_new, 774// .pm = nv40_pm_new,
@@ -796,7 +796,7 @@ nv50_chipset = {
796 .volt = nv40_volt_new, 796 .volt = nv40_volt_new,
797 .disp = nv50_disp_new, 797 .disp = nv50_disp_new,
798 .dma = nv50_dma_new, 798 .dma = nv50_dma_new,
799// .fifo = nv50_fifo_new, 799 .fifo = nv50_fifo_new,
800// .gr = nv50_gr_new, 800// .gr = nv50_gr_new,
801// .mpeg = nv50_mpeg_new, 801// .mpeg = nv50_mpeg_new,
802// .pm = nv50_pm_new, 802// .pm = nv50_pm_new,
@@ -821,7 +821,7 @@ nv63_chipset = {
821 .volt = nv40_volt_new, 821 .volt = nv40_volt_new,
822 .disp = nv04_disp_new, 822 .disp = nv04_disp_new,
823 .dma = nv04_dma_new, 823 .dma = nv04_dma_new,
824// .fifo = nv40_fifo_new, 824 .fifo = nv40_fifo_new,
825// .gr = nv40_gr_new, 825// .gr = nv40_gr_new,
826// .mpeg = nv44_mpeg_new, 826// .mpeg = nv44_mpeg_new,
827// .pm = nv40_pm_new, 827// .pm = nv40_pm_new,
@@ -846,7 +846,7 @@ nv67_chipset = {
846 .volt = nv40_volt_new, 846 .volt = nv40_volt_new,
847 .disp = nv04_disp_new, 847 .disp = nv04_disp_new,
848 .dma = nv04_dma_new, 848 .dma = nv04_dma_new,
849// .fifo = nv40_fifo_new, 849 .fifo = nv40_fifo_new,
850// .gr = nv40_gr_new, 850// .gr = nv40_gr_new,
851// .mpeg = nv44_mpeg_new, 851// .mpeg = nv44_mpeg_new,
852// .pm = nv40_pm_new, 852// .pm = nv40_pm_new,
@@ -871,7 +871,7 @@ nv68_chipset = {
871 .volt = nv40_volt_new, 871 .volt = nv40_volt_new,
872 .disp = nv04_disp_new, 872 .disp = nv04_disp_new,
873 .dma = nv04_dma_new, 873 .dma = nv04_dma_new,
874// .fifo = nv40_fifo_new, 874 .fifo = nv40_fifo_new,
875// .gr = nv40_gr_new, 875// .gr = nv40_gr_new,
876// .mpeg = nv44_mpeg_new, 876// .mpeg = nv44_mpeg_new,
877// .pm = nv40_pm_new, 877// .pm = nv40_pm_new,
@@ -901,7 +901,7 @@ nv84_chipset = {
901 .cipher = g84_cipher_new, 901 .cipher = g84_cipher_new,
902 .disp = g84_disp_new, 902 .disp = g84_disp_new,
903 .dma = nv50_dma_new, 903 .dma = nv50_dma_new,
904// .fifo = g84_fifo_new, 904 .fifo = g84_fifo_new,
905// .gr = nv50_gr_new, 905// .gr = nv50_gr_new,
906// .mpeg = g84_mpeg_new, 906// .mpeg = g84_mpeg_new,
907// .pm = g84_pm_new, 907// .pm = g84_pm_new,
@@ -932,7 +932,7 @@ nv86_chipset = {
932 .cipher = g84_cipher_new, 932 .cipher = g84_cipher_new,
933 .disp = g84_disp_new, 933 .disp = g84_disp_new,
934 .dma = nv50_dma_new, 934 .dma = nv50_dma_new,
935// .fifo = g84_fifo_new, 935 .fifo = g84_fifo_new,
936// .gr = nv50_gr_new, 936// .gr = nv50_gr_new,
937// .mpeg = g84_mpeg_new, 937// .mpeg = g84_mpeg_new,
938// .pm = g84_pm_new, 938// .pm = g84_pm_new,
@@ -963,7 +963,7 @@ nv92_chipset = {
963 .cipher = g84_cipher_new, 963 .cipher = g84_cipher_new,
964 .disp = g84_disp_new, 964 .disp = g84_disp_new,
965 .dma = nv50_dma_new, 965 .dma = nv50_dma_new,
966// .fifo = g84_fifo_new, 966 .fifo = g84_fifo_new,
967// .gr = nv50_gr_new, 967// .gr = nv50_gr_new,
968// .mpeg = g84_mpeg_new, 968// .mpeg = g84_mpeg_new,
969// .pm = g84_pm_new, 969// .pm = g84_pm_new,
@@ -994,7 +994,7 @@ nv94_chipset = {
994 .cipher = g84_cipher_new, 994 .cipher = g84_cipher_new,
995 .disp = g94_disp_new, 995 .disp = g94_disp_new,
996 .dma = nv50_dma_new, 996 .dma = nv50_dma_new,
997// .fifo = g84_fifo_new, 997 .fifo = g84_fifo_new,
998// .gr = nv50_gr_new, 998// .gr = nv50_gr_new,
999// .mpeg = g84_mpeg_new, 999// .mpeg = g84_mpeg_new,
1000// .pm = g84_pm_new, 1000// .pm = g84_pm_new,
@@ -1022,7 +1022,7 @@ nv96_chipset = {
1022 .bar = g84_bar_new, 1022 .bar = g84_bar_new,
1023 .volt = nv40_volt_new, 1023 .volt = nv40_volt_new,
1024 .dma = nv50_dma_new, 1024 .dma = nv50_dma_new,
1025// .fifo = g84_fifo_new, 1025 .fifo = g84_fifo_new,
1026// .sw = nv50_sw_new, 1026// .sw = nv50_sw_new,
1027// .gr = nv50_gr_new, 1027// .gr = nv50_gr_new,
1028// .mpeg = g84_mpeg_new, 1028// .mpeg = g84_mpeg_new,
@@ -1053,7 +1053,7 @@ nv98_chipset = {
1053 .bar = g84_bar_new, 1053 .bar = g84_bar_new,
1054 .volt = nv40_volt_new, 1054 .volt = nv40_volt_new,
1055 .dma = nv50_dma_new, 1055 .dma = nv50_dma_new,
1056// .fifo = g84_fifo_new, 1056 .fifo = g84_fifo_new,
1057// .sw = nv50_sw_new, 1057// .sw = nv50_sw_new,
1058// .gr = nv50_gr_new, 1058// .gr = nv50_gr_new,
1059 .mspdec = g98_mspdec_new, 1059 .mspdec = g98_mspdec_new,
@@ -1087,7 +1087,7 @@ nva0_chipset = {
1087 .cipher = g84_cipher_new, 1087 .cipher = g84_cipher_new,
1088 .disp = gt200_disp_new, 1088 .disp = gt200_disp_new,
1089 .dma = nv50_dma_new, 1089 .dma = nv50_dma_new,
1090// .fifo = g84_fifo_new, 1090 .fifo = g84_fifo_new,
1091// .gr = nv50_gr_new, 1091// .gr = nv50_gr_new,
1092// .mpeg = g84_mpeg_new, 1092// .mpeg = g84_mpeg_new,
1093// .pm = gt200_pm_new, 1093// .pm = gt200_pm_new,
@@ -1118,7 +1118,7 @@ nva3_chipset = {
1118 .ce[0] = gt215_ce_new, 1118 .ce[0] = gt215_ce_new,
1119 .disp = gt215_disp_new, 1119 .disp = gt215_disp_new,
1120 .dma = nv50_dma_new, 1120 .dma = nv50_dma_new,
1121// .fifo = g84_fifo_new, 1121 .fifo = g84_fifo_new,
1122// .gr = nv50_gr_new, 1122// .gr = nv50_gr_new,
1123// .mpeg = g84_mpeg_new, 1123// .mpeg = g84_mpeg_new,
1124 .mspdec = gt215_mspdec_new, 1124 .mspdec = gt215_mspdec_new,
@@ -1151,7 +1151,7 @@ nva5_chipset = {
1151 .ce[0] = gt215_ce_new, 1151 .ce[0] = gt215_ce_new,
1152 .disp = gt215_disp_new, 1152 .disp = gt215_disp_new,
1153 .dma = nv50_dma_new, 1153 .dma = nv50_dma_new,
1154// .fifo = g84_fifo_new, 1154 .fifo = g84_fifo_new,
1155// .gr = nv50_gr_new, 1155// .gr = nv50_gr_new,
1156 .mspdec = gt215_mspdec_new, 1156 .mspdec = gt215_mspdec_new,
1157 .msppp = gt215_msppp_new, 1157 .msppp = gt215_msppp_new,
@@ -1183,7 +1183,7 @@ nva8_chipset = {
1183 .ce[0] = gt215_ce_new, 1183 .ce[0] = gt215_ce_new,
1184 .disp = gt215_disp_new, 1184 .disp = gt215_disp_new,
1185 .dma = nv50_dma_new, 1185 .dma = nv50_dma_new,
1186// .fifo = g84_fifo_new, 1186 .fifo = g84_fifo_new,
1187// .gr = nv50_gr_new, 1187// .gr = nv50_gr_new,
1188 .mspdec = gt215_mspdec_new, 1188 .mspdec = gt215_mspdec_new,
1189 .msppp = gt215_msppp_new, 1189 .msppp = gt215_msppp_new,
@@ -1213,7 +1213,7 @@ nvaa_chipset = {
1213 .volt = nv40_volt_new, 1213 .volt = nv40_volt_new,
1214 .disp = g94_disp_new, 1214 .disp = g94_disp_new,
1215 .dma = nv50_dma_new, 1215 .dma = nv50_dma_new,
1216// .fifo = g84_fifo_new, 1216 .fifo = g84_fifo_new,
1217// .gr = nv50_gr_new, 1217// .gr = nv50_gr_new,
1218 .mspdec = g98_mspdec_new, 1218 .mspdec = g98_mspdec_new,
1219 .msppp = g98_msppp_new, 1219 .msppp = g98_msppp_new,
@@ -1244,7 +1244,7 @@ nvac_chipset = {
1244 .volt = nv40_volt_new, 1244 .volt = nv40_volt_new,
1245 .disp = g94_disp_new, 1245 .disp = g94_disp_new,
1246 .dma = nv50_dma_new, 1246 .dma = nv50_dma_new,
1247// .fifo = g84_fifo_new, 1247 .fifo = g84_fifo_new,
1248// .gr = nv50_gr_new, 1248// .gr = nv50_gr_new,
1249 .mspdec = g98_mspdec_new, 1249 .mspdec = g98_mspdec_new,
1250 .msppp = g98_msppp_new, 1250 .msppp = g98_msppp_new,
@@ -1277,7 +1277,7 @@ nvaf_chipset = {
1277 .ce[0] = gt215_ce_new, 1277 .ce[0] = gt215_ce_new,
1278 .disp = gt215_disp_new, 1278 .disp = gt215_disp_new,
1279 .dma = nv50_dma_new, 1279 .dma = nv50_dma_new,
1280// .fifo = g84_fifo_new, 1280 .fifo = g84_fifo_new,
1281// .gr = nv50_gr_new, 1281// .gr = nv50_gr_new,
1282 .mspdec = gt215_mspdec_new, 1282 .mspdec = gt215_mspdec_new,
1283 .msppp = gt215_msppp_new, 1283 .msppp = gt215_msppp_new,
@@ -1312,7 +1312,7 @@ nvc0_chipset = {
1312 .ce[1] = gf100_ce_new, 1312 .ce[1] = gf100_ce_new,
1313 .disp = gt215_disp_new, 1313 .disp = gt215_disp_new,
1314 .dma = gf100_dma_new, 1314 .dma = gf100_dma_new,
1315// .fifo = gf100_fifo_new, 1315 .fifo = gf100_fifo_new,
1316// .gr = gf100_gr_new, 1316// .gr = gf100_gr_new,
1317 .mspdec = gf100_mspdec_new, 1317 .mspdec = gf100_mspdec_new,
1318 .msppp = gf100_msppp_new, 1318 .msppp = gf100_msppp_new,
@@ -1346,7 +1346,7 @@ nvc1_chipset = {
1346 .ce[0] = gf100_ce_new, 1346 .ce[0] = gf100_ce_new,
1347 .disp = gt215_disp_new, 1347 .disp = gt215_disp_new,
1348 .dma = gf100_dma_new, 1348 .dma = gf100_dma_new,
1349// .fifo = gf100_fifo_new, 1349 .fifo = gf100_fifo_new,
1350// .gr = gf108_gr_new, 1350// .gr = gf108_gr_new,
1351 .mspdec = gf100_mspdec_new, 1351 .mspdec = gf100_mspdec_new,
1352 .msppp = gf100_msppp_new, 1352 .msppp = gf100_msppp_new,
@@ -1380,7 +1380,7 @@ nvc3_chipset = {
1380 .ce[0] = gf100_ce_new, 1380 .ce[0] = gf100_ce_new,
1381 .disp = gt215_disp_new, 1381 .disp = gt215_disp_new,
1382 .dma = gf100_dma_new, 1382 .dma = gf100_dma_new,
1383// .fifo = gf100_fifo_new, 1383 .fifo = gf100_fifo_new,
1384// .gr = gf104_gr_new, 1384// .gr = gf104_gr_new,
1385 .mspdec = gf100_mspdec_new, 1385 .mspdec = gf100_mspdec_new,
1386 .msppp = gf100_msppp_new, 1386 .msppp = gf100_msppp_new,
@@ -1415,7 +1415,7 @@ nvc4_chipset = {
1415 .ce[1] = gf100_ce_new, 1415 .ce[1] = gf100_ce_new,
1416 .disp = gt215_disp_new, 1416 .disp = gt215_disp_new,
1417 .dma = gf100_dma_new, 1417 .dma = gf100_dma_new,
1418// .fifo = gf100_fifo_new, 1418 .fifo = gf100_fifo_new,
1419// .gr = gf104_gr_new, 1419// .gr = gf104_gr_new,
1420 .mspdec = gf100_mspdec_new, 1420 .mspdec = gf100_mspdec_new,
1421 .msppp = gf100_msppp_new, 1421 .msppp = gf100_msppp_new,
@@ -1450,7 +1450,7 @@ nvc8_chipset = {
1450 .ce[1] = gf100_ce_new, 1450 .ce[1] = gf100_ce_new,
1451 .disp = gt215_disp_new, 1451 .disp = gt215_disp_new,
1452 .dma = gf100_dma_new, 1452 .dma = gf100_dma_new,
1453// .fifo = gf100_fifo_new, 1453 .fifo = gf100_fifo_new,
1454// .gr = gf110_gr_new, 1454// .gr = gf110_gr_new,
1455 .mspdec = gf100_mspdec_new, 1455 .mspdec = gf100_mspdec_new,
1456 .msppp = gf100_msppp_new, 1456 .msppp = gf100_msppp_new,
@@ -1485,7 +1485,7 @@ nvce_chipset = {
1485 .ce[1] = gf100_ce_new, 1485 .ce[1] = gf100_ce_new,
1486 .disp = gt215_disp_new, 1486 .disp = gt215_disp_new,
1487 .dma = gf100_dma_new, 1487 .dma = gf100_dma_new,
1488// .fifo = gf100_fifo_new, 1488 .fifo = gf100_fifo_new,
1489// .gr = gf104_gr_new, 1489// .gr = gf104_gr_new,
1490 .mspdec = gf100_mspdec_new, 1490 .mspdec = gf100_mspdec_new,
1491 .msppp = gf100_msppp_new, 1491 .msppp = gf100_msppp_new,
@@ -1519,7 +1519,7 @@ nvcf_chipset = {
1519 .ce[0] = gf100_ce_new, 1519 .ce[0] = gf100_ce_new,
1520 .disp = gt215_disp_new, 1520 .disp = gt215_disp_new,
1521 .dma = gf100_dma_new, 1521 .dma = gf100_dma_new,
1522// .fifo = gf100_fifo_new, 1522 .fifo = gf100_fifo_new,
1523// .gr = gf104_gr_new, 1523// .gr = gf104_gr_new,
1524 .mspdec = gf100_mspdec_new, 1524 .mspdec = gf100_mspdec_new,
1525 .msppp = gf100_msppp_new, 1525 .msppp = gf100_msppp_new,
@@ -1551,7 +1551,7 @@ nvd7_chipset = {
1551 .ce[0] = gf100_ce_new, 1551 .ce[0] = gf100_ce_new,
1552 .disp = gf119_disp_new, 1552 .disp = gf119_disp_new,
1553 .dma = gf119_dma_new, 1553 .dma = gf119_dma_new,
1554// .fifo = gf100_fifo_new, 1554 .fifo = gf100_fifo_new,
1555// .gr = gf117_gr_new, 1555// .gr = gf117_gr_new,
1556 .mspdec = gf100_mspdec_new, 1556 .mspdec = gf100_mspdec_new,
1557 .msppp = gf100_msppp_new, 1557 .msppp = gf100_msppp_new,
@@ -1585,7 +1585,7 @@ nvd9_chipset = {
1585 .ce[0] = gf100_ce_new, 1585 .ce[0] = gf100_ce_new,
1586 .disp = gf119_disp_new, 1586 .disp = gf119_disp_new,
1587 .dma = gf119_dma_new, 1587 .dma = gf119_dma_new,
1588// .fifo = gf100_fifo_new, 1588 .fifo = gf100_fifo_new,
1589// .gr = gf119_gr_new, 1589// .gr = gf119_gr_new,
1590 .mspdec = gf100_mspdec_new, 1590 .mspdec = gf100_mspdec_new,
1591 .msppp = gf100_msppp_new, 1591 .msppp = gf100_msppp_new,
@@ -1621,7 +1621,7 @@ nve4_chipset = {
1621 .ce[2] = gk104_ce_new, 1621 .ce[2] = gk104_ce_new,
1622 .disp = gk104_disp_new, 1622 .disp = gk104_disp_new,
1623 .dma = gf119_dma_new, 1623 .dma = gf119_dma_new,
1624// .fifo = gk104_fifo_new, 1624 .fifo = gk104_fifo_new,
1625// .gr = gk104_gr_new, 1625// .gr = gk104_gr_new,
1626 .mspdec = gk104_mspdec_new, 1626 .mspdec = gk104_mspdec_new,
1627 .msppp = gf100_msppp_new, 1627 .msppp = gf100_msppp_new,
@@ -1657,7 +1657,7 @@ nve6_chipset = {
1657 .ce[2] = gk104_ce_new, 1657 .ce[2] = gk104_ce_new,
1658 .disp = gk104_disp_new, 1658 .disp = gk104_disp_new,
1659 .dma = gf119_dma_new, 1659 .dma = gf119_dma_new,
1660// .fifo = gk104_fifo_new, 1660 .fifo = gk104_fifo_new,
1661// .gr = gk104_gr_new, 1661// .gr = gk104_gr_new,
1662 .mspdec = gk104_mspdec_new, 1662 .mspdec = gk104_mspdec_new,
1663 .msppp = gf100_msppp_new, 1663 .msppp = gf100_msppp_new,
@@ -1693,7 +1693,7 @@ nve7_chipset = {
1693 .ce[2] = gk104_ce_new, 1693 .ce[2] = gk104_ce_new,
1694 .disp = gk104_disp_new, 1694 .disp = gk104_disp_new,
1695 .dma = gf119_dma_new, 1695 .dma = gf119_dma_new,
1696// .fifo = gk104_fifo_new, 1696 .fifo = gk104_fifo_new,
1697// .gr = gk104_gr_new, 1697// .gr = gk104_gr_new,
1698 .mspdec = gk104_mspdec_new, 1698 .mspdec = gk104_mspdec_new,
1699 .msppp = gf100_msppp_new, 1699 .msppp = gf100_msppp_new,
@@ -1720,7 +1720,7 @@ nvea_chipset = {
1720 .volt = gk20a_volt_new, 1720 .volt = gk20a_volt_new,
1721 .ce[2] = gk104_ce_new, 1721 .ce[2] = gk104_ce_new,
1722 .dma = gf119_dma_new, 1722 .dma = gf119_dma_new,
1723// .fifo = gk20a_fifo_new, 1723 .fifo = gk20a_fifo_new,
1724// .gr = gk20a_gr_new, 1724// .gr = gk20a_gr_new,
1725// .pm = gk104_pm_new, 1725// .pm = gk104_pm_new,
1726// .sw = gf100_sw_new, 1726// .sw = gf100_sw_new,
@@ -1753,7 +1753,7 @@ nvf0_chipset = {
1753 .ce[2] = gk104_ce_new, 1753 .ce[2] = gk104_ce_new,
1754 .disp = gk110_disp_new, 1754 .disp = gk110_disp_new,
1755 .dma = gf119_dma_new, 1755 .dma = gf119_dma_new,
1756// .fifo = gk104_fifo_new, 1756 .fifo = gk104_fifo_new,
1757// .gr = gk110_gr_new, 1757// .gr = gk110_gr_new,
1758 .mspdec = gk104_mspdec_new, 1758 .mspdec = gk104_mspdec_new,
1759 .msppp = gf100_msppp_new, 1759 .msppp = gf100_msppp_new,
@@ -1789,7 +1789,7 @@ nvf1_chipset = {
1789 .ce[2] = gk104_ce_new, 1789 .ce[2] = gk104_ce_new,
1790 .disp = gk110_disp_new, 1790 .disp = gk110_disp_new,
1791 .dma = gf119_dma_new, 1791 .dma = gf119_dma_new,
1792// .fifo = gk104_fifo_new, 1792 .fifo = gk104_fifo_new,
1793// .gr = gk110b_gr_new, 1793// .gr = gk110b_gr_new,
1794 .mspdec = gk104_mspdec_new, 1794 .mspdec = gk104_mspdec_new,
1795 .msppp = gf100_msppp_new, 1795 .msppp = gf100_msppp_new,
@@ -1825,7 +1825,7 @@ nv106_chipset = {
1825 .ce[2] = gk104_ce_new, 1825 .ce[2] = gk104_ce_new,
1826 .disp = gk110_disp_new, 1826 .disp = gk110_disp_new,
1827 .dma = gf119_dma_new, 1827 .dma = gf119_dma_new,
1828// .fifo = gk208_fifo_new, 1828 .fifo = gk208_fifo_new,
1829// .gr = gk208_gr_new, 1829// .gr = gk208_gr_new,
1830 .mspdec = gk104_mspdec_new, 1830 .mspdec = gk104_mspdec_new,
1831 .msppp = gf100_msppp_new, 1831 .msppp = gf100_msppp_new,
@@ -1860,7 +1860,7 @@ nv108_chipset = {
1860 .ce[2] = gk104_ce_new, 1860 .ce[2] = gk104_ce_new,
1861 .disp = gk110_disp_new, 1861 .disp = gk110_disp_new,
1862 .dma = gf119_dma_new, 1862 .dma = gf119_dma_new,
1863// .fifo = gk208_fifo_new, 1863 .fifo = gk208_fifo_new,
1864// .gr = gk208_gr_new, 1864// .gr = gk208_gr_new,
1865 .mspdec = gk104_mspdec_new, 1865 .mspdec = gk104_mspdec_new,
1866 .msppp = gf100_msppp_new, 1866 .msppp = gf100_msppp_new,
@@ -1893,7 +1893,7 @@ nv117_chipset = {
1893 .ce[2] = gk104_ce_new, 1893 .ce[2] = gk104_ce_new,
1894 .disp = gm107_disp_new, 1894 .disp = gm107_disp_new,
1895 .dma = gf119_dma_new, 1895 .dma = gf119_dma_new,
1896// .fifo = gk208_fifo_new, 1896 .fifo = gk208_fifo_new,
1897// .gr = gm107_gr_new, 1897// .gr = gm107_gr_new,
1898// .sw = gf100_sw_new, 1898// .sw = gf100_sw_new,
1899}; 1899};
@@ -1922,7 +1922,7 @@ nv124_chipset = {
1922 .ce[2] = gm204_ce_new, 1922 .ce[2] = gm204_ce_new,
1923 .disp = gm204_disp_new, 1923 .disp = gm204_disp_new,
1924 .dma = gf119_dma_new, 1924 .dma = gf119_dma_new,
1925// .fifo = gm204_fifo_new, 1925 .fifo = gm204_fifo_new,
1926// .gr = gm204_gr_new, 1926// .gr = gm204_gr_new,
1927// .sw = gf100_sw_new, 1927// .sw = gf100_sw_new,
1928}; 1928};
@@ -1951,7 +1951,7 @@ nv126_chipset = {
1951 .ce[2] = gm204_ce_new, 1951 .ce[2] = gm204_ce_new,
1952 .disp = gm204_disp_new, 1952 .disp = gm204_disp_new,
1953 .dma = gf119_dma_new, 1953 .dma = gf119_dma_new,
1954// .fifo = gm204_fifo_new, 1954 .fifo = gm204_fifo_new,
1955// .gr = gm206_gr_new, 1955// .gr = gm206_gr_new,
1956// .sw = gf100_sw_new, 1956// .sw = gf100_sw_new,
1957}; 1957};
@@ -1972,7 +1972,7 @@ nv12b_chipset = {
1972 .timer = gk20a_timer_new, 1972 .timer = gk20a_timer_new,
1973 .ce[2] = gm204_ce_new, 1973 .ce[2] = gm204_ce_new,
1974 .dma = gf119_dma_new, 1974 .dma = gf119_dma_new,
1975// .fifo = gm20b_fifo_new, 1975 .fifo = gm20b_fifo_new,
1976// .gr = gm20b_gr_new, 1976// .gr = gm20b_gr_new,
1977// .sw = gf100_sw_new, 1977// .sw = gf100_sw_new,
1978}; 1978};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
index 09a1fe1604a2..d319f5680f44 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
@@ -28,55 +28,46 @@ gf100_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0xc0: 30 case 0xc0:
31 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
32 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
33 device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; 32 device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
34 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 33 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
35 break; 34 break;
36 case 0xc4: 35 case 0xc4:
37 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
38 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 36 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
39 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 37 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
40 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 38 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
41 break; 39 break;
42 case 0xc3: 40 case 0xc3:
43 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
44 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 41 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
45 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 42 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
46 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 43 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
47 break; 44 break;
48 case 0xce: 45 case 0xce:
49 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
50 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 46 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
51 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 47 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
52 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 48 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
53 break; 49 break;
54 case 0xcf: 50 case 0xcf:
55 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
56 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 51 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
57 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 52 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
58 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 53 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
59 break; 54 break;
60 case 0xc1: 55 case 0xc1:
61 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
62 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 56 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
63 device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; 57 device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
64 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; 58 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
65 break; 59 break;
66 case 0xc8: 60 case 0xc8:
67 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
68 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 61 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
69 device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; 62 device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
70 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 63 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
71 break; 64 break;
72 case 0xd9: 65 case 0xd9:
73 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
74 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 66 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
75 device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; 67 device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
76 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; 68 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
77 break; 69 break;
78 case 0xd7: 70 case 0xd7:
79 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
80 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 71 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
81 device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; 72 device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
82 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; 73 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
index b3d25aad22f7..fe8298e02e9f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
@@ -28,48 +28,40 @@ gk104_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0xe4: 30 case 0xe4:
31 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
32 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
33 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; 32 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
34 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 33 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
35 break; 34 break;
36 case 0xe7: 35 case 0xe7:
37 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
38 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 36 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
39 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; 37 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
40 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 38 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
41 break; 39 break;
42 case 0xe6: 40 case 0xe6:
43 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
44 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 41 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
45 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; 42 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
46 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 43 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
47 break; 44 break;
48 case 0xea: 45 case 0xea:
49 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
50 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 46 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
51 device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; 47 device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
52 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 48 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
53 break; 49 break;
54 case 0xf0: 50 case 0xf0:
55 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
56 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 51 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
57 device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; 52 device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
58 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 53 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
59 break; 54 break;
60 case 0xf1: 55 case 0xf1:
61 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
62 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 56 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
63 device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; 57 device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
64 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 58 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
65 break; 59 break;
66 case 0x106: 60 case 0x106:
67 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
68 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 61 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
69 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; 62 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
70 break; 63 break;
71 case 0x108: 64 case 0x108:
72 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
73 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 65 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
74 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; 66 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
75 break; 67 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index c0c1bd3989d6..2362a634462c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device)
31 31
32#if 0 32#if 0
33#endif 33#endif
34 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
35 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 34 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
36 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; 35 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
37#if 0 36#if 0
@@ -46,7 +45,6 @@ gm100_identify(struct nvkm_device *device)
46#endif 45#endif
47#if 0 46#if 0
48#endif 47#endif
49 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
50 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 48 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
51 device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass; 49 device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
52#if 0 50#if 0
@@ -59,7 +57,6 @@ gm100_identify(struct nvkm_device *device)
59#endif 57#endif
60#if 0 58#if 0
61#endif 59#endif
62 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
63 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 60 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
64 device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass; 61 device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
65#if 0 62#if 0
@@ -67,7 +64,6 @@ gm100_identify(struct nvkm_device *device)
67 break; 64 break;
68 case 0x12b: 65 case 0x12b:
69 66
70 device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
71 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 67 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
72 device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass; 68 device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass;
73 break; 69 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index 7a71d0c1d22f..edddbaa41b43 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -28,12 +28,10 @@ nv04_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x04: 30 case 0x04:
31 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
32 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
33 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; 32 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
34 break; 33 break;
35 case 0x05: 34 case 0x05:
36 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
37 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; 35 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
38 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; 36 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
39 break; 37 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index 2b59c02fe734..f1ebb9bcda3b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -31,37 +31,30 @@ nv10_identify(struct nvkm_device *device)
31 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 31 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
32 break; 32 break;
33 case 0x15: 33 case 0x15:
34 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
35 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 34 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
36 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 35 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
37 break; 36 break;
38 case 0x16: 37 case 0x16:
39 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
40 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 38 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
41 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 39 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
42 break; 40 break;
43 case 0x1a: 41 case 0x1a:
44 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
45 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 42 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
46 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 43 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
47 break; 44 break;
48 case 0x11: 45 case 0x11:
49 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
50 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 46 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
51 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 47 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
52 break; 48 break;
53 case 0x17: 49 case 0x17:
54 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
55 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 50 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
56 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 51 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
57 break; 52 break;
58 case 0x1f: 53 case 0x1f:
59 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
60 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 54 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
61 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 55 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
62 break; 56 break;
63 case 0x18: 57 case 0x18:
64 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
65 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 58 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
66 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 59 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
67 break; 60 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index b4f8c479f3d7..f9c4dad1f8ff 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -28,22 +28,18 @@ nv20_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x20: 30 case 0x20:
31 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
32 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
33 device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; 32 device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
34 break; 33 break;
35 case 0x25: 34 case 0x25:
36 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
37 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 35 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
38 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; 36 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
39 break; 37 break;
40 case 0x28: 38 case 0x28:
41 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
42 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 39 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
43 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; 40 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
44 break; 41 break;
45 case 0x2a: 42 case 0x2a:
46 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
47 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 43 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
48 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; 44 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
49 break; 45 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index fec9e3f38a5c..b8e1e43723a3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -28,29 +28,24 @@ nv30_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x30: 30 case 0x30:
31 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
32 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
33 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; 32 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
34 break; 33 break;
35 case 0x35: 34 case 0x35:
36 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
37 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 35 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
38 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; 36 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
39 break; 37 break;
40 case 0x31: 38 case 0x31:
41 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
42 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 39 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
43 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; 40 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
44 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; 41 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
45 break; 42 break;
46 case 0x36: 43 case 0x36:
47 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
48 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 44 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
49 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; 45 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
50 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; 46 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
51 break; 47 break;
52 case 0x34: 48 case 0x34:
53 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
54 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 49 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
55 device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; 50 device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
56 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; 51 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index 553923ab0376..158ed5e395df 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -28,112 +28,96 @@ nv40_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x40: 30 case 0x40:
31 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
32 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
33 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 32 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
34 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 33 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
35 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 34 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
36 break; 35 break;
37 case 0x41: 36 case 0x41:
38 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
39 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 37 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
40 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 38 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
41 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 39 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
42 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 40 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
43 break; 41 break;
44 case 0x42: 42 case 0x42:
45 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
46 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 43 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
47 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 44 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
48 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 45 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
49 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 46 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
50 break; 47 break;
51 case 0x43: 48 case 0x43:
52 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
53 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 49 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
54 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 50 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
55 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 51 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
56 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 52 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
57 break; 53 break;
58 case 0x45: 54 case 0x45:
59 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
60 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 55 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
61 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 56 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
62 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 57 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
63 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 58 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
64 break; 59 break;
65 case 0x47: 60 case 0x47:
66 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
67 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 61 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
68 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 62 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
69 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 63 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
70 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 64 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
71 break; 65 break;
72 case 0x49: 66 case 0x49:
73 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
74 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 67 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
75 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 68 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
76 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 69 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
77 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 70 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
78 break; 71 break;
79 case 0x4b: 72 case 0x4b:
80 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
81 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 73 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
82 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 74 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
83 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 75 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
84 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 76 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
85 break; 77 break;
86 case 0x44: 78 case 0x44:
87 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
88 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 79 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
89 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 80 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
90 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 81 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
91 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 82 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
92 break; 83 break;
93 case 0x46: 84 case 0x46:
94 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
95 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 85 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
96 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 86 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
97 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 87 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
98 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 88 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
99 break; 89 break;
100 case 0x4a: 90 case 0x4a:
101 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
102 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 91 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
103 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 92 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
104 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 93 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
105 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 94 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
106 break; 95 break;
107 case 0x4c: 96 case 0x4c:
108 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
109 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 97 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
110 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 98 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
111 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 99 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
112 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 100 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
113 break; 101 break;
114 case 0x4e: 102 case 0x4e:
115 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
116 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 103 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
117 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 104 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
118 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 105 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
119 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 106 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
120 break; 107 break;
121 case 0x63: 108 case 0x63:
122 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
123 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 109 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
124 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 110 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
125 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 111 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
126 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 112 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
127 break; 113 break;
128 case 0x67: 114 case 0x67:
129 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
130 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 115 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
131 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 116 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
132 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 117 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
133 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 118 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
134 break; 119 break;
135 case 0x68: 120 case 0x68:
136 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
137 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 121 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
138 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 122 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
139 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 123 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index f4c4ded9193f..688b3e2d61ff 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -28,93 +28,79 @@ nv50_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x50: 30 case 0x50:
31 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
32 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
33 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 32 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
34 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; 33 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
35 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; 34 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
36 break; 35 break;
37 case 0x84: 36 case 0x84:
38 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
39 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 37 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
40 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 38 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
41 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 39 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
42 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 40 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
43 break; 41 break;
44 case 0x86: 42 case 0x86:
45 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
46 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 43 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
47 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 44 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
48 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 45 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
49 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 46 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
50 break; 47 break;
51 case 0x92: 48 case 0x92:
52 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
53 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 49 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
54 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 50 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
55 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 51 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
56 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 52 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
57 break; 53 break;
58 case 0x94: 54 case 0x94:
59 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
60 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 55 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
61 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 56 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
62 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 57 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
63 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 58 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
64 break; 59 break;
65 case 0x96: 60 case 0x96:
66 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
67 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 61 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
68 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 62 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
69 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 63 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
70 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 64 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
71 break; 65 break;
72 case 0x98: 66 case 0x98:
73 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
74 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 67 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
75 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 68 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
76 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 69 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
77 break; 70 break;
78 case 0xa0: 71 case 0xa0:
79 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
80 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 72 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
81 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 73 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
82 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 74 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
83 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; 75 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
84 break; 76 break;
85 case 0xaa: 77 case 0xaa:
86 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
87 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 78 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
88 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 79 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
89 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 80 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
90 break; 81 break;
91 case 0xac: 82 case 0xac:
92 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
93 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 83 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
94 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 84 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
95 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 85 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
96 break; 86 break;
97 case 0xa3: 87 case 0xa3:
98 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
99 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 88 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
100 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 89 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
101 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 90 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
102 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 91 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
103 break; 92 break;
104 case 0xa5: 93 case 0xa5:
105 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
106 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 94 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
107 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 95 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
108 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 96 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
109 break; 97 break;
110 case 0xa8: 98 case 0xa8:
111 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
112 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 99 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
113 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 100 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
114 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 101 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
115 break; 102 break;
116 case 0xaf: 103 case 0xaf:
117 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
118 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 104 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
119 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 105 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
120 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 106 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
index e51372bdbf54..2d11b328bee1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
@@ -20,9 +20,10 @@
20 * OTHER DEALINGS IN THE SOFTWARE. 20 * OTHER DEALINGS IN THE SOFTWARE.
21 */ 21 */
22#include <engine/falcon.h> 22#include <engine/falcon.h>
23#include <engine/fifo.h>
24 23
24#include <core/gpuobj.h>
25#include <subdev/timer.h> 25#include <subdev/timer.h>
26#include <engine/fifo.h>
26 27
27static int 28static int
28nvkm_falcon_oclass_get(struct nvkm_oclass *oclass, int index) 29nvkm_falcon_oclass_get(struct nvkm_oclass *oclass, int index)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
index 4525b01598a9..74993c144a84 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
@@ -7,8 +7,8 @@ nvkm-y += nvkm/engine/fifo/nv50.o
7nvkm-y += nvkm/engine/fifo/g84.o 7nvkm-y += nvkm/engine/fifo/g84.o
8nvkm-y += nvkm/engine/fifo/gf100.o 8nvkm-y += nvkm/engine/fifo/gf100.o
9nvkm-y += nvkm/engine/fifo/gk104.o 9nvkm-y += nvkm/engine/fifo/gk104.o
10nvkm-y += nvkm/engine/fifo/gk20a.o
11nvkm-y += nvkm/engine/fifo/gk208.o 10nvkm-y += nvkm/engine/fifo/gk208.o
11nvkm-y += nvkm/engine/fifo/gk20a.o
12nvkm-y += nvkm/engine/fifo/gm204.o 12nvkm-y += nvkm/engine/fifo/gm204.o
13nvkm-y += nvkm/engine/fifo/gm20b.o 13nvkm-y += nvkm/engine/fifo/gm20b.o
14 14
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
index b693127d80e1..1fbbfbe6ca9c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
@@ -25,12 +25,25 @@
25#include "chan.h" 25#include "chan.h"
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/gpuobj.h>
28#include <core/notify.h> 29#include <core/notify.h>
29 30
30#include <nvif/event.h> 31#include <nvif/event.h>
31#include <nvif/unpack.h> 32#include <nvif/unpack.h>
32 33
33void 34void
35nvkm_fifo_pause(struct nvkm_fifo *fifo, unsigned long *flags)
36{
37 return fifo->func->pause(fifo, flags);
38}
39
40void
41nvkm_fifo_start(struct nvkm_fifo *fifo, unsigned long *flags)
42{
43 return fifo->func->start(fifo, flags);
44}
45
46void
34nvkm_fifo_chan_put(struct nvkm_fifo *fifo, unsigned long flags, 47nvkm_fifo_chan_put(struct nvkm_fifo *fifo, unsigned long flags,
35 struct nvkm_fifo_chan **pchan) 48 struct nvkm_fifo_chan **pchan)
36{ 49{
@@ -95,7 +108,21 @@ nvkm_fifo_event_func = {
95 .ctor = nvkm_fifo_event_ctor, 108 .ctor = nvkm_fifo_event_ctor,
96}; 109};
97 110
98int 111static void
112nvkm_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
113{
114 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
115 fifo->func->uevent_fini(fifo);
116}
117
118static void
119nvkm_fifo_uevent_init(struct nvkm_event *event, int type, int index)
120{
121 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
122 fifo->func->uevent_init(fifo);
123}
124
125static int
99nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size, 126nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
100 struct nvkm_notify *notify) 127 struct nvkm_notify *notify)
101{ 128{
@@ -113,6 +140,13 @@ nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
113 return ret; 140 return ret;
114} 141}
115 142
143static const struct nvkm_event_func
144nvkm_fifo_uevent_func = {
145 .ctor = nvkm_fifo_uevent_ctor,
146 .init = nvkm_fifo_uevent_init,
147 .fini = nvkm_fifo_uevent_fini,
148};
149
116void 150void
117nvkm_fifo_uevent(struct nvkm_fifo *fifo) 151nvkm_fifo_uevent(struct nvkm_fifo *fifo)
118{ 152{
@@ -156,50 +190,88 @@ nvkm_fifo_class_get(struct nvkm_oclass *oclass, int index,
156 return c; 190 return c;
157} 191}
158 192
159void 193static void
160nvkm_fifo_destroy(struct nvkm_fifo *fifo) 194nvkm_fifo_intr(struct nvkm_engine *engine)
161{ 195{
162 nvkm_event_fini(&fifo->uevent); 196 struct nvkm_fifo *fifo = nvkm_fifo(engine);
197 fifo->func->intr(fifo);
198}
199
200static int
201nvkm_fifo_fini(struct nvkm_engine *engine, bool suspend)
202{
203 struct nvkm_fifo *fifo = nvkm_fifo(engine);
204 if (fifo->func->fini)
205 fifo->func->fini(fifo);
206 return 0;
207}
208
209static int
210nvkm_fifo_oneinit(struct nvkm_engine *engine)
211{
212 struct nvkm_fifo *fifo = nvkm_fifo(engine);
213 if (fifo->func->oneinit)
214 return fifo->func->oneinit(fifo);
215 return 0;
216}
217
218static int
219nvkm_fifo_init(struct nvkm_engine *engine)
220{
221 struct nvkm_fifo *fifo = nvkm_fifo(engine);
222 fifo->func->init(fifo);
223 return 0;
224}
225
226static void *
227nvkm_fifo_dtor(struct nvkm_engine *engine)
228{
229 struct nvkm_fifo *fifo = nvkm_fifo(engine);
230 void *data = fifo;
231 if (fifo->func->dtor)
232 data = fifo->func->dtor(fifo);
163 nvkm_event_fini(&fifo->cevent); 233 nvkm_event_fini(&fifo->cevent);
164 nvkm_engine_destroy(&fifo->engine); 234 nvkm_event_fini(&fifo->uevent);
235 return data;
165} 236}
166 237
167static const struct nvkm_engine_func 238static const struct nvkm_engine_func
168nvkm_fifo_func = { 239nvkm_fifo = {
240 .dtor = nvkm_fifo_dtor,
241 .oneinit = nvkm_fifo_oneinit,
242 .init = nvkm_fifo_init,
243 .fini = nvkm_fifo_fini,
244 .intr = nvkm_fifo_intr,
169 .base.sclass = nvkm_fifo_class_get, 245 .base.sclass = nvkm_fifo_class_get,
170}; 246};
171 247
172int 248int
173nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, 249nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device,
174 struct nvkm_oclass *oclass, 250 int index, int nr, struct nvkm_fifo *fifo)
175 int min, int max, int length, void **pobject)
176{ 251{
177 struct nvkm_fifo *fifo;
178 int nr = max + 1;
179 int cnt = nr - min;
180 int ret; 252 int ret;
181 253
182 ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO", 254 fifo->func = func;
183 "fifo", length, pobject);
184 fifo = *pobject;
185 if (ret)
186 return ret;
187
188 fifo->engine.func = &nvkm_fifo_func;
189 INIT_LIST_HEAD(&fifo->chan); 255 INIT_LIST_HEAD(&fifo->chan);
256 spin_lock_init(&fifo->lock);
190 257
191 fifo->nr = nr; 258 if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR))
192 if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR)) {
193 fifo->nr = NVKM_FIFO_CHID_NR; 259 fifo->nr = NVKM_FIFO_CHID_NR;
194 cnt = fifo->nr - min; 260 else
195 } 261 fifo->nr = nr;
196 bitmap_fill(fifo->mask, NVKM_FIFO_CHID_NR); 262 bitmap_clear(fifo->mask, 0, fifo->nr);
197 bitmap_clear(fifo->mask, min, cnt);
198 263
199 ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent); 264 ret = nvkm_engine_ctor(&nvkm_fifo, device, index, 0x00000100,
265 true, &fifo->engine);
200 if (ret) 266 if (ret)
201 return ret; 267 return ret;
202 268
203 spin_lock_init(&fifo->lock); 269 if (func->uevent_init) {
204 return 0; 270 ret = nvkm_event_init(&nvkm_fifo_uevent_func, 1, 1,
271 &fifo->uevent);
272 if (ret)
273 return ret;
274 }
275
276 return nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent);
205} 277}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
index a02c60f340c0..4ed06abdc917 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
@@ -24,6 +24,7 @@
24#include "chan.h" 24#include "chan.h"
25 25
26#include <core/client.h> 26#include <core/client.h>
27#include <core/gpuobj.h>
27#include <core/oproxy.h> 28#include <core/oproxy.h>
28#include <subdev/mmu.h> 29#include <subdev/mmu.h>
29#include <engine/dma.h> 30#include <engine/dma.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h
index bfec12dbf492..55dc415c5c08 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h
@@ -1,5 +1,6 @@
1#ifndef __NVKM_FIFO_CHAN_H__ 1#ifndef __NVKM_FIFO_CHAN_H__
2#define __NVKM_FIFO_CHAN_H__ 2#define __NVKM_FIFO_CHAN_H__
3#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object)
3#include "priv.h" 4#include "priv.h"
4 5
5struct nvkm_fifo_chan_func { 6struct nvkm_fifo_chan_func {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
index eafa87886643..52cbc4b47b2c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
@@ -73,7 +73,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
73 struct nv04_fifo *fifo = chan->fifo; 73 struct nv04_fifo *fifo = chan->fifo;
74 struct nvkm_device *device = fifo->base.engine.subdev.device; 74 struct nvkm_device *device = fifo->base.engine.subdev.device;
75 struct nvkm_memory *fctx = device->imem->ramfc; 75 struct nvkm_memory *fctx = device->imem->ramfc;
76 struct ramfc_desc *c; 76 const struct nv04_fifo_ramfc *c;
77 unsigned long flags; 77 unsigned long flags;
78 u32 mask = fifo->base.nr - 1; 78 u32 mask = fifo->base.nr - 1;
79 u32 data = chan->ramfc; 79 u32 data = chan->ramfc;
@@ -90,7 +90,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
90 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); 90 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0);
91 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); 91 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
92 92
93 c = fifo->ramfc_desc; 93 c = fifo->ramfc;
94 do { 94 do {
95 u32 rm = ((1ULL << c->bits) - 1) << c->regs; 95 u32 rm = ((1ULL << c->bits) - 1) << c->regs;
96 u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; 96 u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
@@ -99,7 +99,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
99 nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); 99 nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs));
100 } while ((++c)->bits); 100 } while ((++c)->bits);
101 101
102 c = fifo->ramfc_desc; 102 c = fifo->ramfc;
103 do { 103 do {
104 nvkm_wr32(device, c->regp, 0x00000000); 104 nvkm_wr32(device, c->regp, 0x00000000);
105 } while ((++c)->bits); 105 } while ((++c)->bits);
@@ -136,7 +136,7 @@ nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base)
136 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 136 struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
137 struct nv04_fifo *fifo = chan->fifo; 137 struct nv04_fifo *fifo = chan->fifo;
138 struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; 138 struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
139 struct ramfc_desc *c = fifo->ramfc_desc; 139 const struct nv04_fifo_ramfc *c = fifo->ramfc;
140 140
141 nvkm_kmap(imem->ramfc); 141 nvkm_kmap(imem->ramfc);
142 do { 142 do {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c
index 1ad16205305f..d8e4d55704d1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c
@@ -25,6 +25,7 @@
25#include "regsnv04.h" 25#include "regsnv04.h"
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/gpuobj.h>
28#include <subdev/instmem.h> 29#include <subdev/instmem.h>
29 30
30#include <nvif/class.h> 31#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c
index 2fbb9d4f0900..1424dd9b6299 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c
@@ -25,6 +25,7 @@
25#include "regsnv04.h" 25#include "regsnv04.h"
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/gpuobj.h>
28#include <subdev/instmem.h> 29#include <subdev/instmem.h>
29 30
30#include <nvif/class.h> 31#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
index 00fa9d3eff7a..ff7b529764fe 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
@@ -25,30 +25,29 @@
25#include "channv50.h" 25#include "channv50.h"
26 26
27static void 27static void
28g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) 28g84_fifo_uevent_fini(struct nvkm_fifo *fifo)
29{ 29{
30 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
31 struct nvkm_device *device = fifo->engine.subdev.device; 30 struct nvkm_device *device = fifo->engine.subdev.device;
32 nvkm_mask(device, 0x002140, 0x40000000, 0x00000000); 31 nvkm_mask(device, 0x002140, 0x40000000, 0x00000000);
33} 32}
34 33
35static void 34static void
36g84_fifo_uevent_init(struct nvkm_event *event, int type, int index) 35g84_fifo_uevent_init(struct nvkm_fifo *fifo)
37{ 36{
38 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
39 struct nvkm_device *device = fifo->engine.subdev.device; 37 struct nvkm_device *device = fifo->engine.subdev.device;
40 nvkm_mask(device, 0x002140, 0x40000000, 0x40000000); 38 nvkm_mask(device, 0x002140, 0x40000000, 0x40000000);
41} 39}
42 40
43static const struct nvkm_event_func
44g84_fifo_uevent_func = {
45 .ctor = nvkm_fifo_uevent_ctor,
46 .init = g84_fifo_uevent_init,
47 .fini = g84_fifo_uevent_fini,
48};
49
50static const struct nvkm_fifo_func 41static const struct nvkm_fifo_func
51g84_fifo_func = { 42g84_fifo = {
43 .dtor = nv50_fifo_dtor,
44 .oneinit = nv50_fifo_oneinit,
45 .init = nv50_fifo_init,
46 .intr = nv04_fifo_intr,
47 .pause = nv04_fifo_pause,
48 .start = nv04_fifo_start,
49 .uevent_init = g84_fifo_uevent_init,
50 .uevent_fini = g84_fifo_uevent_fini,
52 .chan = { 51 .chan = {
53 &g84_fifo_dma_oclass, 52 &g84_fifo_dma_oclass,
54 &g84_fifo_gpfifo_oclass, 53 &g84_fifo_gpfifo_oclass,
@@ -56,50 +55,8 @@ g84_fifo_func = {
56 }, 55 },
57}; 56};
58 57
59static int 58int
60g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 59g84_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
61 struct nvkm_oclass *oclass, void *data, u32 size,
62 struct nvkm_object **pobject)
63{ 60{
64 struct nvkm_device *device = (void *)parent; 61 return nv50_fifo_new_(&g84_fifo, device, index, pfifo);
65 struct nv50_fifo *fifo;
66 int ret;
67
68 ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo);
69 *pobject = nv_object(fifo);
70 if (ret)
71 return ret;
72
73 fifo->base.func = &g84_fifo_func;
74
75 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
76 false, &fifo->runlist[0]);
77 if (ret)
78 return ret;
79
80 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
81 false, &fifo->runlist[1]);
82 if (ret)
83 return ret;
84
85 ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &fifo->base.uevent);
86 if (ret)
87 return ret;
88
89 nv_subdev(fifo)->unit = 0x00000100;
90 nv_subdev(fifo)->intr = nv04_fifo_intr;
91 fifo->base.pause = nv04_fifo_pause;
92 fifo->base.start = nv04_fifo_start;
93 return 0;
94} 62}
95
96struct nvkm_oclass *
97g84_fifo_oclass = &(struct nvkm_oclass) {
98 .handle = NV_ENGINE(FIFO, 0x84),
99 .ofuncs = &(struct nvkm_ofuncs) {
100 .ctor = g84_fifo_ctor,
101 .dtor = nv50_fifo_dtor,
102 .init = nv50_fifo_init,
103 .fini = _nvkm_fifo_fini,
104 },
105};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
index e8598fc44796..bc094223f687 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
@@ -26,6 +26,7 @@
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/enum.h> 28#include <core/enum.h>
29#include <core/gpuobj.h>
29#include <core/handle.h> 30#include <core/handle.h>
30#include <subdev/bar.h> 31#include <subdev/bar.h>
31#include <engine/sw.h> 32#include <engine/sw.h>
@@ -33,28 +34,19 @@
33#include <nvif/class.h> 34#include <nvif/class.h>
34 35
35static void 36static void
36gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) 37gf100_fifo_uevent_init(struct nvkm_fifo *fifo)
37{ 38{
38 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
39 struct nvkm_device *device = fifo->engine.subdev.device; 39 struct nvkm_device *device = fifo->engine.subdev.device;
40 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); 40 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
41} 41}
42 42
43static void 43static void
44gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) 44gf100_fifo_uevent_fini(struct nvkm_fifo *fifo)
45{ 45{
46 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
47 struct nvkm_device *device = fifo->engine.subdev.device; 46 struct nvkm_device *device = fifo->engine.subdev.device;
48 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); 47 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
49} 48}
50 49
51static const struct nvkm_event_func
52gf100_fifo_uevent_func = {
53 .ctor = nvkm_fifo_uevent_ctor,
54 .init = gf100_fifo_uevent_init,
55 .fini = gf100_fifo_uevent_fini,
56};
57
58void 50void
59gf100_fifo_runlist_update(struct gf100_fifo *fifo) 51gf100_fifo_runlist_update(struct gf100_fifo *fifo)
60{ 52{
@@ -64,7 +56,7 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo)
64 struct nvkm_memory *cur; 56 struct nvkm_memory *cur;
65 int nr = 0; 57 int nr = 0;
66 58
67 mutex_lock(&nv_subdev(fifo)->mutex); 59 mutex_lock(&subdev->mutex);
68 cur = fifo->runlist.mem[fifo->runlist.active]; 60 cur = fifo->runlist.mem[fifo->runlist.active];
69 fifo->runlist.active = !fifo->runlist.active; 61 fifo->runlist.active = !fifo->runlist.active;
70 62
@@ -83,7 +75,7 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo)
83 !(nvkm_rd32(device, 0x00227c) & 0x00100000), 75 !(nvkm_rd32(device, 0x00227c) & 0x00100000),
84 msecs_to_jiffies(2000)) == 0) 76 msecs_to_jiffies(2000)) == 0)
85 nvkm_error(subdev, "runlist update timeout\n"); 77 nvkm_error(subdev, "runlist update timeout\n");
86 mutex_unlock(&nv_subdev(fifo)->mutex); 78 mutex_unlock(&subdev->mutex);
87} 79}
88 80
89static inline int 81static inline int
@@ -106,6 +98,8 @@ gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
106static inline struct nvkm_engine * 98static inline struct nvkm_engine *
107gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) 99gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
108{ 100{
101 struct nvkm_device *device = fifo->base.engine.subdev.device;
102
109 switch (engn) { 103 switch (engn) {
110 case 0: engn = NVDEV_ENGINE_GR; break; 104 case 0: engn = NVDEV_ENGINE_GR; break;
111 case 1: engn = NVDEV_ENGINE_MSVLD; break; 105 case 1: engn = NVDEV_ENGINE_MSVLD; break;
@@ -117,7 +111,7 @@ gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
117 return NULL; 111 return NULL;
118 } 112 }
119 113
120 return nvkm_engine(fifo, engn); 114 return nvkm_device_engine(device, engn);
121} 115}
122 116
123static void 117static void
@@ -167,7 +161,7 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
167 list_del_init(&chan->head); 161 list_del_init(&chan->head);
168 chan->killed = true; 162 chan->killed = true;
169 163
170 fifo->mask |= 1ULL << nv_engidx(engine); 164 fifo->mask |= 1ULL << engine->subdev.index;
171 schedule_work(&fifo->fault); 165 schedule_work(&fifo->fault);
172} 166}
173 167
@@ -333,7 +327,7 @@ gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit)
333 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); 327 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
334 break; 328 break;
335 default: 329 default:
336 engine = nvkm_engine(fifo, eu->data2); 330 engine = nvkm_device_engine(device, eu->data2);
337 break; 331 break;
338 } 332 }
339 } 333 }
@@ -457,10 +451,11 @@ gf100_fifo_intr_engine(struct gf100_fifo *fifo)
457} 451}
458 452
459static void 453static void
460gf100_fifo_intr(struct nvkm_subdev *subdev) 454gf100_fifo_intr(struct nvkm_fifo *base)
461{ 455{
462 struct gf100_fifo *fifo = (void *)subdev; 456 struct gf100_fifo *fifo = gf100_fifo(base);
463 struct nvkm_device *device = fifo->base.engine.subdev.device; 457 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
458 struct nvkm_device *device = subdev->device;
464 u32 mask = nvkm_rd32(device, 0x002140); 459 u32 mask = nvkm_rd32(device, 0x002140);
465 u32 stat = nvkm_rd32(device, 0x002100) & mask; 460 u32 stat = nvkm_rd32(device, 0x002100) & mask;
466 461
@@ -531,17 +526,52 @@ gf100_fifo_intr(struct nvkm_subdev *subdev)
531} 526}
532 527
533static int 528static int
534gf100_fifo_init(struct nvkm_object *object) 529gf100_fifo_oneinit(struct nvkm_fifo *base)
535{ 530{
536 struct gf100_fifo *fifo = (void *)object; 531 struct gf100_fifo *fifo = gf100_fifo(base);
537 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 532 struct nvkm_device *device = fifo->base.engine.subdev.device;
538 struct nvkm_device *device = subdev->device; 533 int ret;
539 int ret, i;
540 534
541 ret = nvkm_fifo_init(&fifo->base); 535 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
536 false, &fifo->runlist.mem[0]);
537 if (ret)
538 return ret;
539
540 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
541 false, &fifo->runlist.mem[1]);
542 if (ret) 542 if (ret)
543 return ret; 543 return ret;
544 544
545 init_waitqueue_head(&fifo->runlist.wait);
546
547 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000,
548 0x1000, false, &fifo->user.mem);
549 if (ret)
550 return ret;
551
552 ret = nvkm_bar_umap(device->bar, 128 * 0x1000, 12, &fifo->user.bar);
553 if (ret)
554 return ret;
555
556 nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
557 return 0;
558}
559
560static void
561gf100_fifo_fini(struct nvkm_fifo *base)
562{
563 struct gf100_fifo *fifo = gf100_fifo(base);
564 flush_work(&fifo->fault);
565}
566
567static void
568gf100_fifo_init(struct nvkm_fifo *base)
569{
570 struct gf100_fifo *fifo = gf100_fifo(base);
571 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
572 struct nvkm_device *device = subdev->device;
573 int i;
574
545 nvkm_wr32(device, 0x000204, 0xffffffff); 575 nvkm_wr32(device, 0x000204, 0xffffffff);
546 nvkm_wr32(device, 0x002204, 0xffffffff); 576 nvkm_wr32(device, 0x002204, 0xffffffff);
547 577
@@ -571,90 +601,44 @@ gf100_fifo_init(struct nvkm_object *object)
571 nvkm_wr32(device, 0x002100, 0xffffffff); 601 nvkm_wr32(device, 0x002100, 0xffffffff);
572 nvkm_wr32(device, 0x002140, 0x7fffffff); 602 nvkm_wr32(device, 0x002140, 0x7fffffff);
573 nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ 603 nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
574 return 0;
575} 604}
576 605
577static void 606static void *
578gf100_fifo_dtor(struct nvkm_object *object) 607gf100_fifo_dtor(struct nvkm_fifo *base)
579{ 608{
580 struct gf100_fifo *fifo = (void *)object; 609 struct gf100_fifo *fifo = gf100_fifo(base);
581
582 nvkm_vm_put(&fifo->user.bar); 610 nvkm_vm_put(&fifo->user.bar);
583 nvkm_memory_del(&fifo->user.mem); 611 nvkm_memory_del(&fifo->user.mem);
584 nvkm_memory_del(&fifo->runlist.mem[0]); 612 nvkm_memory_del(&fifo->runlist.mem[0]);
585 nvkm_memory_del(&fifo->runlist.mem[1]); 613 nvkm_memory_del(&fifo->runlist.mem[1]);
586 614 return fifo;
587 nvkm_fifo_destroy(&fifo->base);
588} 615}
589 616
590static const struct nvkm_fifo_func 617static const struct nvkm_fifo_func
591gf100_fifo_func = { 618gf100_fifo = {
619 .dtor = gf100_fifo_dtor,
620 .oneinit = gf100_fifo_oneinit,
621 .init = gf100_fifo_init,
622 .fini = gf100_fifo_fini,
623 .intr = gf100_fifo_intr,
624 .uevent_init = gf100_fifo_uevent_init,
625 .uevent_fini = gf100_fifo_uevent_fini,
592 .chan = { 626 .chan = {
593 &gf100_fifo_gpfifo_oclass, 627 &gf100_fifo_gpfifo_oclass,
594 NULL 628 NULL
595 }, 629 },
596}; 630};
597 631
598static int 632int
599gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 633gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
600 struct nvkm_oclass *oclass, void *data, u32 size,
601 struct nvkm_object **pobject)
602{ 634{
603 struct nvkm_device *device = (void *)parent;
604 struct nvkm_bar *bar = device->bar;
605 struct gf100_fifo *fifo; 635 struct gf100_fifo *fifo;
606 int ret;
607
608 ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo);
609 *pobject = nv_object(fifo);
610 if (ret)
611 return ret;
612
613 fifo->base.func = &gf100_fifo_func;
614 636
637 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
638 return -ENOMEM;
615 INIT_LIST_HEAD(&fifo->chan); 639 INIT_LIST_HEAD(&fifo->chan);
616 INIT_WORK(&fifo->fault, gf100_fifo_recover_work); 640 INIT_WORK(&fifo->fault, gf100_fifo_recover_work);
641 *pfifo = &fifo->base;
617 642
618 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, 643 return nvkm_fifo_ctor(&gf100_fifo, device, index, 128, &fifo->base);
619 false, &fifo->runlist.mem[0]);
620 if (ret)
621 return ret;
622
623 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
624 false, &fifo->runlist.mem[1]);
625 if (ret)
626 return ret;
627
628 init_waitqueue_head(&fifo->runlist.wait);
629
630 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000,
631 0x1000, false, &fifo->user.mem);
632 if (ret)
633 return ret;
634
635 ret = nvkm_bar_umap(bar, 128 * 0x1000, 12, &fifo->user.bar);
636 if (ret)
637 return ret;
638
639 nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
640
641 ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent);
642 if (ret)
643 return ret;
644
645 nv_subdev(fifo)->unit = 0x00000100;
646 nv_subdev(fifo)->intr = gf100_fifo_intr;
647 return 0;
648} 644}
649
650
651struct nvkm_oclass *
652gf100_fifo_oclass = &(struct nvkm_oclass) {
653 .handle = NV_ENGINE(FIFO, 0xc0),
654 .ofuncs = &(struct nvkm_ofuncs) {
655 .ctor = gf100_fifo_ctor,
656 .dtor = gf100_fifo_dtor,
657 .init = gf100_fifo_init,
658 .fini = _nvkm_fifo_fini,
659 },
660};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index a69f61f3ecac..465b52dee277 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -26,35 +26,27 @@
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/enum.h> 28#include <core/enum.h>
29#include <core/gpuobj.h>
29#include <core/handle.h> 30#include <core/handle.h>
30#include <subdev/bar.h> 31#include <subdev/bar.h>
31#include <engine/sw.h> 32#include <engine/sw.h>
32 33
33#include <nvif/class.h> 34#include <nvif/class.h>
34 35
35static void 36void
36gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index) 37gk104_fifo_uevent_fini(struct nvkm_fifo *fifo)
37{ 38{
38 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
39 struct nvkm_device *device = fifo->engine.subdev.device; 39 struct nvkm_device *device = fifo->engine.subdev.device;
40 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); 40 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
41} 41}
42 42
43static void 43void
44gk104_fifo_uevent_init(struct nvkm_event *event, int type, int index) 44gk104_fifo_uevent_init(struct nvkm_fifo *fifo)
45{ 45{
46 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
47 struct nvkm_device *device = fifo->engine.subdev.device; 46 struct nvkm_device *device = fifo->engine.subdev.device;
48 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); 47 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
49} 48}
50 49
51static const struct nvkm_event_func
52gk104_fifo_uevent_func = {
53 .ctor = nvkm_fifo_uevent_ctor,
54 .init = gk104_fifo_uevent_init,
55 .fini = gk104_fifo_uevent_fini,
56};
57
58void 50void
59gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) 51gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine)
60{ 52{
@@ -65,7 +57,7 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine)
65 struct nvkm_memory *cur; 57 struct nvkm_memory *cur;
66 int nr = 0; 58 int nr = 0;
67 59
68 mutex_lock(&nv_subdev(fifo)->mutex); 60 mutex_lock(&subdev->mutex);
69 cur = engn->runlist[engn->cur_runlist]; 61 cur = engn->runlist[engn->cur_runlist];
70 engn->cur_runlist = !engn->cur_runlist; 62 engn->cur_runlist = !engn->cur_runlist;
71 63
@@ -84,15 +76,16 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine)
84 (engine * 0x08)) & 0x00100000), 76 (engine * 0x08)) & 0x00100000),
85 msecs_to_jiffies(2000)) == 0) 77 msecs_to_jiffies(2000)) == 0)
86 nvkm_error(subdev, "runlist %d update timeout\n", engine); 78 nvkm_error(subdev, "runlist %d update timeout\n", engine);
87 mutex_unlock(&nv_subdev(fifo)->mutex); 79 mutex_unlock(&subdev->mutex);
88} 80}
89 81
90static inline struct nvkm_engine * 82static inline struct nvkm_engine *
91gk104_fifo_engine(struct gk104_fifo *fifo, u32 engn) 83gk104_fifo_engine(struct gk104_fifo *fifo, u32 engn)
92{ 84{
85 struct nvkm_device *device = fifo->base.engine.subdev.device;
93 u64 subdevs = gk104_fifo_engine_subdev(engn); 86 u64 subdevs = gk104_fifo_engine_subdev(engn);
94 if (subdevs) 87 if (subdevs)
95 return nvkm_engine(fifo, __ffs(subdevs)); 88 return nvkm_device_engine(device, __ffs(subdevs));
96 return NULL; 89 return NULL;
97} 90}
98 91
@@ -136,14 +129,14 @@ gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine,
136 u32 chid = chan->base.chid; 129 u32 chid = chan->base.chid;
137 130
138 nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", 131 nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
139 nvkm_subdev_name[nv_subdev(engine)->index], chid); 132 nvkm_subdev_name[engine->subdev.index], chid);
140 assert_spin_locked(&fifo->base.lock); 133 assert_spin_locked(&fifo->base.lock);
141 134
142 nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); 135 nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800);
143 list_del_init(&chan->head); 136 list_del_init(&chan->head);
144 chan->killed = true; 137 chan->killed = true;
145 138
146 fifo->mask |= 1ULL << nv_engidx(engine); 139 fifo->mask |= 1ULL << engine->subdev.index;
147 schedule_work(&fifo->fault); 140 schedule_work(&fifo->fault);
148} 141}
149 142
@@ -399,7 +392,7 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
399 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); 392 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
400 break; 393 break;
401 default: 394 default:
402 engine = nvkm_engine(fifo, eu->data2); 395 engine = nvkm_device_engine(device, eu->data2);
403 break; 396 break;
404 } 397 }
405 } 398 }
@@ -542,11 +535,12 @@ gk104_fifo_intr_engine(struct gk104_fifo *fifo)
542 nvkm_fifo_uevent(&fifo->base); 535 nvkm_fifo_uevent(&fifo->base);
543} 536}
544 537
545static void 538void
546gk104_fifo_intr(struct nvkm_subdev *subdev) 539gk104_fifo_intr(struct nvkm_fifo *base)
547{ 540{
548 struct gk104_fifo *fifo = (void *)subdev; 541 struct gk104_fifo *fifo = gk104_fifo(base);
549 struct nvkm_device *device = fifo->base.engine.subdev.device; 542 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
543 struct nvkm_device *device = subdev->device;
550 u32 mask = nvkm_rd32(device, 0x002140); 544 u32 mask = nvkm_rd32(device, 0x002140);
551 u32 stat = nvkm_rd32(device, 0x002100) & mask; 545 u32 stat = nvkm_rd32(device, 0x002100) & mask;
552 546
@@ -633,33 +627,62 @@ gk104_fifo_intr(struct nvkm_subdev *subdev)
633 } 627 }
634} 628}
635 629
630void
631gk104_fifo_fini(struct nvkm_fifo *base)
632{
633 struct gk104_fifo *fifo = gk104_fifo(base);
634 struct nvkm_device *device = fifo->base.engine.subdev.device;
635 flush_work(&fifo->fault);
636 /* allow mmu fault interrupts, even when we're not using fifo */
637 nvkm_mask(device, 0x002140, 0x10000000, 0x10000000);
638}
639
636int 640int
637gk104_fifo_fini(struct nvkm_object *object, bool suspend) 641gk104_fifo_oneinit(struct nvkm_fifo *base)
638{ 642{
639 struct gk104_fifo *fifo = (void *)object; 643 struct gk104_fifo *fifo = gk104_fifo(base);
640 struct nvkm_device *device = fifo->base.engine.subdev.device; 644 struct nvkm_device *device = fifo->base.engine.subdev.device;
641 int ret; 645 int ret, i;
642 646
643 ret = nvkm_fifo_fini(&fifo->base, suspend); 647 for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) {
648 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
649 0x8000, 0x1000, false,
650 &fifo->engine[i].runlist[0]);
651 if (ret)
652 return ret;
653
654 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
655 0x8000, 0x1000, false,
656 &fifo->engine[i].runlist[1]);
657 if (ret)
658 return ret;
659
660 init_waitqueue_head(&fifo->engine[i].wait);
661 INIT_LIST_HEAD(&fifo->engine[i].chan);
662 }
663
664 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
665 fifo->base.nr * 0x200, 0x1000, true,
666 &fifo->user.mem);
644 if (ret) 667 if (ret)
645 return ret; 668 return ret;
646 669
647 /* allow mmu fault interrupts, even when we're not using fifo */ 670 ret = nvkm_bar_umap(device->bar, fifo->base.nr * 0x200, 12,
648 nvkm_mask(device, 0x002140, 0x10000000, 0x10000000); 671 &fifo->user.bar);
672 if (ret)
673 return ret;
674
675 nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
649 return 0; 676 return 0;
650} 677}
651 678
652int 679void
653gk104_fifo_init(struct nvkm_object *object) 680gk104_fifo_init(struct nvkm_fifo *base)
654{ 681{
655 struct gk104_fifo *fifo = (void *)object; 682 struct gk104_fifo *fifo = gk104_fifo(base);
656 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 683 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
657 struct nvkm_device *device = subdev->device; 684 struct nvkm_device *device = subdev->device;
658 int ret, i; 685 int i;
659
660 ret = nvkm_fifo_init(&fifo->base);
661 if (ret)
662 return ret;
663 686
664 /* enable all available PBDMA units */ 687 /* enable all available PBDMA units */
665 nvkm_wr32(device, 0x000204, 0xffffffff); 688 nvkm_wr32(device, 0x000204, 0xffffffff);
@@ -683,13 +706,12 @@ gk104_fifo_init(struct nvkm_object *object)
683 706
684 nvkm_wr32(device, 0x002100, 0xffffffff); 707 nvkm_wr32(device, 0x002100, 0xffffffff);
685 nvkm_wr32(device, 0x002140, 0x7fffffff); 708 nvkm_wr32(device, 0x002140, 0x7fffffff);
686 return 0;
687} 709}
688 710
689void 711void *
690gk104_fifo_dtor(struct nvkm_object *object) 712gk104_fifo_dtor(struct nvkm_fifo *base)
691{ 713{
692 struct gk104_fifo *fifo = (void *)object; 714 struct gk104_fifo *fifo = gk104_fifo(base);
693 int i; 715 int i;
694 716
695 nvkm_vm_put(&fifo->user.bar); 717 nvkm_vm_put(&fifo->user.bar);
@@ -700,11 +722,32 @@ gk104_fifo_dtor(struct nvkm_object *object)
700 nvkm_memory_del(&fifo->engine[i].runlist[0]); 722 nvkm_memory_del(&fifo->engine[i].runlist[0]);
701 } 723 }
702 724
703 nvkm_fifo_destroy(&fifo->base); 725 return fifo;
726}
727
728int
729gk104_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
730 int index, int nr, struct nvkm_fifo **pfifo)
731{
732 struct gk104_fifo *fifo;
733
734 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
735 return -ENOMEM;
736 INIT_WORK(&fifo->fault, gk104_fifo_recover_work);
737 *pfifo = &fifo->base;
738
739 return nvkm_fifo_ctor(func, device, index, nr, &fifo->base);
704} 740}
705 741
706static const struct nvkm_fifo_func 742static const struct nvkm_fifo_func
707gk104_fifo_func = { 743gk104_fifo = {
744 .dtor = gk104_fifo_dtor,
745 .oneinit = gk104_fifo_oneinit,
746 .init = gk104_fifo_init,
747 .fini = gk104_fifo_fini,
748 .intr = gk104_fifo_intr,
749 .uevent_init = gk104_fifo_uevent_init,
750 .uevent_fini = gk104_fifo_uevent_fini,
708 .chan = { 751 .chan = {
709 &gk104_fifo_gpfifo_oclass, 752 &gk104_fifo_gpfifo_oclass,
710 NULL 753 NULL
@@ -712,72 +755,7 @@ gk104_fifo_func = {
712}; 755};
713 756
714int 757int
715gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 758gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
716 struct nvkm_oclass *oclass, void *data, u32 size,
717 struct nvkm_object **pobject)
718{ 759{
719 struct nvkm_device *device = (void *)parent; 760 return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo);
720 struct nvkm_bar *bar = device->bar;
721 struct gk104_fifo_impl *impl = (void *)oclass;
722 struct gk104_fifo *fifo;
723 int ret, i;
724
725 ret = nvkm_fifo_create(parent, engine, oclass, 0,
726 impl->channels - 1, &fifo);
727 *pobject = nv_object(fifo);
728 if (ret)
729 return ret;
730
731 fifo->base.func = &gk104_fifo_func;
732
733 INIT_WORK(&fifo->fault, gk104_fifo_recover_work);
734
735 for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) {
736 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
737 0x8000, 0x1000, false,
738 &fifo->engine[i].runlist[0]);
739 if (ret)
740 return ret;
741
742 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
743 0x8000, 0x1000, false,
744 &fifo->engine[i].runlist[1]);
745 if (ret)
746 return ret;
747
748 init_waitqueue_head(&fifo->engine[i].wait);
749 INIT_LIST_HEAD(&fifo->engine[i].chan);
750 }
751
752 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
753 impl->channels * 0x200, 0x1000,
754 true, &fifo->user.mem);
755 if (ret)
756 return ret;
757
758 ret = nvkm_bar_umap(bar, impl->channels * 0x200, 12, &fifo->user.bar);
759 if (ret)
760 return ret;
761
762 nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
763
764 ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &fifo->base.uevent);
765 if (ret)
766 return ret;
767
768 nv_subdev(fifo)->unit = 0x00000100;
769 nv_subdev(fifo)->intr = gk104_fifo_intr;
770 return 0;
771} 761}
772
773struct nvkm_oclass *
774gk104_fifo_oclass = &(struct gk104_fifo_impl) {
775 .base.handle = NV_ENGINE(FIFO, 0xe0),
776 .base.ofuncs = &(struct nvkm_ofuncs) {
777 .ctor = gk104_fifo_ctor,
778 .dtor = gk104_fifo_dtor,
779 .init = gk104_fifo_init,
780 .fini = gk104_fifo_fini,
781 },
782 .channels = 4096,
783}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
index 1103e6b1ee5a..7a5c544a5ffb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
@@ -26,23 +26,17 @@ struct gk104_fifo {
26 int spoon_nr; 26 int spoon_nr;
27}; 27};
28 28
29struct gk104_fifo_impl { 29int gk104_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *,
30 struct nvkm_oclass base; 30 int index, int nr, struct nvkm_fifo **);
31 u32 channels; 31void *gk104_fifo_dtor(struct nvkm_fifo *);
32}; 32int gk104_fifo_oneinit(struct nvkm_fifo *);
33 33void gk104_fifo_init(struct nvkm_fifo *);
34int gk104_fifo_ctor(struct nvkm_object *, struct nvkm_object *, 34void gk104_fifo_fini(struct nvkm_fifo *);
35 struct nvkm_oclass *, void *, u32, 35void gk104_fifo_intr(struct nvkm_fifo *);
36 struct nvkm_object **); 36void gk104_fifo_uevent_init(struct nvkm_fifo *);
37void gk104_fifo_dtor(struct nvkm_object *); 37void gk104_fifo_uevent_fini(struct nvkm_fifo *);
38int gk104_fifo_init(struct nvkm_object *);
39int gk104_fifo_fini(struct nvkm_object *, bool);
40void gk104_fifo_runlist_update(struct gk104_fifo *, u32 engine); 38void gk104_fifo_runlist_update(struct gk104_fifo *, u32 engine);
41 39
42int gm204_fifo_ctor(struct nvkm_object *, struct nvkm_object *,
43 struct nvkm_oclass *, void *, u32,
44 struct nvkm_object **);
45
46static inline u64 40static inline u64
47gk104_fifo_engine_subdev(int engine) 41gk104_fifo_engine_subdev(int engine)
48{ 42{
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
index 927092217a06..ce01c1a7d41c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
@@ -22,15 +22,25 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include "gk104.h" 24#include "gk104.h"
25#include "changk104.h"
25 26
26struct nvkm_oclass * 27static const struct nvkm_fifo_func
27gk208_fifo_oclass = &(struct gk104_fifo_impl) { 28gk208_fifo = {
28 .base.handle = NV_ENGINE(FIFO, 0x08), 29 .dtor = gk104_fifo_dtor,
29 .base.ofuncs = &(struct nvkm_ofuncs) { 30 .oneinit = gk104_fifo_oneinit,
30 .ctor = gk104_fifo_ctor, 31 .init = gk104_fifo_init,
31 .dtor = gk104_fifo_dtor, 32 .fini = gk104_fifo_fini,
32 .init = gk104_fifo_init, 33 .intr = gk104_fifo_intr,
33 .fini = _nvkm_fifo_fini, 34 .uevent_init = gk104_fifo_uevent_init,
35 .uevent_fini = gk104_fifo_uevent_fini,
36 .chan = {
37 &gk104_fifo_gpfifo_oclass,
38 NULL
34 }, 39 },
35 .channels = 1024, 40};
36}.base; 41
42int
43gk208_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
44{
45 return gk104_fifo_new_(&gk208_fifo, device, index, 1024, pfifo);
46}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
index b30dc87a1357..b47fe98f4181 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
@@ -20,15 +20,25 @@
20 * DEALINGS IN THE SOFTWARE. 20 * DEALINGS IN THE SOFTWARE.
21 */ 21 */
22#include "gk104.h" 22#include "gk104.h"
23#include "changk104.h"
23 24
24struct nvkm_oclass * 25static const struct nvkm_fifo_func
25gk20a_fifo_oclass = &(struct gk104_fifo_impl) { 26gk20a_fifo = {
26 .base.handle = NV_ENGINE(FIFO, 0xea), 27 .dtor = gk104_fifo_dtor,
27 .base.ofuncs = &(struct nvkm_ofuncs) { 28 .oneinit = gk104_fifo_oneinit,
28 .ctor = gk104_fifo_ctor, 29 .init = gk104_fifo_init,
29 .dtor = gk104_fifo_dtor, 30 .fini = gk104_fifo_fini,
30 .init = gk104_fifo_init, 31 .intr = gk104_fifo_intr,
31 .fini = gk104_fifo_fini, 32 .uevent_init = gk104_fifo_uevent_init,
33 .uevent_fini = gk104_fifo_uevent_fini,
34 .chan = {
35 &gk104_fifo_gpfifo_oclass,
36 NULL
32 }, 37 },
33 .channels = 128, 38};
34}.base; 39
40int
41gk20a_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
42{
43 return gk104_fifo_new_(&gk20a_fifo, device, index, 128, pfifo);
44}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c
index 18c68ac741a0..2db629f1bf7e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c
@@ -25,7 +25,14 @@
25#include "changk104.h" 25#include "changk104.h"
26 26
27static const struct nvkm_fifo_func 27static const struct nvkm_fifo_func
28gm204_fifo_func = { 28gm204_fifo = {
29 .dtor = gk104_fifo_dtor,
30 .oneinit = gk104_fifo_oneinit,
31 .init = gk104_fifo_init,
32 .fini = gk104_fifo_fini,
33 .intr = gk104_fifo_intr,
34 .uevent_init = gk104_fifo_uevent_init,
35 .uevent_fini = gk104_fifo_uevent_fini,
29 .chan = { 36 .chan = {
30 &gm204_fifo_gpfifo_oclass, 37 &gm204_fifo_gpfifo_oclass,
31 NULL 38 NULL
@@ -33,26 +40,7 @@ gm204_fifo_func = {
33}; 40};
34 41
35int 42int
36gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 43gm204_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
37 struct nvkm_oclass *oclass, void *data, u32 size,
38 struct nvkm_object **pobject)
39{ 44{
40 int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject); 45 return gk104_fifo_new_(&gm204_fifo, device, index, 4096, pfifo);
41 if (ret == 0) {
42 struct gk104_fifo *fifo = (void *)*pobject;
43 fifo->base.func = &gm204_fifo_func;
44 }
45 return ret;
46} 46}
47
48struct nvkm_oclass *
49gm204_fifo_oclass = &(struct gk104_fifo_impl) {
50 .base.handle = NV_ENGINE(FIFO, 0x24),
51 .base.ofuncs = &(struct nvkm_ofuncs) {
52 .ctor = gm204_fifo_ctor,
53 .dtor = gk104_fifo_dtor,
54 .init = gk104_fifo_init,
55 .fini = _nvkm_fifo_fini,
56 },
57 .channels = 4096,
58}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c
index 4abf547c34e6..ae6375d9760f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c
@@ -20,15 +20,25 @@
20 * DEALINGS IN THE SOFTWARE. 20 * DEALINGS IN THE SOFTWARE.
21 */ 21 */
22#include "gk104.h" 22#include "gk104.h"
23#include "changk104.h"
23 24
24struct nvkm_oclass * 25static const struct nvkm_fifo_func
25gm20b_fifo_oclass = &(struct gk104_fifo_impl) { 26gm20b_fifo = {
26 .base.handle = NV_ENGINE(FIFO, 0x2b), 27 .dtor = gk104_fifo_dtor,
27 .base.ofuncs = &(struct nvkm_ofuncs) { 28 .oneinit = gk104_fifo_oneinit,
28 .ctor = gm204_fifo_ctor, 29 .init = gk104_fifo_init,
29 .dtor = gk104_fifo_dtor, 30 .fini = gk104_fifo_fini,
30 .init = gk104_fifo_init, 31 .intr = gk104_fifo_intr,
31 .fini = gk104_fifo_fini, 32 .uevent_init = gk104_fifo_uevent_init,
33 .uevent_fini = gk104_fifo_uevent_fini,
34 .chan = {
35 &gm204_fifo_gpfifo_oclass,
36 NULL
32 }, 37 },
33 .channels = 512, 38};
34}.base; 39
40int
41gm20b_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
42{
43 return gk104_fifo_new_(&gm20b_fifo, device, index, 512, pfifo);
44}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
index eb9195a6f375..5d76c3013a80 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
@@ -24,6 +24,7 @@
24#include "changf100.h" 24#include "changf100.h"
25 25
26#include <core/client.h> 26#include <core/client.h>
27#include <core/gpuobj.h>
27#include <subdev/fb.h> 28#include <subdev/fb.h>
28#include <subdev/timer.h> 29#include <subdev/timer.h>
29 30
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
index 2595cf92ff80..fe39981915b6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
@@ -24,6 +24,7 @@
24#include "changk104.h" 24#include "changk104.h"
25 25
26#include <core/client.h> 26#include <core/client.h>
27#include <core/gpuobj.h>
27#include <subdev/fb.h> 28#include <subdev/fb.h>
28#include <subdev/mmu.h> 29#include <subdev/mmu.h>
29#include <subdev/timer.h> 30#include <subdev/timer.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
index d1ad3fa72c34..e6f04e87139a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
@@ -32,8 +32,8 @@
32#include <subdev/timer.h> 32#include <subdev/timer.h>
33#include <engine/sw.h> 33#include <engine/sw.h>
34 34
35static struct ramfc_desc 35static const struct nv04_fifo_ramfc
36nv04_ramfc[] = { 36nv04_fifo_ramfc[] = {
37 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 37 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
38 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 38 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
39 { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 39 { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
@@ -46,10 +46,10 @@ nv04_ramfc[] = {
46}; 46};
47 47
48void 48void
49nv04_fifo_pause(struct nvkm_fifo *obj, unsigned long *pflags) 49nv04_fifo_pause(struct nvkm_fifo *base, unsigned long *pflags)
50__acquires(fifo->base.lock) 50__acquires(fifo->base.lock)
51{ 51{
52 struct nv04_fifo *fifo = container_of(obj, typeof(*fifo), base); 52 struct nv04_fifo *fifo = nv04_fifo(base);
53 struct nvkm_device *device = fifo->base.engine.subdev.device; 53 struct nvkm_device *device = fifo->base.engine.subdev.device;
54 unsigned long flags; 54 unsigned long flags;
55 55
@@ -82,10 +82,10 @@ __acquires(fifo->base.lock)
82} 82}
83 83
84void 84void
85nv04_fifo_start(struct nvkm_fifo *obj, unsigned long *pflags) 85nv04_fifo_start(struct nvkm_fifo *base, unsigned long *pflags)
86__releases(fifo->base.lock) 86__releases(fifo->base.lock)
87{ 87{
88 struct nv04_fifo *fifo = container_of(obj, typeof(*fifo), base); 88 struct nv04_fifo *fifo = nv04_fifo(base);
89 struct nvkm_device *device = fifo->base.engine.subdev.device; 89 struct nvkm_device *device = fifo->base.engine.subdev.device;
90 unsigned long flags = *pflags; 90 unsigned long flags = *pflags;
91 91
@@ -236,10 +236,11 @@ nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid)
236} 236}
237 237
238void 238void
239nv04_fifo_intr(struct nvkm_subdev *subdev) 239nv04_fifo_intr(struct nvkm_fifo *base)
240{ 240{
241 struct nv04_fifo *fifo = nv04_fifo(base);
242 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
241 struct nvkm_device *device = subdev->device; 243 struct nvkm_device *device = subdev->device;
242 struct nv04_fifo *fifo = (void *)subdev;
243 u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0); 244 u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0);
244 u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask; 245 u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask;
245 u32 reassign, chid, get, sem; 246 u32 reassign, chid, get, sem;
@@ -293,20 +294,15 @@ nv04_fifo_intr(struct nvkm_subdev *subdev)
293 nvkm_wr32(device, NV03_PFIFO_CACHES, reassign); 294 nvkm_wr32(device, NV03_PFIFO_CACHES, reassign);
294} 295}
295 296
296int 297void
297nv04_fifo_init(struct nvkm_object *object) 298nv04_fifo_init(struct nvkm_fifo *base)
298{ 299{
299 struct nv04_fifo *fifo = (void *)object; 300 struct nv04_fifo *fifo = nv04_fifo(base);
300 struct nvkm_device *device = fifo->base.engine.subdev.device; 301 struct nvkm_device *device = fifo->base.engine.subdev.device;
301 struct nvkm_instmem *imem = device->imem; 302 struct nvkm_instmem *imem = device->imem;
302 struct nvkm_ramht *ramht = imem->ramht; 303 struct nvkm_ramht *ramht = imem->ramht;
303 struct nvkm_memory *ramro = imem->ramro; 304 struct nvkm_memory *ramro = imem->ramro;
304 struct nvkm_memory *ramfc = imem->ramfc; 305 struct nvkm_memory *ramfc = imem->ramfc;
305 int ret;
306
307 ret = nvkm_fifo_init(&fifo->base);
308 if (ret)
309 return ret;
310 306
311 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); 307 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);
312 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 308 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
@@ -325,54 +321,44 @@ nv04_fifo_init(struct nvkm_object *object)
325 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 321 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
326 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 322 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
327 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 323 nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
328 return 0;
329} 324}
330 325
331void 326int
332nv04_fifo_dtor(struct nvkm_object *object) 327nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
333{ 328 int index, int nr, const struct nv04_fifo_ramfc *ramfc,
334 struct nv04_fifo *fifo = (void *)object; 329 struct nvkm_fifo **pfifo)
335 nvkm_fifo_destroy(&fifo->base);
336}
337
338static const struct nvkm_fifo_func
339nv04_fifo_func = {
340 .chan = {
341 &nv04_fifo_dma_oclass,
342 NULL
343 },
344};
345
346static int
347nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
348 struct nvkm_oclass *oclass, void *data, u32 size,
349 struct nvkm_object **pobject)
350{ 330{
351 struct nv04_fifo *fifo; 331 struct nv04_fifo *fifo;
352 int ret; 332 int ret;
353 333
354 ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &fifo); 334 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
355 *pobject = nv_object(fifo); 335 return -ENOMEM;
336 fifo->ramfc = ramfc;
337 *pfifo = &fifo->base;
338
339 ret = nvkm_fifo_ctor(func, device, index, nr, &fifo->base);
356 if (ret) 340 if (ret)
357 return ret; 341 return ret;
358 342
359 fifo->base.func = &nv04_fifo_func; 343 set_bit(nr - 1, fifo->base.mask); /* inactive channel */
360
361 nv_subdev(fifo)->unit = 0x00000100;
362 nv_subdev(fifo)->intr = nv04_fifo_intr;
363 fifo->base.pause = nv04_fifo_pause;
364 fifo->base.start = nv04_fifo_start;
365 fifo->ramfc_desc = nv04_ramfc;
366 return 0; 344 return 0;
367} 345}
368 346
369struct nvkm_oclass * 347static const struct nvkm_fifo_func
370nv04_fifo_oclass = &(struct nvkm_oclass) { 348nv04_fifo = {
371 .handle = NV_ENGINE(FIFO, 0x04), 349 .init = nv04_fifo_init,
372 .ofuncs = &(struct nvkm_ofuncs) { 350 .intr = nv04_fifo_intr,
373 .ctor = nv04_fifo_ctor, 351 .pause = nv04_fifo_pause,
374 .dtor = nv04_fifo_dtor, 352 .start = nv04_fifo_start,
375 .init = nv04_fifo_init, 353 .chan = {
376 .fini = _nvkm_fifo_fini, 354 &nv04_fifo_dma_oclass,
355 NULL
377 }, 356 },
378}; 357};
358
359int
360nv04_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
361{
362 return nv04_fifo_new_(&nv04_fifo, device, index, 16,
363 nv04_fifo_ramfc, pfifo);
364}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
index c33dc56f8e02..03f60004bf7c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
@@ -3,7 +3,7 @@
3#define nv04_fifo(p) container_of((p), struct nv04_fifo, base) 3#define nv04_fifo(p) container_of((p), struct nv04_fifo, base)
4#include "priv.h" 4#include "priv.h"
5 5
6struct ramfc_desc { 6struct nv04_fifo_ramfc {
7 unsigned bits:6; 7 unsigned bits:6;
8 unsigned ctxs:5; 8 unsigned ctxs:5;
9 unsigned ctxp:8; 9 unsigned ctxp:8;
@@ -13,9 +13,11 @@ struct ramfc_desc {
13 13
14struct nv04_fifo { 14struct nv04_fifo {
15 struct nvkm_fifo base; 15 struct nvkm_fifo base;
16 struct ramfc_desc *ramfc_desc; 16 const struct nv04_fifo_ramfc *ramfc;
17}; 17};
18 18
19void nv04_fifo_dtor(struct nvkm_object *); 19int nv04_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *,
20int nv04_fifo_init(struct nvkm_object *); 20 int index, int nr, const struct nv04_fifo_ramfc *,
21 struct nvkm_fifo **);
22void nv04_fifo_init(struct nvkm_fifo *);
21#endif 23#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
index d7fab9598fb0..f9a87deb2b3d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
@@ -25,8 +25,8 @@
25#include "channv04.h" 25#include "channv04.h"
26#include "regsnv04.h" 26#include "regsnv04.h"
27 27
28static struct ramfc_desc 28static const struct nv04_fifo_ramfc
29nv10_ramfc[] = { 29nv10_fifo_ramfc[] = {
30 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 30 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
31 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 31 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
32 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, 32 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
@@ -40,43 +40,20 @@ nv10_ramfc[] = {
40}; 40};
41 41
42static const struct nvkm_fifo_func 42static const struct nvkm_fifo_func
43nv10_fifo_func = { 43nv10_fifo = {
44 .init = nv04_fifo_init,
45 .intr = nv04_fifo_intr,
46 .pause = nv04_fifo_pause,
47 .start = nv04_fifo_start,
44 .chan = { 48 .chan = {
45 &nv10_fifo_dma_oclass, 49 &nv10_fifo_dma_oclass,
46 NULL 50 NULL
47 }, 51 },
48}; 52};
49 53
50static int 54int
51nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 55nv10_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
52 struct nvkm_oclass *oclass, void *data, u32 size,
53 struct nvkm_object **pobject)
54{ 56{
55 struct nv04_fifo *fifo; 57 return nv04_fifo_new_(&nv10_fifo, device, index, 32,
56 int ret; 58 nv10_fifo_ramfc, pfifo);
57
58 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo);
59 *pobject = nv_object(fifo);
60 if (ret)
61 return ret;
62
63 fifo->base.func = &nv10_fifo_func;
64
65 nv_subdev(fifo)->unit = 0x00000100;
66 nv_subdev(fifo)->intr = nv04_fifo_intr;
67 fifo->base.pause = nv04_fifo_pause;
68 fifo->base.start = nv04_fifo_start;
69 fifo->ramfc_desc = nv10_ramfc;
70 return 0;
71} 59}
72
73struct nvkm_oclass *
74nv10_fifo_oclass = &(struct nvkm_oclass) {
75 .handle = NV_ENGINE(FIFO, 0x10),
76 .ofuncs = &(struct nvkm_ofuncs) {
77 .ctor = nv10_fifo_ctor,
78 .dtor = nv04_fifo_dtor,
79 .init = nv04_fifo_init,
80 .fini = _nvkm_fifo_fini,
81 },
82};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
index a8e28fc24e75..f6d383a21222 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
@@ -28,8 +28,8 @@
28#include <core/ramht.h> 28#include <core/ramht.h>
29#include <subdev/instmem.h> 29#include <subdev/instmem.h>
30 30
31static struct ramfc_desc 31static const struct nv04_fifo_ramfc
32nv17_ramfc[] = { 32nv17_fifo_ramfc[] = {
33 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 33 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
34 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 34 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
35 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, 35 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
@@ -47,20 +47,15 @@ nv17_ramfc[] = {
47 {} 47 {}
48}; 48};
49 49
50static int 50static void
51nv17_fifo_init(struct nvkm_object *object) 51nv17_fifo_init(struct nvkm_fifo *base)
52{ 52{
53 struct nv04_fifo *fifo = (void *)object; 53 struct nv04_fifo *fifo = nv04_fifo(base);
54 struct nvkm_device *device = fifo->base.engine.subdev.device; 54 struct nvkm_device *device = fifo->base.engine.subdev.device;
55 struct nvkm_instmem *imem = device->imem; 55 struct nvkm_instmem *imem = device->imem;
56 struct nvkm_ramht *ramht = imem->ramht; 56 struct nvkm_ramht *ramht = imem->ramht;
57 struct nvkm_memory *ramro = imem->ramro; 57 struct nvkm_memory *ramro = imem->ramro;
58 struct nvkm_memory *ramfc = imem->ramfc; 58 struct nvkm_memory *ramfc = imem->ramfc;
59 int ret;
60
61 ret = nvkm_fifo_init(&fifo->base);
62 if (ret)
63 return ret;
64 59
65 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); 60 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);
66 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 61 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
@@ -80,47 +75,23 @@ nv17_fifo_init(struct nvkm_object *object)
80 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 75 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
81 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 76 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
82 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 77 nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
83 return 0;
84} 78}
85 79
86static const struct nvkm_fifo_func 80static const struct nvkm_fifo_func
87nv17_fifo_func = { 81nv17_fifo = {
82 .init = nv17_fifo_init,
83 .intr = nv04_fifo_intr,
84 .pause = nv04_fifo_pause,
85 .start = nv04_fifo_start,
88 .chan = { 86 .chan = {
89 &nv17_fifo_dma_oclass, 87 &nv17_fifo_dma_oclass,
90 NULL 88 NULL
91 }, 89 },
92}; 90};
93 91
94static int 92int
95nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 93nv17_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
96 struct nvkm_oclass *oclass, void *data, u32 size,
97 struct nvkm_object **pobject)
98{ 94{
99 struct nv04_fifo *fifo; 95 return nv04_fifo_new_(&nv17_fifo, device, index, 32,
100 int ret; 96 nv17_fifo_ramfc, pfifo);
101
102 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo);
103 *pobject = nv_object(fifo);
104 if (ret)
105 return ret;
106
107 fifo->base.func = &nv17_fifo_func;
108
109 nv_subdev(fifo)->unit = 0x00000100;
110 nv_subdev(fifo)->intr = nv04_fifo_intr;
111 fifo->base.pause = nv04_fifo_pause;
112 fifo->base.start = nv04_fifo_start;
113 fifo->ramfc_desc = nv17_ramfc;
114 return 0;
115} 97}
116
117struct nvkm_oclass *
118nv17_fifo_oclass = &(struct nvkm_oclass) {
119 .handle = NV_ENGINE(FIFO, 0x17),
120 .ofuncs = &(struct nvkm_ofuncs) {
121 .ctor = nv17_fifo_ctor,
122 .dtor = nv04_fifo_dtor,
123 .init = nv17_fifo_init,
124 .fini = _nvkm_fifo_fini,
125 },
126};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
index aca146377d36..8c7ba32763c4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
@@ -29,8 +29,8 @@
29#include <subdev/fb.h> 29#include <subdev/fb.h>
30#include <subdev/instmem.h> 30#include <subdev/instmem.h>
31 31
32static struct ramfc_desc 32static const struct nv04_fifo_ramfc
33nv40_ramfc[] = { 33nv40_fifo_ramfc[] = {
34 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 34 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
35 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 35 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
36 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, 36 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
@@ -56,21 +56,16 @@ nv40_ramfc[] = {
56 {} 56 {}
57}; 57};
58 58
59static int 59static void
60nv40_fifo_init(struct nvkm_object *object) 60nv40_fifo_init(struct nvkm_fifo *base)
61{ 61{
62 struct nv04_fifo *fifo = (void *)object; 62 struct nv04_fifo *fifo = nv04_fifo(base);
63 struct nvkm_device *device = fifo->base.engine.subdev.device; 63 struct nvkm_device *device = fifo->base.engine.subdev.device;
64 struct nvkm_fb *fb = device->fb; 64 struct nvkm_fb *fb = device->fb;
65 struct nvkm_instmem *imem = device->imem; 65 struct nvkm_instmem *imem = device->imem;
66 struct nvkm_ramht *ramht = imem->ramht; 66 struct nvkm_ramht *ramht = imem->ramht;
67 struct nvkm_memory *ramro = imem->ramro; 67 struct nvkm_memory *ramro = imem->ramro;
68 struct nvkm_memory *ramfc = imem->ramfc; 68 struct nvkm_memory *ramfc = imem->ramfc;
69 int ret;
70
71 ret = nvkm_fifo_init(&fifo->base);
72 if (ret)
73 return ret;
74 69
75 nvkm_wr32(device, 0x002040, 0x000000ff); 70 nvkm_wr32(device, 0x002040, 0x000000ff);
76 nvkm_wr32(device, 0x002044, 0x2101ffff); 71 nvkm_wr32(device, 0x002044, 0x2101ffff);
@@ -81,7 +76,7 @@ nv40_fifo_init(struct nvkm_object *object)
81 (ramht->gpuobj->addr >> 8)); 76 (ramht->gpuobj->addr >> 8));
82 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); 77 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
83 78
84 switch (nv_device(fifo)->chipset) { 79 switch (device->chipset) {
85 case 0x47: 80 case 0x47:
86 case 0x49: 81 case 0x49:
87 case 0x4b: 82 case 0x4b:
@@ -110,47 +105,23 @@ nv40_fifo_init(struct nvkm_object *object)
110 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 105 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
111 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 106 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
112 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 107 nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
113 return 0;
114} 108}
115 109
116static const struct nvkm_fifo_func 110static const struct nvkm_fifo_func
117nv40_fifo_func = { 111nv40_fifo = {
112 .init = nv40_fifo_init,
113 .intr = nv04_fifo_intr,
114 .pause = nv04_fifo_pause,
115 .start = nv04_fifo_start,
118 .chan = { 116 .chan = {
119 &nv40_fifo_dma_oclass, 117 &nv40_fifo_dma_oclass,
120 NULL 118 NULL
121 }, 119 },
122}; 120};
123 121
124static int 122int
125nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 123nv40_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
126 struct nvkm_oclass *oclass, void *data, u32 size,
127 struct nvkm_object **pobject)
128{ 124{
129 struct nv04_fifo *fifo; 125 return nv04_fifo_new_(&nv40_fifo, device, index, 32,
130 int ret; 126 nv40_fifo_ramfc, pfifo);
131
132 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo);
133 *pobject = nv_object(fifo);
134 if (ret)
135 return ret;
136
137 fifo->base.func = &nv40_fifo_func;
138
139 nv_subdev(fifo)->unit = 0x00000100;
140 nv_subdev(fifo)->intr = nv04_fifo_intr;
141 fifo->base.pause = nv04_fifo_pause;
142 fifo->base.start = nv04_fifo_start;
143 fifo->ramfc_desc = nv40_ramfc;
144 return 0;
145} 127}
146
147struct nvkm_oclass *
148nv40_fifo_oclass = &(struct nvkm_oclass) {
149 .handle = NV_ENGINE(FIFO, 0x40),
150 .ofuncs = &(struct nvkm_ofuncs) {
151 .ctor = nv40_fifo_ctor,
152 .dtor = nv04_fifo_dtor,
153 .init = nv40_fifo_init,
154 .fini = _nvkm_fifo_fini,
155 },
156};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
index ad653e9c461a..66eb12c2b5ba 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
@@ -24,6 +24,8 @@
24#include "nv50.h" 24#include "nv50.h"
25#include "channv50.h" 25#include "channv50.h"
26 26
27#include <core/gpuobj.h>
28
27static void 29static void
28nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo) 30nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo)
29{ 31{
@@ -49,22 +51,34 @@ nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo)
49void 51void
50nv50_fifo_runlist_update(struct nv50_fifo *fifo) 52nv50_fifo_runlist_update(struct nv50_fifo *fifo)
51{ 53{
52 mutex_lock(&nv_subdev(fifo)->mutex); 54 mutex_lock(&fifo->base.engine.subdev.mutex);
53 nv50_fifo_runlist_update_locked(fifo); 55 nv50_fifo_runlist_update_locked(fifo);
54 mutex_unlock(&nv_subdev(fifo)->mutex); 56 mutex_unlock(&fifo->base.engine.subdev.mutex);
55} 57}
56 58
57int 59int
58nv50_fifo_init(struct nvkm_object *object) 60nv50_fifo_oneinit(struct nvkm_fifo *base)
59{ 61{
60 struct nv50_fifo *fifo = (void *)object; 62 struct nv50_fifo *fifo = nv50_fifo(base);
61 struct nvkm_device *device = fifo->base.engine.subdev.device; 63 struct nvkm_device *device = fifo->base.engine.subdev.device;
62 int ret, i; 64 int ret;
63 65
64 ret = nvkm_fifo_init(&fifo->base); 66 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
67 false, &fifo->runlist[0]);
65 if (ret) 68 if (ret)
66 return ret; 69 return ret;
67 70
71 return nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
72 false, &fifo->runlist[1]);
73}
74
75void
76nv50_fifo_init(struct nvkm_fifo *base)
77{
78 struct nv50_fifo *fifo = nv50_fifo(base);
79 struct nvkm_device *device = fifo->base.engine.subdev.device;
80 int i;
81
68 nvkm_mask(device, 0x000200, 0x00000100, 0x00000000); 82 nvkm_mask(device, 0x000200, 0x00000100, 0x00000000);
69 nvkm_mask(device, 0x000200, 0x00000100, 0x00000100); 83 nvkm_mask(device, 0x000200, 0x00000100, 0x00000100);
70 nvkm_wr32(device, 0x00250c, 0x6f3cfc34); 84 nvkm_wr32(device, 0x00250c, 0x6f3cfc34);
@@ -80,69 +94,54 @@ nv50_fifo_init(struct nvkm_object *object)
80 nvkm_wr32(device, 0x003200, 0x00000001); 94 nvkm_wr32(device, 0x003200, 0x00000001);
81 nvkm_wr32(device, 0x003250, 0x00000001); 95 nvkm_wr32(device, 0x003250, 0x00000001);
82 nvkm_wr32(device, 0x002500, 0x00000001); 96 nvkm_wr32(device, 0x002500, 0x00000001);
83 return 0;
84} 97}
85 98
86void 99void *
87nv50_fifo_dtor(struct nvkm_object *object) 100nv50_fifo_dtor(struct nvkm_fifo *base)
88{ 101{
89 struct nv50_fifo *fifo = (void *)object; 102 struct nv50_fifo *fifo = nv50_fifo(base);
90
91 nvkm_memory_del(&fifo->runlist[1]); 103 nvkm_memory_del(&fifo->runlist[1]);
92 nvkm_memory_del(&fifo->runlist[0]); 104 nvkm_memory_del(&fifo->runlist[0]);
93 105 return fifo;
94 nvkm_fifo_destroy(&fifo->base);
95} 106}
96 107
97static const struct nvkm_fifo_func 108int
98nv50_fifo_func = { 109nv50_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
99 .chan = { 110 int index, struct nvkm_fifo **pfifo)
100 &nv50_fifo_dma_oclass,
101 &nv50_fifo_gpfifo_oclass,
102 NULL
103 },
104};
105
106static int
107nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
108 struct nvkm_oclass *oclass, void *data, u32 size,
109 struct nvkm_object **pobject)
110{ 111{
111 struct nvkm_device *device = (void *)parent;
112 struct nv50_fifo *fifo; 112 struct nv50_fifo *fifo;
113 int ret; 113 int ret;
114 114
115 ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo); 115 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
116 *pobject = nv_object(fifo); 116 return -ENOMEM;
117 if (ret) 117 *pfifo = &fifo->base;
118 return ret;
119
120 fifo->base.func = &nv50_fifo_func;
121
122 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
123 false, &fifo->runlist[0]);
124 if (ret)
125 return ret;
126 118
127 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, 119 ret = nvkm_fifo_ctor(func, device, index, 128, &fifo->base);
128 false, &fifo->runlist[1]);
129 if (ret) 120 if (ret)
130 return ret; 121 return ret;
131 122
132 nv_subdev(fifo)->unit = 0x00000100; 123 set_bit(0, fifo->base.mask); /* PIO channel */
133 nv_subdev(fifo)->intr = nv04_fifo_intr; 124 set_bit(127, fifo->base.mask); /* inactive channel */
134 fifo->base.pause = nv04_fifo_pause;
135 fifo->base.start = nv04_fifo_start;
136 return 0; 125 return 0;
137} 126}
138 127
139struct nvkm_oclass * 128static const struct nvkm_fifo_func
140nv50_fifo_oclass = &(struct nvkm_oclass) { 129nv50_fifo = {
141 .handle = NV_ENGINE(FIFO, 0x50), 130 .dtor = nv50_fifo_dtor,
142 .ofuncs = &(struct nvkm_ofuncs) { 131 .oneinit = nv50_fifo_oneinit,
143 .ctor = nv50_fifo_ctor, 132 .init = nv50_fifo_init,
144 .dtor = nv50_fifo_dtor, 133 .intr = nv04_fifo_intr,
145 .init = nv50_fifo_init, 134 .pause = nv04_fifo_pause,
146 .fini = _nvkm_fifo_fini, 135 .start = nv04_fifo_start,
136 .chan = {
137 &nv50_fifo_dma_oclass,
138 &nv50_fifo_gpfifo_oclass,
139 NULL
147 }, 140 },
148}; 141};
142
143int
144nv50_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
145{
146 return nv50_fifo_new_(&nv50_fifo, device, index, pfifo);
147}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
index a7d5dba12fb8..8ab53948cbb4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
@@ -9,7 +9,11 @@ struct nv50_fifo {
9 int cur_runlist; 9 int cur_runlist;
10}; 10};
11 11
12void nv50_fifo_dtor(struct nvkm_object *); 12int nv50_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *,
13int nv50_fifo_init(struct nvkm_object *); 13 int index, struct nvkm_fifo **);
14
15void *nv50_fifo_dtor(struct nvkm_fifo *);
16int nv50_fifo_oneinit(struct nvkm_fifo *);
17void nv50_fifo_init(struct nvkm_fifo *);
14void nv50_fifo_runlist_update(struct nv50_fifo *); 18void nv50_fifo_runlist_update(struct nv50_fifo *);
15#endif 19#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
index a30d160f30db..cb1432e9be08 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
@@ -1,7 +1,26 @@
1#ifndef __NVKM_FIFO_PRIV_H__ 1#ifndef __NVKM_FIFO_PRIV_H__
2#define __NVKM_FIFO_PRIV_H__ 2#define __NVKM_FIFO_PRIV_H__
3#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine)
3#include <engine/fifo.h> 4#include <engine/fifo.h>
4 5
6int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *,
7 int index, int nr, struct nvkm_fifo *);
8void nvkm_fifo_uevent(struct nvkm_fifo *);
9
10struct nvkm_fifo_func {
11 void *(*dtor)(struct nvkm_fifo *);
12 int (*oneinit)(struct nvkm_fifo *);
13 void (*init)(struct nvkm_fifo *);
14 void (*fini)(struct nvkm_fifo *);
15 void (*intr)(struct nvkm_fifo *);
16 void (*pause)(struct nvkm_fifo *, unsigned long *);
17 void (*start)(struct nvkm_fifo *, unsigned long *);
18 void (*uevent_init)(struct nvkm_fifo *);
19 void (*uevent_fini)(struct nvkm_fifo *);
20 const struct nvkm_fifo_chan_oclass *chan[];
21};
22
23void nv04_fifo_intr(struct nvkm_fifo *);
5void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); 24void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
6void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); 25void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
7#endif 26#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
index f06c16f61a98..a5a4bdd9863e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
@@ -25,6 +25,7 @@
25#include "regs.h" 25#include "regs.h"
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/gpuobj.h>
28#include <engine/fifo.h> 29#include <engine/fifo.h>
29#include <engine/fifo/chan.h> 30#include <engine/fifo/chan.h>
30#include <subdev/instmem.h> 31#include <subdev/instmem.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
index 98fb9e6efb97..d5e44a7332eb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
@@ -25,6 +25,7 @@
25#include "regs.h" 25#include "regs.h"
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/gpuobj.h>
28#include <engine/fifo.h> 29#include <engine/fifo.h>
29#include <engine/fifo/chan.h> 30#include <engine/fifo/chan.h>
30#include <subdev/fb.h> 31#include <subdev/fb.h>
@@ -1055,14 +1056,14 @@ nv10_gr_tile_prog(struct nvkm_engine *engine, int i)
1055 struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; 1056 struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
1056 unsigned long flags; 1057 unsigned long flags;
1057 1058
1058 fifo->pause(fifo, &flags); 1059 nvkm_fifo_pause(fifo, &flags);
1059 nv04_gr_idle(&gr->base); 1060 nv04_gr_idle(&gr->base);
1060 1061
1061 nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit); 1062 nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit);
1062 nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch); 1063 nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch);
1063 nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr); 1064 nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr);
1064 1065
1065 fifo->start(fifo, &flags); 1066 nvkm_fifo_start(fifo, &flags);
1066} 1067}
1067 1068
1068const struct nvkm_bitfield nv10_gr_intr_name[] = { 1069const struct nvkm_bitfield nv10_gr_intr_name[] = {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
index 554f2e3f7e5b..ce4f9925ea9b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
@@ -2,6 +2,7 @@
2#include "regs.h" 2#include "regs.h"
3 3
4#include <core/client.h> 4#include <core/client.h>
5#include <core/gpuobj.h>
5#include <engine/fifo.h> 6#include <engine/fifo.h>
6#include <engine/fifo/chan.h> 7#include <engine/fifo/chan.h>
7#include <subdev/fb.h> 8#include <subdev/fb.h>
@@ -152,7 +153,7 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
152 struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; 153 struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
153 unsigned long flags; 154 unsigned long flags;
154 155
155 fifo->pause(fifo, &flags); 156 nvkm_fifo_pause(fifo, &flags);
156 nv04_gr_idle(&gr->base); 157 nv04_gr_idle(&gr->base);
157 158
158 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); 159 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
@@ -172,7 +173,7 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
172 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp); 173 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
173 } 174 }
174 175
175 fifo->start(fifo, &flags); 176 nvkm_fifo_start(fifo, &flags);
176} 177}
177 178
178void 179void
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
index 7fb53d53426c..cc56ca9505f4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
@@ -1,6 +1,7 @@
1#include "nv20.h" 1#include "nv20.h"
2#include "regs.h" 2#include "regs.h"
3 3
4#include <core/gpuobj.h>
4#include <engine/fifo.h> 5#include <engine/fifo.h>
5#include <engine/fifo/chan.h> 6#include <engine/fifo/chan.h>
6 7
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
index 2fabdc586651..4e4cd93d686d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
@@ -1,6 +1,7 @@
1#include "nv20.h" 1#include "nv20.h"
2#include "regs.h" 2#include "regs.h"
3 3
4#include <core/gpuobj.h>
4#include <engine/fifo.h> 5#include <engine/fifo.h>
5#include <engine/fifo/chan.h> 6#include <engine/fifo/chan.h>
6 7
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
index 8f5bfe3aa487..ea46b16c31e6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
@@ -1,6 +1,7 @@
1#include "nv20.h" 1#include "nv20.h"
2#include "regs.h" 2#include "regs.h"
3 3
4#include <core/gpuobj.h>
4#include <engine/fifo.h> 5#include <engine/fifo.h>
5#include <engine/fifo/chan.h> 6#include <engine/fifo/chan.h>
6#include <subdev/fb.h> 7#include <subdev/fb.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
index 3781a5b311fb..0667e9d14b42 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
@@ -1,6 +1,7 @@
1#include "nv20.h" 1#include "nv20.h"
2#include "regs.h" 2#include "regs.h"
3 3
4#include <core/gpuobj.h>
4#include <engine/fifo.h> 5#include <engine/fifo.h>
5#include <engine/fifo/chan.h> 6#include <engine/fifo/chan.h>
6 7
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
index 285c4eff2e5b..745d0e133d9a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
@@ -1,6 +1,7 @@
1#include "nv20.h" 1#include "nv20.h"
2#include "regs.h" 2#include "regs.h"
3 3
4#include <core/gpuobj.h>
4#include <engine/fifo.h> 5#include <engine/fifo.h>
5#include <engine/fifo/chan.h> 6#include <engine/fifo/chan.h>
6 7
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
index 0e4e1152eeec..be954500b4d8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
@@ -25,6 +25,7 @@
25#include "regs.h" 25#include "regs.h"
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/gpuobj.h>
28#include <subdev/fb.h> 29#include <subdev/fb.h>
29#include <subdev/timer.h> 30#include <subdev/timer.h>
30#include <engine/fifo.h> 31#include <engine/fifo.h>
@@ -176,7 +177,7 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i)
176 struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; 177 struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
177 unsigned long flags; 178 unsigned long flags;
178 179
179 fifo->pause(fifo, &flags); 180 nvkm_fifo_pause(fifo, &flags);
180 nv04_gr_idle(&gr->base); 181 nv04_gr_idle(&gr->base);
181 182
182 switch (nv_device(gr)->chipset) { 183 switch (nv_device(gr)->chipset) {
@@ -243,7 +244,7 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i)
243 break; 244 break;
244 } 245 }
245 246
246 fifo->start(fifo, &flags); 247 nvkm_fifo_start(fifo, &flags);
247} 248}
248 249
249static void 250static void
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
index 2a5bc9270fb9..11c4c8838937 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
@@ -24,6 +24,7 @@
24#include "nv50.h" 24#include "nv50.h"
25 25
26#include <core/client.h> 26#include <core/client.h>
27#include <core/gpuobj.h>
27#include <subdev/timer.h> 28#include <subdev/timer.h>
28#include <engine/fifo.h> 29#include <engine/fifo.h>
29 30
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
index 417cc31a12ef..f79749946b72 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
@@ -24,6 +24,7 @@
24#include "nv31.h" 24#include "nv31.h"
25 25
26#include <core/client.h> 26#include <core/client.h>
27#include <core/gpuobj.h>
27#include <subdev/fb.h> 28#include <subdev/fb.h>
28#include <subdev/timer.h> 29#include <subdev/timer.h>
29#include <engine/fifo.h> 30#include <engine/fifo.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
index 0f9ef18bf18d..d1b914b43cee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
@@ -25,6 +25,7 @@
25#include "priv.h" 25#include "priv.h"
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/gpuobj.h>
28#include <engine/fifo.h> 29#include <engine/fifo.h>
29 30
30#include <nvif/class.h> 31#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
index 1ec4f4fde1c2..995c2c5ec150 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
@@ -27,6 +27,7 @@
27 27
28#include <core/client.h> 28#include <core/client.h>
29#include <core/enum.h> 29#include <core/enum.h>
30#include <core/gpuobj.h>
30 31
31#include <nvif/class.h> 32#include <nvif/class.h>
32 33
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
index 4ca6b88e9a7f..5cd7844f1d5f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
@@ -23,6 +23,7 @@
23 */ 23 */
24#include "nv50.h" 24#include "nv50.h"
25 25
26#include <core/gpuobj.h>
26#include <subdev/bar.h> 27#include <subdev/bar.h>
27#include <engine/disp.h> 28#include <engine/disp.h>
28#include <engine/fifo.h> 29#include <engine/fifo.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
index 6c93a20295a4..a00d9a55e53b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
@@ -23,6 +23,7 @@
23 */ 23 */
24#include "nv50.h" 24#include "nv50.h"
25 25
26#include <core/gpuobj.h>
26#include <core/handle.h> 27#include <core/handle.h>
27#include <engine/disp.h> 28#include <engine/disp.h>
28#include <engine/fifo/chan.h> 29#include <engine/fifo/chan.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
index fa36233a71dd..d6a2b9593538 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
@@ -20,6 +20,8 @@
20 * OTHER DEALINGS IN THE SOFTWARE. 20 * OTHER DEALINGS IN THE SOFTWARE.
21 */ 21 */
22#include <engine/xtensa.h> 22#include <engine/xtensa.h>
23
24#include <core/gpuobj.h>
23#include <engine/fifo.h> 25#include <engine/fifo.h>
24 26
25static int 27static int
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
index e5258ba19834..07feae620c8d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
@@ -317,7 +317,7 @@ gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags)
317 return -EBUSY; 317 return -EBUSY;
318 318
319 if (fifo) 319 if (fifo)
320 fifo->pause(fifo, flags); 320 nvkm_fifo_pause(fifo, flags);
321 321
322 if (nvkm_msec(device, 2000, 322 if (nvkm_msec(device, 2000,
323 if (nvkm_rd32(device, 0x002504) & 0x00000010) 323 if (nvkm_rd32(device, 0x002504) & 0x00000010)
@@ -342,7 +342,7 @@ gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags)
342 struct nvkm_fifo *fifo = device->fifo; 342 struct nvkm_fifo *fifo = device->fifo;
343 343
344 if (fifo && flags) 344 if (fifo && flags)
345 fifo->start(fifo, flags); 345 nvkm_fifo_start(fifo, flags);
346 346
347 nvkm_mask(device, 0x002504, 0x00000001, 0x00000000); 347 nvkm_mask(device, 0x002504, 0x00000001, 0x00000000);
348 nvkm_mask(device, 0x020060, 0x00070000, 0x00040000); 348 nvkm_mask(device, 0x020060, 0x00070000, 0x00040000);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 00:13:16 -0400