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authorTuomas Tynkkynen <ttynkkynen@nvidia.com>2015-05-13 10:58:46 -0400
committerThierry Reding <treding@nvidia.com>2015-07-16 03:34:06 -0400
commit135796c9ccd3d6c53fbc3f6c4d73d8ba6820b739 (patch)
tree93bdb890e585e9a6c1798e8902a35b9afeb27025
parentd770e558e21961ad6cfdf0ff7df0eb5d7d4f0754 (diff)
cpufreq: tegra124: Add device tree bindings
The cpufreq driver for Tegra124 will be a different one than the old Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device tree. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt44
1 files changed, 44 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt
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1Tegra124 CPU frequency scaling driver bindings
2----------------------------------------------
3
4Both required and optional properties listed below must be defined
5under node /cpus/cpu@0.
6
7Required properties:
8- clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10- clock-names: Must include the following entries:
11 - cpu_g: Clock mux for the fast CPU cluster.
12 - cpu_lp: Clock mux for the low-power CPU cluster.
13 - pll_x: Fast PLL clocksource.
14 - pll_p: Auxiliary PLL used during fast PLL rate changes.
15 - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
16- vdd-cpu-supply: Regulator for CPU voltage
17
18Optional properties:
19- clock-latency: Specify the possible maximum transition latency for clock,
20 in unit of nanoseconds.
21
22Example:
23--------
24cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a15";
31 reg = <0>;
32
33 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
34 <&tegra_car TEGRA124_CLK_CCLK_LP>,
35 <&tegra_car TEGRA124_CLK_PLL_X>,
36 <&tegra_car TEGRA124_CLK_PLL_P>,
37 <&dfll>;
38 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
39 clock-latency = <300000>;
40 vdd-cpu-supply: <&vdd_cpu>;
41 };
42
43 <...>
44};