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authorVille Syrjälä <ville.syrjala@linux.intel.com>2016-10-31 16:37:13 -0400
committerVille Syrjälä <ville.syrjala@linux.intel.com>2016-11-01 10:40:38 -0400
commit1353c4fb1803cc094bb0194bb317b090ab08d83c (patch)
tree95e719d6b123e00b282782eea808a5b5035b7d0f
parent4c75b9405ea34c9223890d6470b809126b45c173 (diff)
drm/i915: Pass dev_priv to .get_display_clock_speed()
Unify our approach to things by passing around dev_priv instead of dev. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1477946245-14134-15-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c77
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c2
3 files changed, 38 insertions, 43 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eeed752da9df..60c937dce06f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -494,7 +494,7 @@ struct intel_limit;
494struct dpll; 494struct dpll;
495 495
496struct drm_i915_display_funcs { 496struct drm_i915_display_funcs {
497 int (*get_display_clock_speed)(struct drm_device *dev); 497 int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
498 int (*get_fifo_size)(struct drm_device *dev, int plane); 498 int (*get_fifo_size)(struct drm_device *dev, int plane);
499 int (*compute_pipe_wm)(struct intel_crtc_state *cstate); 499 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
500 int (*compute_intermediate_wm)(struct drm_device *dev, 500 int (*compute_intermediate_wm)(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3c26ea01b7a2..b670ae76317b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5903,7 +5903,7 @@ static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5903 5903
5904static void intel_update_cdclk(struct drm_i915_private *dev_priv) 5904static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5905{ 5905{
5906 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(&dev_priv->drm); 5906 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5907 5907
5908 if (INTEL_GEN(dev_priv) >= 9) 5908 if (INTEL_GEN(dev_priv) >= 9)
5909 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", 5909 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
@@ -6421,7 +6421,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6421 struct drm_i915_private *dev_priv = to_i915(dev); 6421 struct drm_i915_private *dev_priv = to_i915(dev);
6422 u32 val, cmd; 6422 u32 val, cmd;
6423 6423
6424 WARN_ON(dev_priv->display.get_display_clock_speed(dev) 6424 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6425 != dev_priv->cdclk_freq); 6425 != dev_priv->cdclk_freq);
6426 6426
6427 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 6427 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
@@ -6486,7 +6486,7 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6486 struct drm_i915_private *dev_priv = to_i915(dev); 6486 struct drm_i915_private *dev_priv = to_i915(dev);
6487 u32 val, cmd; 6487 u32 val, cmd;
6488 6488
6489 WARN_ON(dev_priv->display.get_display_clock_speed(dev) 6489 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6490 != dev_priv->cdclk_freq); 6490 != dev_priv->cdclk_freq);
6491 6491
6492 switch (cdclk) { 6492 switch (cdclk) {
@@ -7245,10 +7245,9 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
7245 return 0; 7245 return 0;
7246} 7246}
7247 7247
7248static int skylake_get_display_clock_speed(struct drm_device *dev) 7248static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7249{ 7249{
7250 struct drm_i915_private *dev_priv = to_i915(dev); 7250 u32 cdctl;
7251 uint32_t cdctl;
7252 7251
7253 skl_dpll0_update(dev_priv); 7252 skl_dpll0_update(dev_priv);
7254 7253
@@ -7307,9 +7306,8 @@ static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7307 dev_priv->cdclk_pll.ref; 7306 dev_priv->cdclk_pll.ref;
7308} 7307}
7309 7308
7310static int broxton_get_display_clock_speed(struct drm_device *dev) 7309static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7311{ 7310{
7312 struct drm_i915_private *dev_priv = to_i915(dev);
7313 u32 divider; 7311 u32 divider;
7314 int div, vco; 7312 int div, vco;
7315 7313
@@ -7342,9 +7340,8 @@ static int broxton_get_display_clock_speed(struct drm_device *dev)
7342 return DIV_ROUND_CLOSEST(vco, div); 7340 return DIV_ROUND_CLOSEST(vco, div);
7343} 7341}
7344 7342
7345static int broadwell_get_display_clock_speed(struct drm_device *dev) 7343static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7346{ 7344{
7347 struct drm_i915_private *dev_priv = to_i915(dev);
7348 uint32_t lcpll = I915_READ(LCPLL_CTL); 7345 uint32_t lcpll = I915_READ(LCPLL_CTL);
7349 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 7346 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7350 7347
@@ -7362,9 +7359,8 @@ static int broadwell_get_display_clock_speed(struct drm_device *dev)
7362 return 675000; 7359 return 675000;
7363} 7360}
7364 7361
7365static int haswell_get_display_clock_speed(struct drm_device *dev) 7362static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7366{ 7363{
7367 struct drm_i915_private *dev_priv = to_i915(dev);
7368 uint32_t lcpll = I915_READ(LCPLL_CTL); 7364 uint32_t lcpll = I915_READ(LCPLL_CTL);
7369 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 7365 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7370 7366
@@ -7380,35 +7376,35 @@ static int haswell_get_display_clock_speed(struct drm_device *dev)
7380 return 540000; 7376 return 540000;
7381} 7377}
7382 7378
7383static int valleyview_get_display_clock_speed(struct drm_device *dev) 7379static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7384{ 7380{
7385 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", 7381 return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7386 CCK_DISPLAY_CLOCK_CONTROL); 7382 CCK_DISPLAY_CLOCK_CONTROL);
7387} 7383}
7388 7384
7389static int ilk_get_display_clock_speed(struct drm_device *dev) 7385static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7390{ 7386{
7391 return 450000; 7387 return 450000;
7392} 7388}
7393 7389
7394static int i945_get_display_clock_speed(struct drm_device *dev) 7390static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7395{ 7391{
7396 return 400000; 7392 return 400000;
7397} 7393}
7398 7394
7399static int i915_get_display_clock_speed(struct drm_device *dev) 7395static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7400{ 7396{
7401 return 333333; 7397 return 333333;
7402} 7398}
7403 7399
7404static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) 7400static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7405{ 7401{
7406 return 200000; 7402 return 200000;
7407} 7403}
7408 7404
7409static int pnv_get_display_clock_speed(struct drm_device *dev) 7405static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7410{ 7406{
7411 struct pci_dev *pdev = dev->pdev; 7407 struct pci_dev *pdev = dev_priv->drm.pdev;
7412 u16 gcfgc = 0; 7408 u16 gcfgc = 0;
7413 7409
7414 pci_read_config_word(pdev, GCFGC, &gcfgc); 7410 pci_read_config_word(pdev, GCFGC, &gcfgc);
@@ -7431,9 +7427,9 @@ static int pnv_get_display_clock_speed(struct drm_device *dev)
7431 } 7427 }
7432} 7428}
7433 7429
7434static int i915gm_get_display_clock_speed(struct drm_device *dev) 7430static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7435{ 7431{
7436 struct pci_dev *pdev = dev->pdev; 7432 struct pci_dev *pdev = dev_priv->drm.pdev;
7437 u16 gcfgc = 0; 7433 u16 gcfgc = 0;
7438 7434
7439 pci_read_config_word(pdev, GCFGC, &gcfgc); 7435 pci_read_config_word(pdev, GCFGC, &gcfgc);
@@ -7451,14 +7447,14 @@ static int i915gm_get_display_clock_speed(struct drm_device *dev)
7451 } 7447 }
7452} 7448}
7453 7449
7454static int i865_get_display_clock_speed(struct drm_device *dev) 7450static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7455{ 7451{
7456 return 266667; 7452 return 266667;
7457} 7453}
7458 7454
7459static int i85x_get_display_clock_speed(struct drm_device *dev) 7455static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7460{ 7456{
7461 struct pci_dev *pdev = dev->pdev; 7457 struct pci_dev *pdev = dev_priv->drm.pdev;
7462 u16 hpllcc = 0; 7458 u16 hpllcc = 0;
7463 7459
7464 /* 7460 /*
@@ -7494,14 +7490,13 @@ static int i85x_get_display_clock_speed(struct drm_device *dev)
7494 return 0; 7490 return 0;
7495} 7491}
7496 7492
7497static int i830_get_display_clock_speed(struct drm_device *dev) 7493static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7498{ 7494{
7499 return 133333; 7495 return 133333;
7500} 7496}
7501 7497
7502static unsigned int intel_hpll_vco(struct drm_device *dev) 7498static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7503{ 7499{
7504 struct drm_i915_private *dev_priv = to_i915(dev);
7505 static const unsigned int blb_vco[8] = { 7500 static const unsigned int blb_vco[8] = {
7506 [0] = 3200000, 7501 [0] = 3200000,
7507 [1] = 4000000, 7502 [1] = 4000000,
@@ -7548,16 +7543,16 @@ static unsigned int intel_hpll_vco(struct drm_device *dev)
7548 vco_table = ctg_vco; 7543 vco_table = ctg_vco;
7549 else if (IS_G4X(dev_priv)) 7544 else if (IS_G4X(dev_priv))
7550 vco_table = elk_vco; 7545 vco_table = elk_vco;
7551 else if (IS_CRESTLINE(dev)) 7546 else if (IS_CRESTLINE(dev_priv))
7552 vco_table = cl_vco; 7547 vco_table = cl_vco;
7553 else if (IS_PINEVIEW(dev)) 7548 else if (IS_PINEVIEW(dev_priv))
7554 vco_table = pnv_vco; 7549 vco_table = pnv_vco;
7555 else if (IS_G33(dev)) 7550 else if (IS_G33(dev_priv))
7556 vco_table = blb_vco; 7551 vco_table = blb_vco;
7557 else 7552 else
7558 return 0; 7553 return 0;
7559 7554
7560 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); 7555 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7561 7556
7562 vco = vco_table[tmp & 0x7]; 7557 vco = vco_table[tmp & 0x7];
7563 if (vco == 0) 7558 if (vco == 0)
@@ -7568,10 +7563,10 @@ static unsigned int intel_hpll_vco(struct drm_device *dev)
7568 return vco; 7563 return vco;
7569} 7564}
7570 7565
7571static int gm45_get_display_clock_speed(struct drm_device *dev) 7566static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7572{ 7567{
7573 struct pci_dev *pdev = dev->pdev; 7568 struct pci_dev *pdev = dev_priv->drm.pdev;
7574 unsigned int cdclk_sel, vco = intel_hpll_vco(dev); 7569 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7575 uint16_t tmp = 0; 7570 uint16_t tmp = 0;
7576 7571
7577 pci_read_config_word(pdev, GCFGC, &tmp); 7572 pci_read_config_word(pdev, GCFGC, &tmp);
@@ -7591,14 +7586,14 @@ static int gm45_get_display_clock_speed(struct drm_device *dev)
7591 } 7586 }
7592} 7587}
7593 7588
7594static int i965gm_get_display_clock_speed(struct drm_device *dev) 7589static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7595{ 7590{
7596 struct pci_dev *pdev = dev->pdev; 7591 struct pci_dev *pdev = dev_priv->drm.pdev;
7597 static const uint8_t div_3200[] = { 16, 10, 8 }; 7592 static const uint8_t div_3200[] = { 16, 10, 8 };
7598 static const uint8_t div_4000[] = { 20, 12, 10 }; 7593 static const uint8_t div_4000[] = { 20, 12, 10 };
7599 static const uint8_t div_5333[] = { 24, 16, 14 }; 7594 static const uint8_t div_5333[] = { 24, 16, 14 };
7600 const uint8_t *div_table; 7595 const uint8_t *div_table;
7601 unsigned int cdclk_sel, vco = intel_hpll_vco(dev); 7596 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7602 uint16_t tmp = 0; 7597 uint16_t tmp = 0;
7603 7598
7604 pci_read_config_word(pdev, GCFGC, &tmp); 7599 pci_read_config_word(pdev, GCFGC, &tmp);
@@ -7629,15 +7624,15 @@ fail:
7629 return 200000; 7624 return 200000;
7630} 7625}
7631 7626
7632static int g33_get_display_clock_speed(struct drm_device *dev) 7627static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7633{ 7628{
7634 struct pci_dev *pdev = dev->pdev; 7629 struct pci_dev *pdev = dev_priv->drm.pdev;
7635 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; 7630 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7636 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; 7631 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7637 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; 7632 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7638 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; 7633 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7639 const uint8_t *div_table; 7634 const uint8_t *div_table;
7640 unsigned int cdclk_sel, vco = intel_hpll_vco(dev); 7635 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7641 uint16_t tmp = 0; 7636 uint16_t tmp = 0;
7642 7637
7643 pci_read_config_word(pdev, GCFGC, &tmp); 7638 pci_read_config_word(pdev, GCFGC, &tmp);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9a3a7455d29c..05994083e161 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -907,7 +907,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
907 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 907 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
908 908
909 WARN_ON(dev_priv->cdclk_freq != 909 WARN_ON(dev_priv->cdclk_freq !=
910 dev_priv->display.get_display_clock_speed(&dev_priv->drm)); 910 dev_priv->display.get_display_clock_speed(dev_priv));
911 911
912 gen9_assert_dbuf_enabled(dev_priv); 912 gen9_assert_dbuf_enabled(dev_priv);
913 913