diff options
author | Stefan Brüns <stefan.bruens@rwth-aachen.de> | 2017-09-27 21:49:25 -0400 |
---|---|---|
committer | Vinod Koul <vinod.koul@intel.com> | 2017-10-16 03:01:36 -0400 |
commit | 12e0177055ee4b5ab656414b32054e64568160d8 (patch) | |
tree | add909df6c4dcbced8de8ba63ab86deebc987749 | |
parent | d93cc0e7888a7c650a9155ad70e2236d15785c1e (diff) |
dmaengine: sun6i: Add support for Allwinner A64 and compatibles
The A64 SoC has the same dma engine as the H3 (sun8i), with a
reduced amount of physical channels. To allow future reuse of the
compatible, leave the channel count etc. in the config data blank
and retrieve it from the devicetree.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r-- | drivers/dma/sun6i-dma.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index f27b126dd6cd..0cabb48b0fb5 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c | |||
@@ -1122,6 +1122,25 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { | |||
1122 | }; | 1122 | }; |
1123 | 1123 | ||
1124 | /* | 1124 | /* |
1125 | * The A64 binding uses the number of dma channels from the | ||
1126 | * device tree node. | ||
1127 | */ | ||
1128 | static struct sun6i_dma_config sun50i_a64_dma_cfg = { | ||
1129 | .clock_autogate_enable = sun6i_enable_clock_autogate_h3, | ||
1130 | .set_burst_length = sun6i_set_burst_length_h3, | ||
1131 | .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), | ||
1132 | .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), | ||
1133 | .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | | ||
1134 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | | ||
1135 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | | ||
1136 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), | ||
1137 | .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | | ||
1138 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | | ||
1139 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | | ||
1140 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), | ||
1141 | }; | ||
1142 | |||
1143 | /* | ||
1125 | * The V3s have only 8 physical channels, a maximum DRQ port id of 23, | 1144 | * The V3s have only 8 physical channels, a maximum DRQ port id of 23, |
1126 | * and a total of 24 usable source and destination endpoints. | 1145 | * and a total of 24 usable source and destination endpoints. |
1127 | */ | 1146 | */ |
@@ -1148,6 +1167,7 @@ static const struct of_device_id sun6i_dma_match[] = { | |||
1148 | { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg }, | 1167 | { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg }, |
1149 | { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, | 1168 | { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, |
1150 | { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg }, | 1169 | { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg }, |
1170 | { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, | ||
1151 | { /* sentinel */ } | 1171 | { /* sentinel */ } |
1152 | }; | 1172 | }; |
1153 | MODULE_DEVICE_TABLE(of, sun6i_dma_match); | 1173 | MODULE_DEVICE_TABLE(of, sun6i_dma_match); |