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authorRussell King <rmk+kernel@armlinux.org.uk>2017-07-08 05:22:35 -0400
committerRussell King <rmk+kernel@armlinux.org.uk>2017-12-08 07:21:59 -0500
commit11df53dc5bd832dcc4472bdd5e98ac0d9709e739 (patch)
tree897ad678c7ab6c7eaa9200d8de5716f121a863a6
parent07da3c787a273b6d8478b416a694a740c85bdf72 (diff)
drm/armada: extract register generation from armada_drm_primary_set()
Extract the register generation from armada_drm_primary_set(), so that it can be re-used. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-rw-r--r--drivers/gpu/drm/armada/armada_crtc.c25
1 files changed, 16 insertions, 9 deletions
diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index c38a1409a14e..9958f2d3d0e8 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -571,18 +571,14 @@ static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
571 return val; 571 return val;
572} 572}
573 573
574static void armada_drm_primary_set(struct drm_crtc *crtc, 574static void armada_drm_gra_plane_regs(struct armada_regs *regs,
575 struct drm_plane *plane, int x, int y) 575 struct drm_framebuffer *fb, struct armada_plane_state *state,
576 int x, int y, bool interlaced)
576{ 577{
577 struct armada_plane_state *state = &drm_to_armada_plane(plane)->state; 578 unsigned int i;
578 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
579 struct armada_regs regs[8];
580 bool interlaced = dcrtc->interlaced;
581 unsigned i;
582 u32 ctrl0; 579 u32 ctrl0;
583 580
584 i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced); 581 i = armada_drm_crtc_calc_fb(fb, x, y, regs, interlaced);
585
586 armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN); 582 armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
587 armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN); 583 armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
588 armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN); 584 armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
@@ -598,6 +594,17 @@ static void armada_drm_primary_set(struct drm_crtc *crtc,
598 CFG_GRA_HSMOOTH | CFG_GRA_ENA, 594 CFG_GRA_HSMOOTH | CFG_GRA_ENA,
599 LCD_SPU_DMA_CTRL0); 595 LCD_SPU_DMA_CTRL0);
600 armada_reg_queue_end(regs, i); 596 armada_reg_queue_end(regs, i);
597}
598
599static void armada_drm_primary_set(struct drm_crtc *crtc,
600 struct drm_plane *plane, int x, int y)
601{
602 struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
603 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
604 struct armada_regs regs[8];
605 bool interlaced = dcrtc->interlaced;
606
607 armada_drm_gra_plane_regs(regs, plane->fb, state, x, y, interlaced);
601 armada_drm_crtc_update_regs(dcrtc, regs); 608 armada_drm_crtc_update_regs(dcrtc, regs);
602} 609}
603 610