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authorArnd Bergmann <arnd@arndb.de>2017-10-30 09:17:29 -0400
committerArnd Bergmann <arnd@arndb.de>2017-10-30 09:17:29 -0400
commit11c3889c237b8ff4ff62420d9a964b10e15f330d (patch)
tree4a1dbf9ee92e4f03b9ed6fdb5a8582ef35f1f893
parentadd5c42e99b2d88542e4a194ba586930756c94ff (diff)
parent76c48e1ecaf34eccaf1bddc462159e82be3d609a (diff)
Merge tag 'uniphier-dt64-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt
Pull "UniPhier ARM64 SoC DT updates for v4.15" from Masahiro Yamada: - add thermal monitor and thermal zone nodes - add efuse nodes - fix W=2 warnings - add GPIO controller nodes and related properties - add resets properties * tag 'uniphier-dt64-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: add resets properties arm64: dts: uniphier: add eMMC hardware reset provider node arm64: dts: uniphier: add GPIO hog definition arm64: dts: uniphier: route on-board device IRQ to GPIO controller arm64: dts: uniphier: add GPIO controller nodes arm64: dts: uniphier: fix W=2 build warnings arm64: dts: uniphier: enable NAND for PXs3 reference board arm64: dts: uniphier: add efuse node for LD11, LD20, and PXs3 arm64: dts: uniphier: add nodes of thermal monitor and thermal zone for LD20
Diffstat
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts11
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi65
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts11
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi105
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts4
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi58
6 files changed, 248 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
index ffb473ad2e0f..dd7193acc7df 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
@@ -40,13 +40,22 @@
40}; 40};
41 41
42&ethsc { 42&ethsc {
43 interrupts = <0 48 4>; 43 interrupt-parent = <&gpio>;
44 interrupts = <0 8>;
44}; 45};
45 46
46&serial0 { 47&serial0 {
47 status = "okay"; 48 status = "okay";
48}; 49};
49 50
51&gpio {
52 xirq0 {
53 gpio-hog;
54 gpios = <120 0>;
55 input;
56 };
57};
58
50&i2c0 { 59&i2c0 {
51 status = "okay"; 60 status = "okay";
52}; 61};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index ee4aff53a5f5..2120b0f1febb 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -7,6 +7,8 @@
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */ 8 */
9 9
10#include <dt-bindings/gpio/gpio.h>
11
10/memreserve/ 0x80000000 0x02000000; 12/memreserve/ 0x80000000 0x02000000;
11 13
12/ { 14/ {
@@ -49,7 +51,7 @@
49 }; 51 };
50 }; 52 };
51 53
52 cluster0_opp: opp_table { 54 cluster0_opp: opp-table {
53 compatible = "operating-points-v2"; 55 compatible = "operating-points-v2";
54 opp-shared; 56 opp-shared;
55 57
@@ -96,6 +98,11 @@
96 }; 98 };
97 }; 99 };
98 100
101 emmc_pwrseq: emmc-pwrseq {
102 compatible = "mmc-pwrseq-emmc";
103 reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
104 };
105
99 timer { 106 timer {
100 compatible = "arm,armv8-timer"; 107 compatible = "arm,armv8-timer";
101 interrupts = <1 13 4>, 108 interrupts = <1 13 4>,
@@ -118,6 +125,7 @@
118 pinctrl-names = "default"; 125 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_uart0>; 126 pinctrl-0 = <&pinctrl_uart0>;
120 clocks = <&peri_clk 0>; 127 clocks = <&peri_clk 0>;
128 resets = <&peri_rst 0>;
121 }; 129 };
122 130
123 serial1: serial@54006900 { 131 serial1: serial@54006900 {
@@ -128,6 +136,7 @@
128 pinctrl-names = "default"; 136 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_uart1>; 137 pinctrl-0 = <&pinctrl_uart1>;
130 clocks = <&peri_clk 1>; 138 clocks = <&peri_clk 1>;
139 resets = <&peri_rst 1>;
131 }; 140 };
132 141
133 serial2: serial@54006a00 { 142 serial2: serial@54006a00 {
@@ -138,6 +147,7 @@
138 pinctrl-names = "default"; 147 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_uart2>; 148 pinctrl-0 = <&pinctrl_uart2>;
140 clocks = <&peri_clk 2>; 149 clocks = <&peri_clk 2>;
150 resets = <&peri_rst 2>;
141 }; 151 };
142 152
143 serial3: serial@54006b00 { 153 serial3: serial@54006b00 {
@@ -148,6 +158,32 @@
148 pinctrl-names = "default"; 158 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_uart3>; 159 pinctrl-0 = <&pinctrl_uart3>;
150 clocks = <&peri_clk 3>; 160 clocks = <&peri_clk 3>;
161 resets = <&peri_rst 3>;
162 };
163
164 gpio: gpio@55000000 {
165 compatible = "socionext,uniphier-gpio";
166 reg = <0x55000000 0x200>;
167 interrupt-parent = <&aidet>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 gpio-controller;
171 #gpio-cells = <2>;
172 gpio-ranges = <&pinctrl 0 0 0>,
173 <&pinctrl 43 0 0>,
174 <&pinctrl 51 0 0>,
175 <&pinctrl 96 0 0>,
176 <&pinctrl 160 0 0>,
177 <&pinctrl 184 0 0>;
178 gpio-ranges-group-names = "gpio_range0",
179 "gpio_range1",
180 "gpio_range2",
181 "gpio_range3",
182 "gpio_range4",
183 "gpio_range5";
184 ngpios = <200>;
185 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
186 <21 217 3>;
151 }; 187 };
152 188
153 adamv@57920000 { 189 adamv@57920000 {
@@ -171,6 +207,7 @@
171 pinctrl-names = "default"; 207 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_i2c0>; 208 pinctrl-0 = <&pinctrl_i2c0>;
173 clocks = <&peri_clk 4>; 209 clocks = <&peri_clk 4>;
210 resets = <&peri_rst 4>;
174 clock-frequency = <100000>; 211 clock-frequency = <100000>;
175 }; 212 };
176 213
@@ -184,6 +221,7 @@
184 pinctrl-names = "default"; 221 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_i2c1>; 222 pinctrl-0 = <&pinctrl_i2c1>;
186 clocks = <&peri_clk 5>; 223 clocks = <&peri_clk 5>;
224 resets = <&peri_rst 5>;
187 clock-frequency = <100000>; 225 clock-frequency = <100000>;
188 }; 226 };
189 227
@@ -194,6 +232,7 @@
194 #size-cells = <0>; 232 #size-cells = <0>;
195 interrupts = <0 43 4>; 233 interrupts = <0 43 4>;
196 clocks = <&peri_clk 6>; 234 clocks = <&peri_clk 6>;
235 resets = <&peri_rst 6>;
197 clock-frequency = <400000>; 236 clock-frequency = <400000>;
198 }; 237 };
199 238
@@ -207,6 +246,7 @@
207 pinctrl-names = "default"; 246 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_i2c3>; 247 pinctrl-0 = <&pinctrl_i2c3>;
209 clocks = <&peri_clk 7>; 248 clocks = <&peri_clk 7>;
249 resets = <&peri_rst 7>;
210 clock-frequency = <100000>; 250 clock-frequency = <100000>;
211 }; 251 };
212 252
@@ -220,6 +260,7 @@
220 pinctrl-names = "default"; 260 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_i2c4>; 261 pinctrl-0 = <&pinctrl_i2c4>;
222 clocks = <&peri_clk 8>; 262 clocks = <&peri_clk 8>;
263 resets = <&peri_rst 8>;
223 clock-frequency = <100000>; 264 clock-frequency = <100000>;
224 }; 265 };
225 266
@@ -230,6 +271,7 @@
230 #size-cells = <0>; 271 #size-cells = <0>;
231 interrupts = <0 25 4>; 272 interrupts = <0 25 4>;
232 clocks = <&peri_clk 9>; 273 clocks = <&peri_clk 9>;
274 resets = <&peri_rst 9>;
233 clock-frequency = <400000>; 275 clock-frequency = <400000>;
234 }; 276 };
235 277
@@ -282,9 +324,11 @@
282 pinctrl-names = "default"; 324 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_emmc>; 325 pinctrl-0 = <&pinctrl_emmc>;
284 clocks = <&sys_clk 4>; 326 clocks = <&sys_clk 4>;
327 resets = <&sys_rst 4>;
285 bus-width = <8>; 328 bus-width = <8>;
286 mmc-ddr-1_8v; 329 mmc-ddr-1_8v;
287 mmc-hs200-1_8v; 330 mmc-hs200-1_8v;
331 mmc-pwrseq = <&emmc_pwrseq>;
288 cdns,phy-input-delay-legacy = <4>; 332 cdns,phy-input-delay-legacy = <4>;
289 cdns,phy-input-delay-mmc-highspeed = <2>; 333 cdns,phy-input-delay-mmc-highspeed = <2>;
290 cdns,phy-input-delay-mmc-ddr = <3>; 334 cdns,phy-input-delay-mmc-ddr = <3>;
@@ -355,6 +399,24 @@
355 }; 399 };
356 }; 400 };
357 401
402 soc-glue@5f900000 {
403 compatible = "socionext,uniphier-ld11-soc-glue-debug",
404 "simple-mfd";
405 #address-cells = <1>;
406 #size-cells = <1>;
407 ranges = <0 0x5f900000 0x2000>;
408
409 efuse@100 {
410 compatible = "socionext,uniphier-efuse";
411 reg = <0x100 0x28>;
412 };
413
414 efuse@200 {
415 compatible = "socionext,uniphier-efuse";
416 reg = <0x200 0x68>;
417 };
418 };
419
358 aidet: aidet@5fc20000 { 420 aidet: aidet@5fc20000 {
359 compatible = "socionext,uniphier-ld11-aidet"; 421 compatible = "socionext,uniphier-ld11-aidet";
360 reg = <0x5fc20000 0x200>; 422 reg = <0x5fc20000 0x200>;
@@ -400,6 +462,7 @@
400 pinctrl-names = "default"; 462 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_nand>; 463 pinctrl-0 = <&pinctrl_nand>;
402 clocks = <&sys_clk 2>; 464 clocks = <&sys_clk 2>;
465 resets = <&sys_rst 2>;
403 }; 466 };
404 }; 467 };
405}; 468};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
index 1ca0c8620dc5..d99e3731358c 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
@@ -40,13 +40,22 @@
40}; 40};
41 41
42&ethsc { 42&ethsc {
43 interrupts = <0 48 4>; 43 interrupt-parent = <&gpio>;
44 interrupts = <0 8>;
44}; 45};
45 46
46&serial0 { 47&serial0 {
47 status = "okay"; 48 status = "okay";
48}; 49};
49 50
51&gpio {
52 xirq0 {
53 gpio-hog;
54 gpios = <120 0>;
55 input;
56 };
57};
58
50&i2c0 { 59&i2c0 {
51 status = "okay"; 60 status = "okay";
52}; 61};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index a29c279b6e8e..5c81070944cc 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -7,6 +7,9 @@
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */ 8 */
9 9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/thermal/thermal.h>
12
10/memreserve/ 0x80000000 0x02000000; 13/memreserve/ 0x80000000 0x02000000;
11 14
12/ { 15/ {
@@ -46,6 +49,7 @@
46 clocks = <&sys_clk 32>; 49 clocks = <&sys_clk 32>;
47 enable-method = "psci"; 50 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>; 51 operating-points-v2 = <&cluster0_opp>;
52 #cooling-cells = <2>;
49 }; 53 };
50 54
51 cpu1: cpu@1 { 55 cpu1: cpu@1 {
@@ -64,6 +68,7 @@
64 clocks = <&sys_clk 33>; 68 clocks = <&sys_clk 33>;
65 enable-method = "psci"; 69 enable-method = "psci";
66 operating-points-v2 = <&cluster1_opp>; 70 operating-points-v2 = <&cluster1_opp>;
71 #cooling-cells = <2>;
67 }; 72 };
68 73
69 cpu3: cpu@101 { 74 cpu3: cpu@101 {
@@ -76,7 +81,7 @@
76 }; 81 };
77 }; 82 };
78 83
79 cluster0_opp: opp_table0 { 84 cluster0_opp: opp-table0 {
80 compatible = "operating-points-v2"; 85 compatible = "operating-points-v2";
81 opp-shared; 86 opp-shared;
82 87
@@ -114,7 +119,7 @@
114 }; 119 };
115 }; 120 };
116 121
117 cluster1_opp: opp_table1 { 122 cluster1_opp: opp-table1 {
118 compatible = "operating-points-v2"; 123 compatible = "operating-points-v2";
119 opp-shared; 124 opp-shared;
120 125
@@ -165,6 +170,11 @@
165 }; 170 };
166 }; 171 };
167 172
173 emmc_pwrseq: emmc-pwrseq {
174 compatible = "mmc-pwrseq-emmc";
175 reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
176 };
177
168 timer { 178 timer {
169 compatible = "arm,armv8-timer"; 179 compatible = "arm,armv8-timer";
170 interrupts = <1 13 4>, 180 interrupts = <1 13 4>,
@@ -173,6 +183,40 @@
173 <1 10 4>; 183 <1 10 4>;
174 }; 184 };
175 185
186 thermal-zones {
187 cpu-thermal {
188 polling-delay-passive = <250>; /* 250ms */
189 polling-delay = <1000>; /* 1000ms */
190 thermal-sensors = <&pvtctl>;
191
192 trips {
193 cpu_crit: cpu-crit {
194 temperature = <110000>; /* 110C */
195 hysteresis = <2000>;
196 type = "critical";
197 };
198 cpu_alert: cpu-alert {
199 temperature = <100000>; /* 100C */
200 hysteresis = <2000>;
201 type = "passive";
202 };
203 };
204
205 cooling-maps {
206 map0 {
207 trip = <&cpu_alert>;
208 cooling-device = <&cpu0
209 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 };
211 map1 {
212 trip = <&cpu_alert>;
213 cooling-device = <&cpu2
214 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
215 };
216 };
217 };
218 };
219
176 soc@0 { 220 soc@0 {
177 compatible = "simple-bus"; 221 compatible = "simple-bus";
178 #address-cells = <1>; 222 #address-cells = <1>;
@@ -187,6 +231,7 @@
187 pinctrl-names = "default"; 231 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_uart0>; 232 pinctrl-0 = <&pinctrl_uart0>;
189 clocks = <&peri_clk 0>; 233 clocks = <&peri_clk 0>;
234 resets = <&peri_rst 0>;
190 }; 235 };
191 236
192 serial1: serial@54006900 { 237 serial1: serial@54006900 {
@@ -197,6 +242,7 @@
197 pinctrl-names = "default"; 242 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart1>; 243 pinctrl-0 = <&pinctrl_uart1>;
199 clocks = <&peri_clk 1>; 244 clocks = <&peri_clk 1>;
245 resets = <&peri_rst 1>;
200 }; 246 };
201 247
202 serial2: serial@54006a00 { 248 serial2: serial@54006a00 {
@@ -207,6 +253,7 @@
207 pinctrl-names = "default"; 253 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart2>; 254 pinctrl-0 = <&pinctrl_uart2>;
209 clocks = <&peri_clk 2>; 255 clocks = <&peri_clk 2>;
256 resets = <&peri_rst 2>;
210 }; 257 };
211 258
212 serial3: serial@54006b00 { 259 serial3: serial@54006b00 {
@@ -217,6 +264,26 @@
217 pinctrl-names = "default"; 264 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_uart3>; 265 pinctrl-0 = <&pinctrl_uart3>;
219 clocks = <&peri_clk 3>; 266 clocks = <&peri_clk 3>;
267 resets = <&peri_rst 3>;
268 };
269
270 gpio: gpio@55000000 {
271 compatible = "socionext,uniphier-gpio";
272 reg = <0x55000000 0x200>;
273 interrupt-parent = <&aidet>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 gpio-controller;
277 #gpio-cells = <2>;
278 gpio-ranges = <&pinctrl 0 0 0>,
279 <&pinctrl 96 0 0>,
280 <&pinctrl 160 0 0>;
281 gpio-ranges-group-names = "gpio_range0",
282 "gpio_range1",
283 "gpio_range2";
284 ngpios = <205>;
285 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
286 <21 217 3>;
220 }; 287 };
221 288
222 adamv@57920000 { 289 adamv@57920000 {
@@ -240,6 +307,7 @@
240 pinctrl-names = "default"; 307 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_i2c0>; 308 pinctrl-0 = <&pinctrl_i2c0>;
242 clocks = <&peri_clk 4>; 309 clocks = <&peri_clk 4>;
310 resets = <&peri_rst 4>;
243 clock-frequency = <100000>; 311 clock-frequency = <100000>;
244 }; 312 };
245 313
@@ -253,6 +321,7 @@
253 pinctrl-names = "default"; 321 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_i2c1>; 322 pinctrl-0 = <&pinctrl_i2c1>;
255 clocks = <&peri_clk 5>; 323 clocks = <&peri_clk 5>;
324 resets = <&peri_rst 5>;
256 clock-frequency = <100000>; 325 clock-frequency = <100000>;
257 }; 326 };
258 327
@@ -263,6 +332,7 @@
263 #size-cells = <0>; 332 #size-cells = <0>;
264 interrupts = <0 43 4>; 333 interrupts = <0 43 4>;
265 clocks = <&peri_clk 6>; 334 clocks = <&peri_clk 6>;
335 resets = <&peri_rst 6>;
266 clock-frequency = <400000>; 336 clock-frequency = <400000>;
267 }; 337 };
268 338
@@ -276,6 +346,7 @@
276 pinctrl-names = "default"; 346 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_i2c3>; 347 pinctrl-0 = <&pinctrl_i2c3>;
278 clocks = <&peri_clk 7>; 348 clocks = <&peri_clk 7>;
349 resets = <&peri_rst 7>;
279 clock-frequency = <100000>; 350 clock-frequency = <100000>;
280 }; 351 };
281 352
@@ -289,6 +360,7 @@
289 pinctrl-names = "default"; 360 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_i2c4>; 361 pinctrl-0 = <&pinctrl_i2c4>;
291 clocks = <&peri_clk 8>; 362 clocks = <&peri_clk 8>;
363 resets = <&peri_rst 8>;
292 clock-frequency = <100000>; 364 clock-frequency = <100000>;
293 }; 365 };
294 366
@@ -299,6 +371,7 @@
299 #size-cells = <0>; 371 #size-cells = <0>;
300 interrupts = <0 25 4>; 372 interrupts = <0 25 4>;
301 clocks = <&peri_clk 9>; 373 clocks = <&peri_clk 9>;
374 resets = <&peri_rst 9>;
302 clock-frequency = <400000>; 375 clock-frequency = <400000>;
303 }; 376 };
304 377
@@ -356,9 +429,11 @@
356 pinctrl-names = "default"; 429 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_emmc>; 430 pinctrl-0 = <&pinctrl_emmc>;
358 clocks = <&sys_clk 4>; 431 clocks = <&sys_clk 4>;
432 resets = <&sys_rst 4>;
359 bus-width = <8>; 433 bus-width = <8>;
360 mmc-ddr-1_8v; 434 mmc-ddr-1_8v;
361 mmc-hs200-1_8v; 435 mmc-hs200-1_8v;
436 mmc-pwrseq = <&emmc_pwrseq>;
362 cdns,phy-input-delay-legacy = <4>; 437 cdns,phy-input-delay-legacy = <4>;
363 cdns,phy-input-delay-mmc-highspeed = <2>; 438 cdns,phy-input-delay-mmc-highspeed = <2>;
364 cdns,phy-input-delay-mmc-ddr = <3>; 439 cdns,phy-input-delay-mmc-ddr = <3>;
@@ -376,6 +451,24 @@
376 }; 451 };
377 }; 452 };
378 453
454 soc-glue@5f900000 {
455 compatible = "socionext,uniphier-ld20-soc-glue-debug",
456 "simple-mfd";
457 #address-cells = <1>;
458 #size-cells = <1>;
459 ranges = <0 0x5f900000 0x2000>;
460
461 efuse@100 {
462 compatible = "socionext,uniphier-efuse";
463 reg = <0x100 0x28>;
464 };
465
466 efuse@200 {
467 compatible = "socionext,uniphier-efuse";
468 reg = <0x200 0x68>;
469 };
470 };
471
379 aidet: aidet@5fc20000 { 472 aidet: aidet@5fc20000 {
380 compatible = "socionext,uniphier-ld20-aidet"; 473 compatible = "socionext,uniphier-ld20-aidet";
381 reg = <0x5fc20000 0x200>; 474 reg = <0x5fc20000 0x200>;
@@ -410,6 +503,13 @@
410 watchdog { 503 watchdog {
411 compatible = "socionext,uniphier-wdt"; 504 compatible = "socionext,uniphier-wdt";
412 }; 505 };
506
507 pvtctl: pvtctl {
508 compatible = "socionext,uniphier-ld20-thermal";
509 interrupts = <0 3 4>;
510 #thermal-sensor-cells = <0>;
511 socionext,tmod-calibration = <0x0f22 0x68ee>;
512 };
413 }; 513 };
414 514
415 nand: nand@68000000 { 515 nand: nand@68000000 {
@@ -421,6 +521,7 @@
421 pinctrl-names = "default"; 521 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_nand>; 522 pinctrl-0 = <&pinctrl_nand>;
423 clocks = <&sys_clk 2>; 523 clocks = <&sys_clk 2>;
524 resets = <&sys_rst 2>;
424 }; 525 };
425 }; 526 };
426}; 527};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
index d65f746a3f9d..dad4743fb151 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
@@ -60,3 +60,7 @@
60&i2c3 { 60&i2c3 {
61 status = "okay"; 61 status = "okay";
62}; 62};
63
64&nand {
65 status = "okay";
66};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 384729fa740f..48e733136db4 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -7,6 +7,8 @@
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */ 8 */
9 9
10#include <dt-bindings/gpio/gpio.h>
11
10/memreserve/ 0x80000000 0x02000000; 12/memreserve/ 0x80000000 0x02000000;
11 13
12/ { 14/ {
@@ -73,7 +75,7 @@
73 }; 75 };
74 }; 76 };
75 77
76 cluster0_opp: opp_table { 78 cluster0_opp: opp-table {
77 compatible = "operating-points-v2"; 79 compatible = "operating-points-v2";
78 opp-shared; 80 opp-shared;
79 81
@@ -124,6 +126,11 @@
124 }; 126 };
125 }; 127 };
126 128
129 emmc_pwrseq: emmc-pwrseq {
130 compatible = "mmc-pwrseq-emmc";
131 reset-gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
132 };
133
127 timer { 134 timer {
128 compatible = "arm,armv8-timer"; 135 compatible = "arm,armv8-timer";
129 interrupts = <1 13 4>, 136 interrupts = <1 13 4>,
@@ -146,6 +153,7 @@
146 pinctrl-names = "default"; 153 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_uart0>; 154 pinctrl-0 = <&pinctrl_uart0>;
148 clocks = <&peri_clk 0>; 155 clocks = <&peri_clk 0>;
156 resets = <&peri_rst 0>;
149 }; 157 };
150 158
151 serial1: serial@54006900 { 159 serial1: serial@54006900 {
@@ -156,6 +164,7 @@
156 pinctrl-names = "default"; 164 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_uart1>; 165 pinctrl-0 = <&pinctrl_uart1>;
158 clocks = <&peri_clk 1>; 166 clocks = <&peri_clk 1>;
167 resets = <&peri_rst 1>;
159 }; 168 };
160 169
161 serial2: serial@54006a00 { 170 serial2: serial@54006a00 {
@@ -166,6 +175,7 @@
166 pinctrl-names = "default"; 175 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_uart2>; 176 pinctrl-0 = <&pinctrl_uart2>;
168 clocks = <&peri_clk 2>; 177 clocks = <&peri_clk 2>;
178 resets = <&peri_rst 2>;
169 }; 179 };
170 180
171 serial3: serial@54006b00 { 181 serial3: serial@54006b00 {
@@ -176,6 +186,26 @@
176 pinctrl-names = "default"; 186 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_uart3>; 187 pinctrl-0 = <&pinctrl_uart3>;
178 clocks = <&peri_clk 3>; 188 clocks = <&peri_clk 3>;
189 resets = <&peri_rst 3>;
190 };
191
192 gpio: gpio@55000000 {
193 compatible = "socionext,uniphier-gpio";
194 reg = <0x55000000 0x200>;
195 interrupt-parent = <&aidet>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
198 gpio-controller;
199 #gpio-cells = <2>;
200 gpio-ranges = <&pinctrl 0 0 0>,
201 <&pinctrl 96 0 0>,
202 <&pinctrl 160 0 0>;
203 gpio-ranges-group-names = "gpio_range0",
204 "gpio_range1",
205 "gpio_range2";
206 ngpios = <286>;
207 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
208 <21 217 3>;
179 }; 209 };
180 210
181 i2c0: i2c@58780000 { 211 i2c0: i2c@58780000 {
@@ -188,6 +218,7 @@
188 pinctrl-names = "default"; 218 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_i2c0>; 219 pinctrl-0 = <&pinctrl_i2c0>;
190 clocks = <&peri_clk 4>; 220 clocks = <&peri_clk 4>;
221 resets = <&peri_rst 4>;
191 clock-frequency = <100000>; 222 clock-frequency = <100000>;
192 }; 223 };
193 224
@@ -201,6 +232,7 @@
201 pinctrl-names = "default"; 232 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_i2c1>; 233 pinctrl-0 = <&pinctrl_i2c1>;
203 clocks = <&peri_clk 5>; 234 clocks = <&peri_clk 5>;
235 resets = <&peri_rst 5>;
204 clock-frequency = <100000>; 236 clock-frequency = <100000>;
205 }; 237 };
206 238
@@ -214,6 +246,7 @@
214 pinctrl-names = "default"; 246 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_i2c2>; 247 pinctrl-0 = <&pinctrl_i2c2>;
216 clocks = <&peri_clk 6>; 248 clocks = <&peri_clk 6>;
249 resets = <&peri_rst 6>;
217 clock-frequency = <100000>; 250 clock-frequency = <100000>;
218 }; 251 };
219 252
@@ -227,6 +260,7 @@
227 pinctrl-names = "default"; 260 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_i2c3>; 261 pinctrl-0 = <&pinctrl_i2c3>;
229 clocks = <&peri_clk 7>; 262 clocks = <&peri_clk 7>;
263 resets = <&peri_rst 7>;
230 clock-frequency = <100000>; 264 clock-frequency = <100000>;
231 }; 265 };
232 266
@@ -238,6 +272,7 @@
238 #size-cells = <0>; 272 #size-cells = <0>;
239 interrupts = <0 26 4>; 273 interrupts = <0 26 4>;
240 clocks = <&peri_clk 10>; 274 clocks = <&peri_clk 10>;
275 resets = <&peri_rst 10>;
241 clock-frequency = <400000>; 276 clock-frequency = <400000>;
242 }; 277 };
243 278
@@ -295,9 +330,11 @@
295 pinctrl-names = "default"; 330 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_emmc>; 331 pinctrl-0 = <&pinctrl_emmc>;
297 clocks = <&sys_clk 4>; 332 clocks = <&sys_clk 4>;
333 resets = <&sys_rst 4>;
298 bus-width = <8>; 334 bus-width = <8>;
299 mmc-ddr-1_8v; 335 mmc-ddr-1_8v;
300 mmc-hs200-1_8v; 336 mmc-hs200-1_8v;
337 mmc-pwrseq = <&emmc_pwrseq>;
301 cdns,phy-input-delay-legacy = <4>; 338 cdns,phy-input-delay-legacy = <4>;
302 cdns,phy-input-delay-mmc-highspeed = <2>; 339 cdns,phy-input-delay-mmc-highspeed = <2>;
303 cdns,phy-input-delay-mmc-ddr = <3>; 340 cdns,phy-input-delay-mmc-ddr = <3>;
@@ -315,6 +352,24 @@
315 }; 352 };
316 }; 353 };
317 354
355 soc-glue@5f900000 {
356 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
357 "simple-mfd";
358 #address-cells = <1>;
359 #size-cells = <1>;
360 ranges = <0 0x5f900000 0x2000>;
361
362 efuse@100 {
363 compatible = "socionext,uniphier-efuse";
364 reg = <0x100 0x28>;
365 };
366
367 efuse@200 {
368 compatible = "socionext,uniphier-efuse";
369 reg = <0x200 0x68>;
370 };
371 };
372
318 aidet: aidet@5fc20000 { 373 aidet: aidet@5fc20000 {
319 compatible = "socionext,uniphier-pxs3-aidet"; 374 compatible = "socionext,uniphier-pxs3-aidet";
320 reg = <0x5fc20000 0x200>; 375 reg = <0x5fc20000 0x200>;
@@ -360,6 +415,7 @@
360 pinctrl-names = "default"; 415 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_nand>; 416 pinctrl-0 = <&pinctrl_nand>;
362 clocks = <&sys_clk 2>; 417 clocks = <&sys_clk 2>;
418 resets = <&sys_rst 2>;
363 }; 419 };
364 }; 420 };
365}; 421};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 22:23:43 -0400