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authorFuyun Liang <liangfuyun1@huawei.com>2018-01-12 03:23:15 -0500
committerDavid S. Miller <davem@davemloft.net>2018-01-12 10:12:33 -0500
commit11af96a47beda880e07b6f2f68efaae60794ae78 (patch)
treeb28ac25dd4de9b47311796b7961299697dd7685f
parentb81c59e1f70914b6958fd342608dbc5aa6b487e4 (diff)
net: hns3: add int_gl_idx setup for TX and RX queues
If the int_gl_idx does not be set, the default interrupt coalesce index is 0. The TX queues and the RX queues will both use the GL0 as the interrupt coalesce GL switch. But it should be GL1 for TX queues and GL0 for RX queues. This patch adds the int_gl_idx setup for TX queues and RX queues. Fixes: 76ad4f0ee747 ("net: hns3: Add support of HNS3 Ethernet Driver for hip08 SoC") Signed-off-by: Fuyun Liang <liangfuyun1@huawei.com> Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/hisilicon/hns3/hnae3.h5
-rw-r--r--drivers/net/ethernet/hisilicon/hns3/hns3_enet.c11
-rw-r--r--drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c5
3 files changed, 21 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
index 0bad0e37edbd..634e9327968b 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
@@ -133,11 +133,16 @@ struct hnae3_vector_info {
133#define HNAE3_RING_TYPE_B 0 133#define HNAE3_RING_TYPE_B 0
134#define HNAE3_RING_TYPE_TX 0 134#define HNAE3_RING_TYPE_TX 0
135#define HNAE3_RING_TYPE_RX 1 135#define HNAE3_RING_TYPE_RX 1
136#define HNAE3_RING_GL_IDX_S 0
137#define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
138#define HNAE3_RING_GL_RX 0
139#define HNAE3_RING_GL_TX 1
136 140
137struct hnae3_ring_chain_node { 141struct hnae3_ring_chain_node {
138 struct hnae3_ring_chain_node *next; 142 struct hnae3_ring_chain_node *next;
139 u32 tqp_index; 143 u32 tqp_index;
140 u32 flag; 144 u32 flag;
145 u32 int_gl_idx;
141}; 146};
142 147
143#define HNAE3_IS_TX_RING(node) \ 148#define HNAE3_IS_TX_RING(node) \
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index 2e9e61c1a50d..34879c458309 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -2523,6 +2523,8 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2523 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2523 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
2524 hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2524 hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2525 HNAE3_RING_TYPE_TX); 2525 HNAE3_RING_TYPE_TX);
2526 hnae_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2527 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
2526 2528
2527 cur_chain->next = NULL; 2529 cur_chain->next = NULL;
2528 2530
@@ -2538,6 +2540,10 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2538 chain->tqp_index = tx_ring->tqp->tqp_index; 2540 chain->tqp_index = tx_ring->tqp->tqp_index;
2539 hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2541 hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2540 HNAE3_RING_TYPE_TX); 2542 HNAE3_RING_TYPE_TX);
2543 hnae_set_field(chain->int_gl_idx,
2544 HNAE3_RING_GL_IDX_M,
2545 HNAE3_RING_GL_IDX_S,
2546 HNAE3_RING_GL_TX);
2541 2547
2542 cur_chain = chain; 2548 cur_chain = chain;
2543 } 2549 }
@@ -2549,6 +2555,8 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2549 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 2555 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
2550 hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2556 hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2551 HNAE3_RING_TYPE_RX); 2557 HNAE3_RING_TYPE_RX);
2558 hnae_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2559 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2552 2560
2553 rx_ring = rx_ring->next; 2561 rx_ring = rx_ring->next;
2554 } 2562 }
@@ -2562,6 +2570,9 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2562 chain->tqp_index = rx_ring->tqp->tqp_index; 2570 chain->tqp_index = rx_ring->tqp->tqp_index;
2563 hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2571 hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2564 HNAE3_RING_TYPE_RX); 2572 HNAE3_RING_TYPE_RX);
2573 hnae_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2574 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2575
2565 cur_chain = chain; 2576 cur_chain = chain;
2566 2577
2567 rx_ring = rx_ring->next; 2578 rx_ring = rx_ring->next;
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index d7352f5f75c3..27f0ab695f5a 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -3409,6 +3409,11 @@ int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3409 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B)); 3409 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3410 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 3410 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3411 HCLGE_TQP_ID_S, node->tqp_index); 3411 HCLGE_TQP_ID_S, node->tqp_index);
3412 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3413 HCLGE_INT_GL_IDX_S,
3414 hnae_get_field(node->int_gl_idx,
3415 HNAE3_RING_GL_IDX_M,
3416 HNAE3_RING_GL_IDX_S));
3412 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 3417 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3413 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 3418 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3414 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 3419 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;