diff options
author | Minghuan Lian <Minghuan.Lian@nxp.com> | 2016-02-29 18:24:15 -0500 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-02-29 18:24:15 -0500 |
commit | 1195c103f6c98d9ff381cac3a8760d4f8a133627 (patch) | |
tree | 9ba46aa432943770bfc6495dc5a985f239354a0a | |
parent | 79e3f4a853ed161cd4c06d84b50beebf961a47c6 (diff) |
PCI: layerscape: Fix MSG TLP drop setting
Some kinds of Layerscape PCIe controllers will forward the received message
TLPs to system application address space, which could corrupt system memory
or lead to a system hang. Enable MSG_DROP to fix this issue.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r-- | drivers/pci/host/pci-layerscape.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 3923bed93c7e..f39961bcf7aa 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c | |||
@@ -77,6 +77,16 @@ static void ls_pcie_fix_class(struct ls_pcie *pcie) | |||
77 | iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); | 77 | iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); |
78 | } | 78 | } |
79 | 79 | ||
80 | /* Drop MSG TLP except for Vendor MSG */ | ||
81 | static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) | ||
82 | { | ||
83 | u32 val; | ||
84 | |||
85 | val = ioread32(pcie->dbi + PCIE_STRFMR1); | ||
86 | val &= 0xDFFFFFFF; | ||
87 | iowrite32(val, pcie->dbi + PCIE_STRFMR1); | ||
88 | } | ||
89 | |||
80 | static int ls1021_pcie_link_up(struct pcie_port *pp) | 90 | static int ls1021_pcie_link_up(struct pcie_port *pp) |
81 | { | 91 | { |
82 | u32 state; | 92 | u32 state; |
@@ -97,7 +107,7 @@ static int ls1021_pcie_link_up(struct pcie_port *pp) | |||
97 | static void ls1021_pcie_host_init(struct pcie_port *pp) | 107 | static void ls1021_pcie_host_init(struct pcie_port *pp) |
98 | { | 108 | { |
99 | struct ls_pcie *pcie = to_ls_pcie(pp); | 109 | struct ls_pcie *pcie = to_ls_pcie(pp); |
100 | u32 val, index[2]; | 110 | u32 index[2]; |
101 | 111 | ||
102 | pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node, | 112 | pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node, |
103 | "fsl,pcie-scfg"); | 113 | "fsl,pcie-scfg"); |
@@ -116,13 +126,7 @@ static void ls1021_pcie_host_init(struct pcie_port *pp) | |||
116 | 126 | ||
117 | dw_pcie_setup_rc(pp); | 127 | dw_pcie_setup_rc(pp); |
118 | 128 | ||
119 | /* | 129 | ls_pcie_drop_msg_tlp(pcie); |
120 | * LS1021A Workaround for internal TKT228622 | ||
121 | * to fix the INTx hang issue | ||
122 | */ | ||
123 | val = ioread32(pcie->dbi + PCIE_STRFMR1); | ||
124 | val &= 0xffff; | ||
125 | iowrite32(val, pcie->dbi + PCIE_STRFMR1); | ||
126 | } | 130 | } |
127 | 131 | ||
128 | static int ls_pcie_link_up(struct pcie_port *pp) | 132 | static int ls_pcie_link_up(struct pcie_port *pp) |
@@ -147,6 +151,7 @@ static void ls_pcie_host_init(struct pcie_port *pp) | |||
147 | iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN); | 151 | iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN); |
148 | ls_pcie_fix_class(pcie); | 152 | ls_pcie_fix_class(pcie); |
149 | ls_pcie_clear_multifunction(pcie); | 153 | ls_pcie_clear_multifunction(pcie); |
154 | ls_pcie_drop_msg_tlp(pcie); | ||
150 | iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); | 155 | iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); |
151 | } | 156 | } |
152 | 157 | ||