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authorGeert Uytterhoeven <geert+renesas@glider.be>2016-05-20 03:10:00 -0400
committerSimon Horman <horms+renesas@verge.net.au>2016-05-29 20:37:11 -0400
commit1178814b0fc3649a9c586554e8f6d4f161a97c1f (patch)
treee40d07c462c39e6d8b2862b26330fde4f0b50890
parent34ea4b4a827b4ee76295501b7df61fc904ab8ae3 (diff)
ARM: dts: sh73a0: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /cache-controller has a reg or ranges property, but no unit name Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index c4f434cdec60..032fe2f14b16 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -55,7 +55,7 @@
55 <0xf0000100 0x100>; 55 <0xf0000100 0x100>;
56 }; 56 };
57 57
58 L2: cache-controller { 58 L2: cache-controller@f0100000 {
59 compatible = "arm,pl310-cache"; 59 compatible = "arm,pl310-cache";
60 reg = <0xf0100000 0x1000>; 60 reg = <0xf0100000 0x1000>;
61 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 61 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;