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authorXing Zheng <zhengxing@rock-chips.com>2016-03-28 05:51:37 -0400
committerHeiko Stuebner <heiko@sntech.de>2016-03-28 08:57:07 -0400
commit115510053e5e5872f1f19a2220b04aab5542c5c4 (patch)
tree4ab3c6c8522d91cd2b04313a5dcd9a200cee11a3
parent485a40d7cd4aab5ae939320278809776388f5c06 (diff)
clk: rockchip: add clock controller for the RK3399
Add the clock tree definition for the new RK3399 SoC. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat
-rw-r--r--drivers/clk/rockchip/Makefile1
-rw-r--r--drivers/clk/rockchip/clk-rk3399.c1540
-rw-r--r--drivers/clk/rockchip/clk.h22
3 files changed, 1562 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 80b9a379beb4..f47a2fa962d2 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -15,3 +15,4 @@ obj-y += clk-rk3188.o
15obj-y += clk-rk3228.o 15obj-y += clk-rk3228.o
16obj-y += clk-rk3288.o 16obj-y += clk-rk3288.o
17obj-y += clk-rk3368.o 17obj-y += clk-rk3368.o
18obj-y += clk-rk3399.o
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
new file mode 100644
index 000000000000..356e13256242
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -0,0 +1,1540 @@
1/*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include <dt-bindings/clock/rk3399-cru.h>
22#include "clk.h"
23
24enum rk3399_plls {
25 lpll, bpll, dpll, cpll, gpll, npll, vpll,
26};
27
28enum rk3399_pmu_plls {
29 ppll,
30};
31
32static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
75 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
76 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
80 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
84 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
85 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
86 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
90 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
95 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
96 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
97 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
98 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
99 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
100 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
101 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
102 { /* sentinel */ },
103};
104
105/* CRU parents */
106PNAME(mux_pll_p) = { "xin24m", "xin32k" };
107
108PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
109 "clk_core_l_bpll_src",
110 "clk_core_l_dpll_src",
111 "clk_core_l_gpll_src" };
112PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
113 "clk_core_b_bpll_src",
114 "clk_core_b_dpll_src",
115 "clk_core_b_gpll_src" };
116PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
117 "gpll_aclk_cci_src",
118 "npll_aclk_cci_src",
119 "vpll_aclk_cci_src" };
120PNAME(mux_cci_trace_p) = { "cpll_cci_trace", "gpll_cci_trace" };
121PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", "npll_cs"};
122PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
123
124PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
125PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
126PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
127PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
128PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
129PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", "ppll" };
130PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", "xin24m" };
131PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", "clk_usbphy_480m" };
132PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };
133PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", "upll", "xin24m" };
134PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
135
136PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
137PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", "npll" };
138PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", "xin24m" };
139
140PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", "dclk_vop0_frac" };
141PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", "dclk_vop1_frac" };
142
143PNAME(mux_clk_cif_p) = { "clk_cifout_div", "xin24m" };
144
145PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
146PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
147PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", "cpll", "gpll" };
148PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", "clk_pcie_core_phy" };
149
150PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" };
151
152PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" };
153
154PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", "gpll_fclk_cm0s_src" };
155
156PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" };
157
158PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
159PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
160
161PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", "clk_usbphy1_480m_src" };
162PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" };
163PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
164PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
165 "clkin_i2s", "xin12m" };
166PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
167 "clkin_i2s", "xin12m" };
168PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
169 "clkin_i2s", "xin12m" };
170PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
171 "clkin_i2s", "xin12m" };
172PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", "clk_i2s2" };
173PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
174
175PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
176PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
177PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
178PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
179
180/* PMU CRU parents */
181PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
182PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
183PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
184PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
185PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", "xin24m" };
186PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
187
188static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
189 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
190 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
191 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
192 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
193 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
194 RK3399_PLL_CON(19), 8, 31, 0, NULL),
195 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
196 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
197 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
198 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
199 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
200 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
201 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
202 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
203};
204
205static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
206 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
207 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
208};
209
210#define MFLAGS CLK_MUX_HIWORD_MASK
211#define DFLAGS CLK_DIVIDER_HIWORD_MASK
212#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
213#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
214
215static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
216 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
217 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
218
219static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
220 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
221 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
222
223static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
224 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
225 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
226
227static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
228 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
229 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
230
231static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
232 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
233 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
234
235static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
236 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
237 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
238
239static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
240 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
241 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
242
243static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
244 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
245 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
246
247static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
248 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
249 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
250
251static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
252 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
253 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
254
255static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
256 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
257 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
258
259static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
260 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
261 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
262
263static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
264 .core_reg = RK3399_CLKSEL_CON(0),
265 .div_core_shift = 0,
266 .div_core_mask = 0x1f,
267 .mux_core_alt = 3,
268 .mux_core_main = 0,
269 .mux_core_shift = 6,
270 .mux_core_mask = 0x3,
271};
272
273static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
274 .core_reg = RK3399_CLKSEL_CON(2),
275 .div_core_shift = 0,
276 .div_core_mask = 0x1f,
277 .mux_core_alt = 3,
278 .mux_core_main = 1,
279 .mux_core_shift = 6,
280 .mux_core_mask = 0x3,
281};
282
283#define RK3399_DIV_ACLKM_MASK 0x1f
284#define RK3399_DIV_ACLKM_SHIFT 8
285#define RK3399_DIV_ATCLK_MASK 0x1f
286#define RK3399_DIV_ATCLK_SHIFT 0
287#define RK3399_DIV_PCLK_DBG_MASK 0x1f
288#define RK3399_DIV_PCLK_DBG_SHIFT 8
289
290#define RK3399_CLKSEL0(_offs, _aclkm) \
291 { \
292 .reg = RK3399_CLKSEL_CON(0 + _offs), \
293 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
294 RK3399_DIV_ACLKM_SHIFT), \
295 }
296#define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
297 { \
298 .reg = RK3399_CLKSEL_CON(1 + _offs), \
299 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
300 RK3399_DIV_ATCLK_SHIFT) | \
301 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
302 RK3399_DIV_PCLK_DBG_SHIFT), \
303 }
304
305/* cluster_l: aclkm in clksel0, rest in clksel1 */
306#define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
307 { \
308 .prate = _prate##U, \
309 .divs = { \
310 RK3399_CLKSEL0(0, _aclkm), \
311 RK3399_CLKSEL1(0, _atclk, _pdbg), \
312 }, \
313 }
314
315/* cluster_b: aclkm in clksel2, rest in clksel3 */
316#define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
317 { \
318 .prate = _prate##U, \
319 .divs = { \
320 RK3399_CLKSEL0(2, _aclkm), \
321 RK3399_CLKSEL1(2, _atclk, _pdbg), \
322 }, \
323 }
324
325static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
326 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
327 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
328 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
329 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
330 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
331 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
332 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
333 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
334 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
335 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
336 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
337 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
338 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
339};
340
341static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
342 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
343 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
344 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
345 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
346 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
347 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
348 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
349 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
350 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
351 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
352 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
353 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
354 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
355 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
356 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
357 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
358 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
359 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
360 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
361};
362
363static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
364 /*
365 * CRU Clock-Architecture
366 */
367
368 /* usbphy */
369 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
370 RK3399_CLKGATE_CON(6), 5, GFLAGS),
371 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
372 RK3399_CLKGATE_CON(6), 6, GFLAGS),
373
374 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
375 RK3399_CLKGATE_CON(13), 12, GFLAGS),
376 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
377 RK3399_CLKGATE_CON(13), 12, GFLAGS),
378 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
379 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
380
381 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
382 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
383
384 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, CLK_IGNORE_UNUSED,
385 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
386 RK3399_CLKGATE_CON(6), 4, GFLAGS),
387
388 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
389 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
390 RK3399_CLKGATE_CON(12), 0, GFLAGS),
391 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
392 RK3399_CLKGATE_CON(30), 0, GFLAGS),
393 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLK_IGNORE_UNUSED,
394 RK3399_CLKGATE_CON(30), 1, GFLAGS),
395 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLK_IGNORE_UNUSED,
396 RK3399_CLKGATE_CON(30), 2, GFLAGS),
397 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLK_IGNORE_UNUSED,
398 RK3399_CLKGATE_CON(30), 3, GFLAGS),
399 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLK_IGNORE_UNUSED,
400 RK3399_CLKGATE_CON(30), 4, GFLAGS),
401
402 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLK_IGNORE_UNUSED,
403 RK3399_CLKGATE_CON(12), 1, GFLAGS),
404 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLK_IGNORE_UNUSED,
405 RK3399_CLKGATE_CON(12), 2, GFLAGS),
406
407 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, CLK_IGNORE_UNUSED,
408 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
409 RK3399_CLKGATE_CON(12), 3, GFLAGS),
410
411 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, CLK_IGNORE_UNUSED,
412 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
413 RK3399_CLKGATE_CON(12), 4, GFLAGS),
414
415 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED,
416 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
417 RK3399_CLKGATE_CON(13), 4, GFLAGS),
418
419 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED,
420 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
421 RK3399_CLKGATE_CON(13), 5, GFLAGS),
422
423 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED,
424 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
425 RK3399_CLKGATE_CON(13), 6, GFLAGS),
426
427 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED,
428 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
429 RK3399_CLKGATE_CON(13), 7, GFLAGS),
430
431 /* little core */
432 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
433 RK3399_CLKGATE_CON(0), 0, GFLAGS),
434 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
435 RK3399_CLKGATE_CON(0), 1, GFLAGS),
436 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
437 RK3399_CLKGATE_CON(0), 2, GFLAGS),
438 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
439 RK3399_CLKGATE_CON(0), 3, GFLAGS),
440
441 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
442 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
443 RK3399_CLKGATE_CON(0), 4, GFLAGS),
444 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
445 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
446 RK3399_CLKGATE_CON(0), 5, GFLAGS),
447 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
448 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
449 RK3399_CLKGATE_CON(0), 6, GFLAGS),
450
451 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
452 RK3399_CLKGATE_CON(14), 12, GFLAGS),
453 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
454 RK3399_CLKGATE_CON(14), 13, GFLAGS),
455
456 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
457 RK3399_CLKGATE_CON(14), 9, GFLAGS),
458 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
459 RK3399_CLKGATE_CON(14), 10, GFLAGS),
460 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
461 RK3399_CLKGATE_CON(14), 11, GFLAGS),
462 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED,
463 RK3399_CLKGATE_CON(0), 7, GFLAGS),
464
465 /* big core */
466 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
467 RK3399_CLKGATE_CON(1), 0, GFLAGS),
468 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
469 RK3399_CLKGATE_CON(1), 1, GFLAGS),
470 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
471 RK3399_CLKGATE_CON(1), 2, GFLAGS),
472 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
473 RK3399_CLKGATE_CON(1), 3, GFLAGS),
474
475 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
476 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
477 RK3399_CLKGATE_CON(1), 4, GFLAGS),
478 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
479 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
480 RK3399_CLKGATE_CON(1), 5, GFLAGS),
481 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
482 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
483 RK3399_CLKGATE_CON(1), 6, GFLAGS),
484
485 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
486 RK3399_CLKGATE_CON(14), 5, GFLAGS),
487 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
488 RK3399_CLKGATE_CON(14), 6, GFLAGS),
489
490 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
491 RK3399_CLKGATE_CON(14), 1, GFLAGS),
492 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
493 RK3399_CLKGATE_CON(14), 3, GFLAGS),
494 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
495 RK3399_CLKGATE_CON(14), 4, GFLAGS),
496
497 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
498 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
499
500 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
501 RK3399_CLKGATE_CON(14), 2, GFLAGS),
502
503 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED,
504 RK3399_CLKGATE_CON(1), 7, GFLAGS),
505
506 /* gmac */
507 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
508 RK3399_CLKGATE_CON(6), 9, GFLAGS),
509 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
510 RK3399_CLKGATE_CON(6), 8, GFLAGS),
511 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, CLK_IGNORE_UNUSED,
512 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
513 RK3399_CLKGATE_CON(6), 10, GFLAGS),
514
515 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
516 RK3399_CLKGATE_CON(32), 0, GFLAGS),
517 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
518 RK3399_CLKGATE_CON(32), 1, GFLAGS),
519 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
520 RK3399_CLKGATE_CON(32), 4, GFLAGS),
521
522 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
523 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
524 RK3399_CLKGATE_CON(6), 11, GFLAGS),
525 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
526 RK3399_CLKGATE_CON(32), 2, GFLAGS),
527 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
528 RK3399_CLKGATE_CON(32), 3, GFLAGS),
529
530 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
531 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
532 RK3399_CLKGATE_CON(5), 5, GFLAGS),
533
534 MUX(0, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
535 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
536 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLK_IGNORE_UNUSED,
537 RK3399_CLKGATE_CON(5), 6, GFLAGS),
538 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLK_IGNORE_UNUSED,
539 RK3399_CLKGATE_CON(5), 7, GFLAGS),
540 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLK_IGNORE_UNUSED,
541 RK3399_CLKGATE_CON(5), 8, GFLAGS),
542 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLK_IGNORE_UNUSED,
543 RK3399_CLKGATE_CON(5), 9, GFLAGS),
544
545 /* spdif */
546 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
547 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
548 RK3399_CLKGATE_CON(8), 13, GFLAGS),
549 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
550 RK3399_CLKSEL_CON(99), 0,
551 RK3399_CLKGATE_CON(8), 14, GFLAGS,
552 &rk3399_spdif_fracmux),
553 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
554 RK3399_CLKGATE_CON(8), 15, GFLAGS),
555
556 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
557 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
558 RK3399_CLKGATE_CON(10), 6, GFLAGS),
559 /* i2s */
560 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
561 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
562 RK3399_CLKGATE_CON(8), 3, GFLAGS),
563 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
564 RK3399_CLKSEL_CON(96), 0,
565 RK3399_CLKGATE_CON(8), 4, GFLAGS,
566 &rk3399_i2s0_fracmux),
567 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
568 RK3399_CLKGATE_CON(8), 5, GFLAGS),
569
570 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
571 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
572 RK3399_CLKGATE_CON(8), 6, GFLAGS),
573 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
574 RK3399_CLKSEL_CON(97), 0,
575 RK3399_CLKGATE_CON(8), 7, GFLAGS,
576 &rk3399_i2s1_fracmux),
577 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
578 RK3399_CLKGATE_CON(8), 8, GFLAGS),
579
580 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
581 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
582 RK3399_CLKGATE_CON(8), 9, GFLAGS),
583 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
584 RK3399_CLKSEL_CON(98), 0,
585 RK3399_CLKGATE_CON(8), 10, GFLAGS,
586 &rk3399_i2s2_fracmux),
587 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
588 RK3399_CLKGATE_CON(8), 11, GFLAGS),
589
590 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
591 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
592 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
593 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
594 RK3399_CLKGATE_CON(8), 12, GFLAGS),
595
596 /* uart */
597 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
598 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
599 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
600 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
601 RK3399_CLKGATE_CON(9), 0, GFLAGS),
602 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
603 RK3399_CLKSEL_CON(100), 0,
604 RK3399_CLKGATE_CON(9), 1, GFLAGS,
605 &rk3399_uart0_fracmux),
606
607 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
608 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
609 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
610 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
611 RK3399_CLKGATE_CON(9), 2, GFLAGS),
612 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
613 RK3399_CLKSEL_CON(101), 0,
614 RK3399_CLKGATE_CON(9), 3, GFLAGS,
615 &rk3399_uart1_fracmux),
616
617 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
618 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
619 RK3399_CLKGATE_CON(9), 4, GFLAGS),
620 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
621 RK3399_CLKSEL_CON(102), 0,
622 RK3399_CLKGATE_CON(9), 5, GFLAGS,
623 &rk3399_uart2_fracmux),
624
625 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
626 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
627 RK3399_CLKGATE_CON(9), 6, GFLAGS),
628 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
629 RK3399_CLKSEL_CON(103), 0,
630 RK3399_CLKGATE_CON(9), 7, GFLAGS,
631 &rk3399_uart3_fracmux),
632
633 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
634 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
635 RK3399_CLKGATE_CON(3), 4, GFLAGS),
636
637 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
638 RK3399_CLKGATE_CON(18), 10, GFLAGS),
639 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
640 RK3399_CLKGATE_CON(18), 12, GFLAGS),
641 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
642 RK3399_CLKGATE_CON(18), 15, GFLAGS),
643 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
644 RK3399_CLKGATE_CON(19), 2, GFLAGS),
645
646 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED,
647 RK3399_CLKGATE_CON(4), 11, GFLAGS),
648 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
649 RK3399_CLKGATE_CON(3), 5, GFLAGS),
650 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
651 RK3399_CLKGATE_CON(3), 6, GFLAGS),
652
653 /* cci */
654 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
655 RK3399_CLKGATE_CON(2), 0, GFLAGS),
656 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
657 RK3399_CLKGATE_CON(2), 1, GFLAGS),
658 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
659 RK3399_CLKGATE_CON(2), 2, GFLAGS),
660 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
661 RK3399_CLKGATE_CON(2), 3, GFLAGS),
662
663 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
664 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
665 RK3399_CLKGATE_CON(2), 4, GFLAGS),
666
667 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
668 RK3399_CLKGATE_CON(15), 0, GFLAGS),
669 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
670 RK3399_CLKGATE_CON(15), 1, GFLAGS),
671 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
672 RK3399_CLKGATE_CON(15), 2, GFLAGS),
673 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
674 RK3399_CLKGATE_CON(15), 3, GFLAGS),
675 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
676 RK3399_CLKGATE_CON(15), 4, GFLAGS),
677 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
678 RK3399_CLKGATE_CON(15), 7, GFLAGS),
679
680 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
681 RK3399_CLKGATE_CON(2), 5, GFLAGS),
682 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
683 RK3399_CLKGATE_CON(2), 6, GFLAGS),
684 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
685 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
686 RK3399_CLKGATE_CON(2), 7, GFLAGS),
687
688 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
689 RK3399_CLKGATE_CON(2), 8, GFLAGS),
690 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
691 RK3399_CLKGATE_CON(2), 9, GFLAGS),
692 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
693 RK3399_CLKGATE_CON(2), 10, GFLAGS),
694 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
695 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
696 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
697 RK3399_CLKGATE_CON(15), 5, GFLAGS),
698 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
699 RK3399_CLKGATE_CON(15), 6, GFLAGS),
700
701 /* vcodec */
702 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
703 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
704 RK3399_CLKGATE_CON(4), 0, GFLAGS),
705 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
706 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
707 RK3399_CLKGATE_CON(4), 1, GFLAGS),
708 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
709 RK3399_CLKGATE_CON(17), 2, GFLAGS),
710 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
711 RK3399_CLKGATE_CON(17), 3, GFLAGS),
712
713 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
714 RK3399_CLKGATE_CON(17), 0, GFLAGS),
715 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
716 RK3399_CLKGATE_CON(17), 1, GFLAGS),
717
718 /* vdu */
719 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
720 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
721 RK3399_CLKGATE_CON(4), 4, GFLAGS),
722 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
723 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
724 RK3399_CLKGATE_CON(4), 5, GFLAGS),
725
726 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
727 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
728 RK3399_CLKGATE_CON(4), 2, GFLAGS),
729 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
730 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
731 RK3399_CLKGATE_CON(4), 3, GFLAGS),
732 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
733 RK3399_CLKGATE_CON(17), 10, GFLAGS),
734 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
735 RK3399_CLKGATE_CON(17), 11, GFLAGS),
736
737 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
738 RK3399_CLKGATE_CON(17), 8, GFLAGS),
739 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
740 RK3399_CLKGATE_CON(17), 9, GFLAGS),
741
742 /* iep */
743 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
744 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
745 RK3399_CLKGATE_CON(4), 6, GFLAGS),
746 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
747 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
748 RK3399_CLKGATE_CON(4), 7, GFLAGS),
749 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", CLK_IGNORE_UNUSED,
750 RK3399_CLKGATE_CON(16), 2, GFLAGS),
751 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
752 RK3399_CLKGATE_CON(16), 3, GFLAGS),
753
754 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", CLK_IGNORE_UNUSED,
755 RK3399_CLKGATE_CON(16), 0, GFLAGS),
756 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
757 RK3399_CLKGATE_CON(16), 1, GFLAGS),
758
759 /* rga */
760 COMPOSITE(0, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
761 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
762 RK3399_CLKGATE_CON(4), 10, GFLAGS),
763
764 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
765 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
766 RK3399_CLKGATE_CON(4), 8, GFLAGS),
767 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
768 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
769 RK3399_CLKGATE_CON(4), 9, GFLAGS),
770 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", CLK_IGNORE_UNUSED,
771 RK3399_CLKGATE_CON(16), 10, GFLAGS),
772 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
773 RK3399_CLKGATE_CON(16), 11, GFLAGS),
774
775 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", CLK_IGNORE_UNUSED,
776 RK3399_CLKGATE_CON(16), 8, GFLAGS),
777 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
778 RK3399_CLKGATE_CON(16), 9, GFLAGS),
779
780 /* center */
781 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
782 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
783 RK3399_CLKGATE_CON(3), 7, GFLAGS),
784 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
785 RK3399_CLKGATE_CON(19), 0, GFLAGS),
786 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
787 RK3399_CLKGATE_CON(19), 1, GFLAGS),
788
789 /* gpu */
790 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
791 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
792 RK3399_CLKGATE_CON(13), 0, GFLAGS),
793 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
794 RK3399_CLKGATE_CON(30), 8, GFLAGS),
795 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
796 RK3399_CLKGATE_CON(30), 10, GFLAGS),
797 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
798 RK3399_CLKGATE_CON(30), 11, GFLAGS),
799 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", CLK_IGNORE_UNUSED,
800 RK3399_CLKGATE_CON(13), 1, GFLAGS),
801
802 /* perihp */
803 GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
804 RK3399_CLKGATE_CON(5), 0, GFLAGS),
805 GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
806 RK3399_CLKGATE_CON(5), 1, GFLAGS),
807 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
808 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
809 RK3399_CLKGATE_CON(5), 2, GFLAGS),
810 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
811 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
812 RK3399_CLKGATE_CON(5), 3, GFLAGS),
813 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
814 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
815 RK3399_CLKGATE_CON(5), 4, GFLAGS),
816
817 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
818 RK3399_CLKGATE_CON(20), 2, GFLAGS),
819 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
820 RK3399_CLKGATE_CON(20), 10, GFLAGS),
821 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
822 RK3399_CLKGATE_CON(20), 12, GFLAGS),
823
824 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", CLK_IGNORE_UNUSED,
825 RK3399_CLKGATE_CON(20), 5, GFLAGS),
826 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLK_IGNORE_UNUSED,
827 RK3399_CLKGATE_CON(20), 6, GFLAGS),
828 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", CLK_IGNORE_UNUSED,
829 RK3399_CLKGATE_CON(20), 7, GFLAGS),
830 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLK_IGNORE_UNUSED,
831 RK3399_CLKGATE_CON(20), 8, GFLAGS),
832 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", CLK_IGNORE_UNUSED,
833 RK3399_CLKGATE_CON(20), 9, GFLAGS),
834 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
835 RK3399_CLKGATE_CON(20), 13, GFLAGS),
836 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
837 RK3399_CLKGATE_CON(20), 15, GFLAGS),
838
839 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
840 RK3399_CLKGATE_CON(20), 4, GFLAGS),
841 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLK_IGNORE_UNUSED,
842 RK3399_CLKGATE_CON(20), 11, GFLAGS),
843 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
844 RK3399_CLKGATE_CON(20), 14, GFLAGS),
845 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", CLK_IGNORE_UNUSED,
846 RK3399_CLKGATE_CON(31), 8, GFLAGS),
847
848 /* sdio & sdmmc */
849 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
850 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
851 RK3399_CLKGATE_CON(12), 13, GFLAGS),
852 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLK_IGNORE_UNUSED,
853 RK3399_CLKGATE_CON(33), 8, GFLAGS),
854 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
855 RK3399_CLKGATE_CON(33), 9, GFLAGS),
856
857 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED,
858 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
859 RK3399_CLKGATE_CON(6), 0, GFLAGS),
860
861 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED,
862 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
863 RK3399_CLKGATE_CON(6), 1, GFLAGS),
864
865 MMC(SCLK_SDMMC_DRV, "emmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
866 MMC(SCLK_SDMMC_SAMPLE, "emmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
867
868 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
869 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
870
871 /* pcie */
872 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, CLK_IGNORE_UNUSED,
873 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
874 RK3399_CLKGATE_CON(6), 2, GFLAGS),
875
876 COMPOSITE_NOMUX(0, "clk_pciephy_ref100m", "npll", CLK_IGNORE_UNUSED,
877 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
878 RK3399_CLKGATE_CON(12), 6, GFLAGS),
879 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
880 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
881
882 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
883 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
884 RK3399_CLKGATE_CON(6), 3, GFLAGS),
885 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
886 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
887
888 /* emmc */
889 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, CLK_IGNORE_UNUSED,
890 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
891 RK3399_CLKGATE_CON(6), 14, GFLAGS),
892
893 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
894 RK3399_CLKGATE_CON(6), 12, GFLAGS),
895 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
896 RK3399_CLKGATE_CON(6), 13, GFLAGS),
897 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
898 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
899 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
900 RK3399_CLKGATE_CON(32), 8, GFLAGS),
901 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
902 RK3399_CLKGATE_CON(32), 9, GFLAGS),
903 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
904 RK3399_CLKGATE_CON(32), 10, GFLAGS),
905
906 /* perilp0 */
907 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
908 RK3399_CLKGATE_CON(7), 1, GFLAGS),
909 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
910 RK3399_CLKGATE_CON(7), 0, GFLAGS),
911 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
912 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
913 RK3399_CLKGATE_CON(7), 2, GFLAGS),
914 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
915 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
916 RK3399_CLKGATE_CON(7), 3, GFLAGS),
917 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
918 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
919 RK3399_CLKGATE_CON(7), 4, GFLAGS),
920
921 /* aclk_perilp0 gates */
922 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
923 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
924 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
925 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
926 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
927 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
928 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
929 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
930 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
931 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
932 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
933 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 7, GFLAGS),
934
935 /* hclk_perilp0 gates */
936 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
937 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 5, GFLAGS),
938 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 6, GFLAGS),
939 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 14, GFLAGS),
940 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 15, GFLAGS),
941 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
942
943 /* pclk_perilp0 gates */
944 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
945
946 /* crypto */
947 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
948 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
949 RK3399_CLKGATE_CON(7), 7, GFLAGS),
950
951 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
952 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
953 RK3399_CLKGATE_CON(7), 8, GFLAGS),
954
955 /* cm0s_perilp */
956 GATE(0, "cpll_fclk_cm0s_src", "cpll", CLK_IGNORE_UNUSED,
957 RK3399_CLKGATE_CON(7), 6, GFLAGS),
958 GATE(0, "gpll_fclk_cm0s_src", "gpll", CLK_IGNORE_UNUSED,
959 RK3399_CLKGATE_CON(7), 5, GFLAGS),
960 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, CLK_IGNORE_UNUSED,
961 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
962 RK3399_CLKGATE_CON(7), 9, GFLAGS),
963
964 /* fclk_cm0s gates */
965 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 8, GFLAGS),
966 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 9, GFLAGS),
967 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 10, GFLAGS),
968 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 11, GFLAGS),
969 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
970
971 /* perilp1 */
972 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
973 RK3399_CLKGATE_CON(8), 1, GFLAGS),
974 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
975 RK3399_CLKGATE_CON(8), 0, GFLAGS),
976 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
977 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
978 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
979 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
980 RK3399_CLKGATE_CON(8), 2, GFLAGS),
981
982 /* hclk_perilp1 gates */
983 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
984 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
985 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 0, GFLAGS),
986 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 1, GFLAGS),
987 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 2, GFLAGS),
988 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 3, GFLAGS),
989 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 4, GFLAGS),
990 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 5, GFLAGS),
991 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
992
993 /* pclk_perilp1 gates */
994 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
995 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
996 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
997 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
998 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
999 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1000 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1001 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1002 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1003 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1004 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1005 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1006 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1007 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1008 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1009 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1010 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1011 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1012 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1013 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1014 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1015
1016 /* saradc */
1017 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1018 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1019 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1020
1021 /* tsadc */
1022 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, CLK_IGNORE_UNUSED,
1023 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1024 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1025
1026 /* cif_testout */
1027 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1028 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1029 COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1030 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1031 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1032
1033 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1034 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1035 COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
1036 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1037 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1038
1039 /* vio */
1040 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1041 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1042 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1043 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1044 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1045 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1046
1047 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1048 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1049
1050 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", CLK_IGNORE_UNUSED,
1051 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1052 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", CLK_IGNORE_UNUSED,
1053 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1054 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1055 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1056
1057 /* hdcp */
1058 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1059 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1060 RK3399_CLKGATE_CON(11), 12, GFLAGS),
1061 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED,
1062 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1063 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1064 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED,
1065 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1066 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1067
1068 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1069 RK3399_CLKGATE_CON(29), 4, GFLAGS),
1070 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", CLK_IGNORE_UNUSED,
1071 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1072
1073 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1074 RK3399_CLKGATE_CON(29), 5, GFLAGS),
1075 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", CLK_IGNORE_UNUSED,
1076 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1077
1078 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1079 RK3399_CLKGATE_CON(29), 3, GFLAGS),
1080 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED,
1081 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1082 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED,
1083 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1084 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", CLK_IGNORE_UNUSED,
1085 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1086 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", CLK_IGNORE_UNUSED,
1087 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1088
1089 /* edp */
1090 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1091 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1092 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1093
1094 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1095 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1096 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1097 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1098 RK3399_CLKGATE_CON(32), 12, GFLAGS),
1099 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLK_IGNORE_UNUSED,
1100 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1101
1102 /* hdmi */
1103 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLK_IGNORE_UNUSED,
1104 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1105
1106 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, CLK_IGNORE_UNUSED,
1107 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1108 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1109
1110 /* vop0 */
1111 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1112 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1113 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1114 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1115 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1116 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1117
1118 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1119 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1120 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1121 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1122
1123 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1124 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1125 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1126 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1127
1128 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1129 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1130 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1131
1132 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1133 RK3399_CLKSEL_CON(106), 0,
1134 &rk3399_dclk_vop0_fracmux),
1135
1136 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1137 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1138 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1139
1140 /* vop1 */
1141 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1142 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1143 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1144 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1145 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1146 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1147
1148 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1149 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1150 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1151 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1152
1153 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1154 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1155 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1156 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1157
1158 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1159 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1160 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1161
1162 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1163 RK3399_CLKSEL_CON(107), 0,
1164 &rk3399_dclk_vop1_fracmux),
1165
1166 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1167 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1168 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1169
1170 /* isp */
1171 COMPOSITE(0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1172 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1173 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1174 COMPOSITE_NOMUX(0, "hclk_isp0", "aclk_isp0", 0,
1175 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1176 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1177
1178 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1179 RK3399_CLKGATE_CON(27), 1, GFLAGS),
1180 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED,
1181 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1182 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED,
1183 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1184
1185 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1186 RK3399_CLKGATE_CON(27), 0, GFLAGS),
1187 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", CLK_IGNORE_UNUSED,
1188 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1189
1190 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1191 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1192 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1193
1194 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1195 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1196 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1197 COMPOSITE_NOMUX(0, "hclk_isp1", "aclk_isp1", 0,
1198 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1199 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1200
1201 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1202 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1203
1204 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1205 RK3399_CLKGATE_CON(27), 2, GFLAGS),
1206 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", CLK_IGNORE_UNUSED,
1207 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1208
1209 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1210 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1211 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1212
1213 /*
1214 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1215 * so we ignore the mux and make clocks nodes as following,
1216 *
1217 * pclkin_cifinv --|-------\
1218 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1219 * pclkin_cif --|-------/
1220 */
1221 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", CLK_IGNORE_UNUSED,
1222 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1223
1224 /* cif */
1225 COMPOSITE(0, "clk_cifout_div", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1226 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 0, 5, DFLAGS,
1227 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1228 MUX(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
1229 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS),
1230
1231 /* gic */
1232 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1233 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1234 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1235
1236 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1237 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1238 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1239 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1240 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1241 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1242
1243 /* alive */
1244 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1245 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1246 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1247
1248 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1249 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1250 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1251 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1252 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1253
1254 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1255 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1256 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1257 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1258 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1259 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1260 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1261 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1262 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1263
1264 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1265 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1266
1267 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1268 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1269 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1270 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1271
1272 /* testout */
1273 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1274 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1275 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1276 RK3399_CLKSEL_CON(105), 0,
1277 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1278
1279 DIV(0, "clk_test_24m", "xin24m", 0,
1280 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1281
1282 /* spi */
1283 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1284 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1285 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1286
1287 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1288 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1289 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1290
1291 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1292 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1293 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1294
1295 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1296 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1297 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1298
1299 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1300 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1301 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1302
1303 /* i2c */
1304 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1305 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1306 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1307
1308 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1309 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1310 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1311
1312 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1313 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1314 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1315
1316 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1317 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1318 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1319
1320 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1321 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1322 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1323
1324 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1325 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1326 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1327
1328 /* timer */
1329 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1330 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1331 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1332 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1333 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1334 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1335 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1336 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1337 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1338 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1339 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1340 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1341
1342 /* clk_test */
1343 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1344 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1345 RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
1346 RK3368_CLKGATE_CON(13), 11, GFLAGS),
1347};
1348
1349static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1350 /*
1351 * PMU CRU Clock-Architecture
1352 */
1353
1354 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IGNORE_UNUSED,
1355 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1356
1357 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IGNORE_UNUSED,
1358 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1359
1360 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, CLK_IGNORE_UNUSED,
1361 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1362 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1363
1364 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1365 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1366 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1367
1368 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1369 RK3399_PMU_CLKSEL_CON(7), 0,
1370 &rk3399_pmuclk_wifi_fracmux),
1371
1372 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1373 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1374
1375 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1376 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1377 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1378
1379 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1380 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1381 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1382
1383 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1384 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1385 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1386
1387 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1388 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1389 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1390 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1391
1392 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, CLK_IGNORE_UNUSED,
1393 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1394 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1395
1396 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1397 RK3399_PMU_CLKSEL_CON(6), 0,
1398 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1399 &rk3399_uart4_pmu_fracmux),
1400
1401 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1402 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1403
1404 /* pmu clock gates */
1405 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1406 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1407
1408 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1409
1410 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1411 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1412 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1413 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1414 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1415 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1416 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1417 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1418 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1419 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1420 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1421 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1422 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1423 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1424 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1425 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1426
1427 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1428 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1429 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1430 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1431 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1432};
1433
1434static const char *const rk3399_cru_critical_clocks[] __initconst = {
1435 "aclk_cci_pre",
1436 "pclk_perilp0",
1437 "pclk_perilp0",
1438 "hclk_perilp0",
1439 "hclk_perilp0_noc",
1440 "pclk_perilp1",
1441 "pclk_perilp1_noc",
1442 "pclk_perihp",
1443 "pclk_perihp_noc",
1444 "hclk_perihp",
1445 "aclk_perihp",
1446 "aclk_perihp_noc",
1447 "aclk_perilp0",
1448 "aclk_perilp0_noc",
1449 "hclk_perilp1",
1450 "hclk_perilp1_noc",
1451 "aclk_dmac0_perilp",
1452 "gpll_hclk_perilp1_src",
1453 "gpll_aclk_perilp0_src",
1454 "gpll_aclk_perihp_src",
1455};
1456
1457static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1458 "ppll",
1459 "pclk_pmu_src",
1460 "fclk_cm0s_src_pmu",
1461 "clk_timer_src_pmu",
1462};
1463
1464static void __init rk3399_clk_init(struct device_node *np)
1465{
1466 struct rockchip_clk_provider *ctx;
1467 void __iomem *reg_base;
1468
1469 reg_base = of_iomap(np, 0);
1470 if (!reg_base) {
1471 pr_err("%s: could not map cru region\n", __func__);
1472 return;
1473 }
1474
1475 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1476 if (IS_ERR(ctx)) {
1477 pr_err("%s: rockchip clk init failed\n", __func__);
1478 return;
1479 }
1480
1481 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1482 ARRAY_SIZE(rk3399_pll_clks), -1);
1483
1484 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1485 ARRAY_SIZE(rk3399_clk_branches));
1486
1487 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1488 ARRAY_SIZE(rk3399_cru_critical_clocks));
1489
1490 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1491 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1492 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1493 ARRAY_SIZE(rk3399_cpuclkl_rates));
1494
1495 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1496 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1497 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1498 ARRAY_SIZE(rk3399_cpuclkb_rates));
1499
1500 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1501 ROCKCHIP_SOFTRST_HIWORD_MASK);
1502
1503 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1504
1505 rockchip_clk_of_add_provider(np, ctx);
1506}
1507CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1508
1509static void __init rk3399_pmu_clk_init(struct device_node *np)
1510{
1511 struct rockchip_clk_provider *ctx;
1512 void __iomem *reg_base;
1513
1514 reg_base = of_iomap(np, 0);
1515 if (!reg_base) {
1516 pr_err("%s: could not map cru pmu region\n", __func__);
1517 return;
1518 }
1519
1520 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1521 if (IS_ERR(ctx)) {
1522 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1523 return;
1524 }
1525
1526 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1527 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1528
1529 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1530 ARRAY_SIZE(rk3399_clk_pmu_branches));
1531
1532 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1533 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1534
1535 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1536 ROCKCHIP_SOFTRST_HIWORD_MASK);
1537
1538 rockchip_clk_of_add_provider(np, ctx);
1539}
1540CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index cb6a63963693..880349f6d3d7 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -34,7 +34,7 @@ struct clk;
34#define HIWORD_UPDATE(val, mask, shift) \ 34#define HIWORD_UPDATE(val, mask, shift) \
35 ((val) << (shift) | (mask) << ((shift) + 16)) 35 ((val) << (shift) | (mask) << ((shift) + 16))
36 36
37/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */ 37/* register positions shared by RK2928, RK3036, RK3066, RK3188, RK3228, RK3399 */
38#define RK2928_PLL_CON(x) ((x) * 0x4) 38#define RK2928_PLL_CON(x) ((x) * 0x4)
39#define RK2928_MODE_CON 0x40 39#define RK2928_MODE_CON 0x40
40#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) 40#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
@@ -93,6 +93,26 @@ struct clk;
93#define RK3368_EMMC_CON0 0x418 93#define RK3368_EMMC_CON0 0x418
94#define RK3368_EMMC_CON1 0x41c 94#define RK3368_EMMC_CON1 0x41c
95 95
96#define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
97#define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
98#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
99#define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
100#define RK3399_GLB_SRST_FST 0x500
101#define RK3399_GLB_SRST_SND 0x504
102#define RK3399_GLB_CNT_TH 0x508
103#define RK3399_MISC_CON 0x50c
104#define RK3399_RST_CON 0x510
105#define RK3399_RST_ST 0x514
106#define RK3399_SDMMC_CON0 0x580
107#define RK3399_SDMMC_CON1 0x584
108#define RK3399_SDIO_CON0 0x588
109#define RK3399_SDIO_CON1 0x58c
110
111#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
112#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
113#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
114#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
115
96enum rockchip_pll_type { 116enum rockchip_pll_type {
97 pll_rk3036, 117 pll_rk3036,
98 pll_rk3066, 118 pll_rk3066,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-26 22:52:16 -0400