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authorArvind Yadav <arvind.yadav.cs@gmail.com>2016-09-20 07:46:55 -0400
committerStephen Boyd <sboyd@codeaurora.org>2016-12-08 19:34:15 -0500
commit113ff9c99a6926047e279cdf4479c186b41c5eae (patch)
tree5059b881790c29dbfdc936f7e413f7832b4b5ae6
parent81ba3cc29a03b2cd9360739014b7d8ade88a9863 (diff)
clk: keystone: pll: Unmap region obtained by of_iomap
Free memory mapping, if of_pll_div_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r--drivers/clk/keystone/pll.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
index 185f19c6836e..e7e840fb74ea 100644
--- a/drivers/clk/keystone/pll.c
+++ b/drivers/clk/keystone/pll.c
@@ -267,25 +267,30 @@ static void __init of_pll_div_clk_init(struct device_node *node)
267 parent_name = of_clk_get_parent_name(node, 0); 267 parent_name = of_clk_get_parent_name(node, 0);
268 if (!parent_name) { 268 if (!parent_name) {
269 pr_err("%s: missing parent clock\n", __func__); 269 pr_err("%s: missing parent clock\n", __func__);
270 iounmap(reg);
270 return; 271 return;
271 } 272 }
272 273
273 if (of_property_read_u32(node, "bit-shift", &shift)) { 274 if (of_property_read_u32(node, "bit-shift", &shift)) {
274 pr_err("%s: missing 'shift' property\n", __func__); 275 pr_err("%s: missing 'shift' property\n", __func__);
276 iounmap(reg);
275 return; 277 return;
276 } 278 }
277 279
278 if (of_property_read_u32(node, "bit-mask", &mask)) { 280 if (of_property_read_u32(node, "bit-mask", &mask)) {
279 pr_err("%s: missing 'bit-mask' property\n", __func__); 281 pr_err("%s: missing 'bit-mask' property\n", __func__);
282 iounmap(reg);
280 return; 283 return;
281 } 284 }
282 285
283 clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, 286 clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
284 mask, 0, NULL); 287 mask, 0, NULL);
285 if (clk) 288 if (clk) {
286 of_clk_add_provider(node, of_clk_src_simple_get, clk); 289 of_clk_add_provider(node, of_clk_src_simple_get, clk);
287 else 290 } else {
288 pr_err("%s: error registering divider %s\n", __func__, clk_name); 291 pr_err("%s: error registering divider %s\n", __func__, clk_name);
292 iounmap(reg);
293 }
289} 294}
290CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init); 295CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init);
291 296