diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-05-09 04:45:45 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-05-23 13:04:46 -0400 |
| commit | 111c7751e3f86bdfe7256741281709afe22bba71 (patch) | |
| tree | e84605e1fe43356aefc1f6efcf97a783cb2f62c2 | |
| parent | 29d668d260a5a022eaad1cc91fea08d02deb45b1 (diff) | |
ARM: omap1: convert to using readl/writel instead of volatile struct
Tested-by: Tony Lindgren <tony@atomide.com>
Cc: linux-omap@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | arch/arm/mach-omap1/time.c | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index e2c29b477c95..e7ab61625b44 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c | |||
| @@ -68,49 +68,50 @@ typedef struct { | |||
| 68 | } omap_mpu_timer_regs_t; | 68 | } omap_mpu_timer_regs_t; |
| 69 | 69 | ||
| 70 | #define omap_mpu_timer_base(n) \ | 70 | #define omap_mpu_timer_base(n) \ |
| 71 | ((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ | 71 | ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ |
| 72 | (n)*OMAP_MPU_TIMER_OFFSET)) | 72 | (n)*OMAP_MPU_TIMER_OFFSET)) |
| 73 | 73 | ||
| 74 | static inline unsigned long notrace omap_mpu_timer_read(int nr) | 74 | static inline unsigned long notrace omap_mpu_timer_read(int nr) |
| 75 | { | 75 | { |
| 76 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); | 76 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
| 77 | return timer->read_tim; | 77 | return readl(&timer->read_tim); |
| 78 | } | 78 | } |
| 79 | 79 | ||
| 80 | static inline void omap_mpu_set_autoreset(int nr) | 80 | static inline void omap_mpu_set_autoreset(int nr) |
| 81 | { | 81 | { |
| 82 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); | 82 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
| 83 | 83 | ||
| 84 | timer->cntl = timer->cntl | MPU_TIMER_AR; | 84 | writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); |
| 85 | } | 85 | } |
| 86 | 86 | ||
| 87 | static inline void omap_mpu_remove_autoreset(int nr) | 87 | static inline void omap_mpu_remove_autoreset(int nr) |
| 88 | { | 88 | { |
| 89 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); | 89 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
| 90 | 90 | ||
| 91 | timer->cntl = timer->cntl & ~MPU_TIMER_AR; | 91 | writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); |
| 92 | } | 92 | } |
| 93 | 93 | ||
| 94 | static inline void omap_mpu_timer_start(int nr, unsigned long load_val, | 94 | static inline void omap_mpu_timer_start(int nr, unsigned long load_val, |
| 95 | int autoreset) | 95 | int autoreset) |
| 96 | { | 96 | { |
| 97 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); | 97 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
| 98 | unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST); | 98 | unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST; |
| 99 | 99 | ||
| 100 | if (autoreset) timerflags |= MPU_TIMER_AR; | 100 | if (autoreset) |
| 101 | timerflags |= MPU_TIMER_AR; | ||
| 101 | 102 | ||
| 102 | timer->cntl = MPU_TIMER_CLOCK_ENABLE; | 103 | writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); |
| 103 | udelay(1); | 104 | udelay(1); |
| 104 | timer->load_tim = load_val; | 105 | writel(load_val, &timer->load_tim); |
| 105 | udelay(1); | 106 | udelay(1); |
| 106 | timer->cntl = timerflags; | 107 | writel(timerflags, &timer->cntl); |
| 107 | } | 108 | } |
| 108 | 109 | ||
| 109 | static inline void omap_mpu_timer_stop(int nr) | 110 | static inline void omap_mpu_timer_stop(int nr) |
| 110 | { | 111 | { |
| 111 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); | 112 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
| 112 | 113 | ||
| 113 | timer->cntl &= ~MPU_TIMER_ST; | 114 | writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); |
| 114 | } | 115 | } |
| 115 | 116 | ||
| 116 | /* | 117 | /* |
