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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2019-03-13 07:58:25 -0400
committerAndy Shevchenko <andriy.shevchenko@linux.intel.com>2019-04-03 07:49:47 -0400
commit10d64c871c309afb2403a3fadf5ff3ab7d96d8ed (patch)
treeb2fa869861a10acade198c0a1231d070da7ae645
parentd6cb77228e3ae070061195a6fff6ba7c3c0b8e47 (diff)
pinctrl: cedarfork: Update pin names according to v1.13c
Version 1.13c of pin list has some changes in pin names for Intel Cedarfork. Update the driver accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linar.org>
-rw-r--r--drivers/pinctrl/intel/pinctrl-cedarfork.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-cedarfork.c b/drivers/pinctrl/intel/pinctrl-cedarfork.c
index b7d632f1dbf6..aa6f9040d3d8 100644
--- a/drivers/pinctrl/intel/pinctrl-cedarfork.c
+++ b/drivers/pinctrl/intel/pinctrl-cedarfork.c
@@ -91,13 +91,13 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
91 PINCTRL_PIN(43, "MEMTRIP_N"), 91 PINCTRL_PIN(43, "MEMTRIP_N"),
92 PINCTRL_PIN(44, "UART0_RXD"), 92 PINCTRL_PIN(44, "UART0_RXD"),
93 PINCTRL_PIN(45, "UART0_TXD"), 93 PINCTRL_PIN(45, "UART0_TXD"),
94 PINCTRL_PIN(46, "UART1_RXD"), 94 PINCTRL_PIN(46, "GBE_UART_RXD"),
95 PINCTRL_PIN(47, "UART1_TXD"), 95 PINCTRL_PIN(47, "GBE_UART_TXD"),
96 /* WEST01 */ 96 /* WEST01 */
97 PINCTRL_PIN(48, "GBE_GPIO13"), 97 PINCTRL_PIN(48, "GBE_GPIO13"),
98 PINCTRL_PIN(49, "AUX_PWR"), 98 PINCTRL_PIN(49, "AUX_PWR"),
99 PINCTRL_PIN(50, "CPU_GP_2"), 99 PINCTRL_PIN(50, "UART0_RTS"),
100 PINCTRL_PIN(51, "CPU_GP_3"), 100 PINCTRL_PIN(51, "UART0_CTS"),
101 PINCTRL_PIN(52, "FAN_PWM_0"), 101 PINCTRL_PIN(52, "FAN_PWM_0"),
102 PINCTRL_PIN(53, "FAN_PWM_1"), 102 PINCTRL_PIN(53, "FAN_PWM_1"),
103 PINCTRL_PIN(54, "FAN_PWM_2"), 103 PINCTRL_PIN(54, "FAN_PWM_2"),
@@ -201,8 +201,8 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
201 /* WESTF */ 201 /* WESTF */
202 PINCTRL_PIN(145, "NAC_RMII_CLK"), 202 PINCTRL_PIN(145, "NAC_RMII_CLK"),
203 PINCTRL_PIN(146, "NAC_RGMII_CLK"), 203 PINCTRL_PIN(146, "NAC_RGMII_CLK"),
204 PINCTRL_PIN(147, "NAC_SPARE0"), 204 PINCTRL_PIN(147, "NAC_GBE_SMB_CLK_TX_N2S"),
205 PINCTRL_PIN(148, "NAC_SPARE1"), 205 PINCTRL_PIN(148, "NAC_GBE_SMB_DATA_TX_N2S"),
206 PINCTRL_PIN(149, "NAC_SPARE2"), 206 PINCTRL_PIN(149, "NAC_SPARE2"),
207 PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"), 207 PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"),
208 PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"), 208 PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"),
@@ -219,8 +219,8 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
219 PINCTRL_PIN(162, "NAC_NCSI_TXD1"), 219 PINCTRL_PIN(162, "NAC_NCSI_TXD1"),
220 PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"), 220 PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"),
221 PINCTRL_PIN(164, "NAC_NCSI_OE_N"), 221 PINCTRL_PIN(164, "NAC_NCSI_OE_N"),
222 PINCTRL_PIN(165, "NAC_GBE_SMB_CLK"), 222 PINCTRL_PIN(165, "NAC_GBE_SMB_CLK_RX_S2N"),
223 PINCTRL_PIN(166, "NAC_GBE_SMB_DATA"), 223 PINCTRL_PIN(166, "NAC_GBE_SMB_DATA_RX_S2N"),
224 PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"), 224 PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"),
225 /* EAST2 */ 225 /* EAST2 */
226 PINCTRL_PIN(168, "USB_OC0_N"), 226 PINCTRL_PIN(168, "USB_OC0_N"),
@@ -232,7 +232,7 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
232 PINCTRL_PIN(174, "GBE_GPIO5"), 232 PINCTRL_PIN(174, "GBE_GPIO5"),
233 PINCTRL_PIN(175, "GBE_GPIO6"), 233 PINCTRL_PIN(175, "GBE_GPIO6"),
234 PINCTRL_PIN(176, "GBE_GPIO7"), 234 PINCTRL_PIN(176, "GBE_GPIO7"),
235 PINCTRL_PIN(177, "GBE_GPIO8"), 235 PINCTRL_PIN(177, "SPI_TPM_CS_N"),
236 PINCTRL_PIN(178, "GBE_GPIO9"), 236 PINCTRL_PIN(178, "GBE_GPIO9"),
237 PINCTRL_PIN(179, "GBE_GPIO10"), 237 PINCTRL_PIN(179, "GBE_GPIO10"),
238 PINCTRL_PIN(180, "GBE_GPIO11"), 238 PINCTRL_PIN(180, "GBE_GPIO11"),