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authorFrederick Lawler <fred@fredlawl.com>2019-05-07 19:24:47 -0400
committerBjorn Helgaas <bhelgaas@google.com>2019-05-09 17:27:34 -0400
commit10a9990c10447a7bfe9dc016629898814741d090 (patch)
treece276a28a2203c20f39ee52aaafb2ac5779046da
parent00ebf1348cb332941dab52948f29480592bfbe6a (diff)
PCI/DPC: Log messages with pci_dev, not pcie_device
Log messages with pci_dev, not pcie_device. Factor out common message prefixes with dev_fmt(). Example output change: - dpc 0000:00:01.1:pcie008: DPC error containment capabilities... + pcieport 0000:00:01.1: DPC: error containment capabilities... Link: https://lore.kernel.org/lkml/20190509141456.223614-4-helgaas@kernel.org Signed-off-by: Frederick Lawler <fred@fredlawl.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com>
-rw-r--r--drivers/pci/pcie/dpc.c37
1 files changed, 18 insertions, 19 deletions
diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
index 7b77754a82de..a32ec3487a8d 100644
--- a/drivers/pci/pcie/dpc.c
+++ b/drivers/pci/pcie/dpc.c
@@ -6,6 +6,8 @@
6 * Copyright (C) 2016 Intel Corp. 6 * Copyright (C) 2016 Intel Corp.
7 */ 7 */
8 8
9#define dev_fmt(fmt) "DPC: " fmt
10
9#include <linux/aer.h> 11#include <linux/aer.h>
10#include <linux/delay.h> 12#include <linux/delay.h>
11#include <linux/interrupt.h> 13#include <linux/interrupt.h>
@@ -100,7 +102,6 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
100{ 102{
101 unsigned long timeout = jiffies + HZ; 103 unsigned long timeout = jiffies + HZ;
102 struct pci_dev *pdev = dpc->dev->port; 104 struct pci_dev *pdev = dpc->dev->port;
103 struct device *dev = &dpc->dev->device;
104 u16 cap = dpc->cap_pos, status; 105 u16 cap = dpc->cap_pos, status;
105 106
106 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 107 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
@@ -110,7 +111,7 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
110 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 111 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
111 } 112 }
112 if (status & PCI_EXP_DPC_RP_BUSY) { 113 if (status & PCI_EXP_DPC_RP_BUSY) {
113 dev_warn(dev, "DPC root port still busy\n"); 114 pci_warn(pdev, "root port still busy\n");
114 return -EBUSY; 115 return -EBUSY;
115 } 116 }
116 return 0; 117 return 0;
@@ -148,7 +149,6 @@ static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
148 149
149static void dpc_process_rp_pio_error(struct dpc_dev *dpc) 150static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
150{ 151{
151 struct device *dev = &dpc->dev->device;
152 struct pci_dev *pdev = dpc->dev->port; 152 struct pci_dev *pdev = dpc->dev->port;
153 u16 cap = dpc->cap_pos, dpc_status, first_error; 153 u16 cap = dpc->cap_pos, dpc_status, first_error;
154 u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix; 154 u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
@@ -156,13 +156,13 @@ static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
156 156
157 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status); 157 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
158 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask); 158 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
159 dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n", 159 pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
160 status, mask); 160 status, mask);
161 161
162 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev); 162 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
163 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr); 163 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
164 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc); 164 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
165 dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n", 165 pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
166 sev, syserr, exc); 166 sev, syserr, exc);
167 167
168 /* Get First Error Pointer */ 168 /* Get First Error Pointer */
@@ -171,7 +171,7 @@ static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
171 171
172 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) { 172 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
173 if ((status & ~mask) & (1 << i)) 173 if ((status & ~mask) & (1 << i))
174 dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i], 174 pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
175 first_error == i ? " (First)" : ""); 175 first_error == i ? " (First)" : "");
176 } 176 }
177 177
@@ -185,18 +185,18 @@ static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
185 &dw2); 185 &dw2);
186 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12, 186 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
187 &dw3); 187 &dw3);
188 dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n", 188 pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
189 dw0, dw1, dw2, dw3); 189 dw0, dw1, dw2, dw3);
190 190
191 if (dpc->rp_log_size < 5) 191 if (dpc->rp_log_size < 5)
192 goto clear_status; 192 goto clear_status;
193 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log); 193 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
194 dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log); 194 pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
195 195
196 for (i = 0; i < dpc->rp_log_size - 5; i++) { 196 for (i = 0; i < dpc->rp_log_size - 5; i++) {
197 pci_read_config_dword(pdev, 197 pci_read_config_dword(pdev,
198 cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix); 198 cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
199 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix); 199 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
200 } 200 }
201 clear_status: 201 clear_status:
202 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status); 202 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
@@ -229,18 +229,17 @@ static irqreturn_t dpc_handler(int irq, void *context)
229 struct aer_err_info info; 229 struct aer_err_info info;
230 struct dpc_dev *dpc = context; 230 struct dpc_dev *dpc = context;
231 struct pci_dev *pdev = dpc->dev->port; 231 struct pci_dev *pdev = dpc->dev->port;
232 struct device *dev = &dpc->dev->device;
233 u16 cap = dpc->cap_pos, status, source, reason, ext_reason; 232 u16 cap = dpc->cap_pos, status, source, reason, ext_reason;
234 233
235 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 234 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
236 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source); 235 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
237 236
238 dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n", 237 pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
239 status, source); 238 status, source);
240 239
241 reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1; 240 reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
242 ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5; 241 ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
243 dev_warn(dev, "DPC %s detected\n", 242 pci_warn(pdev, "%s detected\n",
244 (reason == 0) ? "unmasked uncorrectable error" : 243 (reason == 0) ? "unmasked uncorrectable error" :
245 (reason == 1) ? "ERR_NONFATAL" : 244 (reason == 1) ? "ERR_NONFATAL" :
246 (reason == 2) ? "ERR_FATAL" : 245 (reason == 2) ? "ERR_FATAL" :
@@ -307,7 +306,7 @@ static int dpc_probe(struct pcie_device *dev)
307 dpc_handler, IRQF_SHARED, 306 dpc_handler, IRQF_SHARED,
308 "pcie-dpc", dpc); 307 "pcie-dpc", dpc);
309 if (status) { 308 if (status) {
310 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq, 309 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
311 status); 310 status);
312 return status; 311 return status;
313 } 312 }
@@ -319,7 +318,7 @@ static int dpc_probe(struct pcie_device *dev)
319 if (dpc->rp_extensions) { 318 if (dpc->rp_extensions) {
320 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8; 319 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
321 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) { 320 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
322 dev_err(device, "RP PIO log size %u is invalid\n", 321 pci_err(pdev, "RP PIO log size %u is invalid\n",
323 dpc->rp_log_size); 322 dpc->rp_log_size);
324 dpc->rp_log_size = 0; 323 dpc->rp_log_size = 0;
325 } 324 }
@@ -328,11 +327,11 @@ static int dpc_probe(struct pcie_device *dev)
328 ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; 327 ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
329 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl); 328 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
330 329
331 dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", 330 pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
332 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT), 331 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
333 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP), 332 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
334 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size, 333 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
335 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE)); 334 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
336 335
337 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16)); 336 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
338 return status; 337 return status;